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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fcbltlr.cgs] - Blame information for rev 816

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# frv testcase for fcbltlr $FCCi,$ccond,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fcbltlr
fcbltlr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbltlr         fcc0,0,0
 
        set_spr_addr    bad,lr
        set_fcc         0x1 1
        fcbltlr         fcc1,0,1
 
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbltlr         fcc2,0,2
 
        set_spr_addr    bad,lr
        set_fcc         0x3 3
        fcbltlr         fcc3,0,3
 
        set_spr_addr    ok5,lr
        set_fcc         0x4 0
        fcbltlr         fcc0,0,0
        fail
ok5:
        set_spr_addr    ok6,lr
        set_fcc         0x5 1
        fcbltlr         fcc1,0,1
        fail
ok6:
        set_spr_addr    ok7,lr
        set_fcc         0x6 2
        fcbltlr         fcc2,0,2
        fail
ok7:
        set_spr_addr    ok8,lr
        set_fcc         0x7 3
        fcbltlr         fcc3,0,3
        fail
ok8:
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbltlr         fcc0,0,0
 
        set_spr_addr    bad,lr
        set_fcc         0x9 1
        fcbltlr         fcc1,0,1
 
        set_spr_addr    bad,lr
        set_fcc         0xa 2
        fcbltlr         fcc2,0,2
 
        set_spr_addr    bad,lr
        set_fcc         0xb 3
        fcbltlr         fcc3,0,3
 
        set_spr_addr    okd,lr
        set_fcc         0xc 0
        fcbltlr         fcc0,0,0
        fail
okd:
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        fcbltlr         fcc1,0,1
        fail
oke:
        set_spr_addr    okf,lr
        set_fcc         0xe 2
        fcbltlr         fcc2,0,2
        fail
okf:
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        fcbltlr         fcc3,0,3
        fail
okg:
 
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbltlr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x1 1
        fcbltlr         fcc1,1,1
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbltlr         fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x3 3
        fcbltlr         fcc3,1,3
 
        set_spr_immed   1,lcr
        set_spr_addr    okl,lr
        set_fcc         0x4 0
        fcbltlr         fcc0,1,0
        fail
okl:
        set_spr_immed   1,lcr
        set_spr_addr    okm,lr
        set_fcc         0x5 1
        fcbltlr         fcc1,1,1
        fail
okm:
        set_spr_immed   1,lcr
        set_spr_addr    okn,lr
        set_fcc         0x6 2
        fcbltlr         fcc2,1,2
        fail
okn:
        set_spr_immed   1,lcr
        set_spr_addr    oko,lr
        set_fcc         0x7 3
        fcbltlr         fcc3,1,3
        fail
oko:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbltlr         fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x9 1
        fcbltlr         fcc1,1,1
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0xa 2
        fcbltlr         fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0xb 3
        fcbltlr         fcc3,1,3
 
        set_spr_immed   1,lcr
        set_spr_addr    okt,lr
        set_fcc         0xc 0
        fcbltlr         fcc0,1,0
        fail
okt:
        set_spr_immed   1,lcr
        set_spr_addr    oku,lr
        set_fcc         0xd 1
        fcbltlr         fcc1,1,1
        fail
oku:
        set_spr_immed   1,lcr
        set_spr_addr    okv,lr
        set_fcc         0xe 2
        fcbltlr         fcc2,1,2
        fail
okv:
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_fcc         0xf 3
        fcbltlr         fcc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
 
        set_fcc         0x0 0
        fcbltlr fcc0,1,0
        set_fcc         0x1 1
        fcbltlr fcc1,1,1
        set_fcc         0x2 2
        fcbltlr fcc2,1,2
        set_fcc         0x3 3
        fcbltlr fcc3,1,3
        set_fcc         0x4 0
        fcbltlr fcc0,1,0
        set_fcc         0x5 1
        fcbltlr fcc1,1,1
        set_fcc         0x6 2
        fcbltlr fcc2,1,2
        set_fcc         0x7 3
        fcbltlr fcc3,1,3
        set_fcc         0x8 0
        fcbltlr fcc0,1,0
        set_fcc         0x9 1
        fcbltlr fcc1,1,1
        set_fcc         0xa 2
        fcbltlr fcc2,1,2
        set_fcc         0xb 3
        fcbltlr fcc3,1,3
        set_fcc         0xc 0
        fcbltlr fcc0,1,0
        set_fcc         0xd 1
        fcbltlr fcc1,1,1
        set_fcc         0xe 2
        fcbltlr fcc2,1,2
        set_fcc         0xf 3
        fcbltlr fcc3,1,3
 
        ; ccond is false
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        fcbltlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        fcbltlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        fcbltlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        fcbltlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        fcbltlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        fcbltlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        fcbltlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        fcbltlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        fcbltlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        fcbltlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        fcbltlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        fcbltlr fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        fcbltlr fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        fcbltlr fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        fcbltlr fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        fcbltlr fcc3,0,3
 
        pass
bad:
        fail

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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fcbltlr.cgs] - Blame information for rev 816

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for fcbltlr $FCCi,$ccond,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fcbltlr`
9			`fcbltlr:`
10			`; ccond is true`
11			`set_spr_immed 128,lcr`
12			`set_spr_addr bad,lr`
13			`set_fcc 0x0 0`
14			`fcbltlr fcc0,0,0`
15
16			`set_spr_addr bad,lr`
17			`set_fcc 0x1 1`
18			`fcbltlr fcc1,0,1`
19
20			`set_spr_addr bad,lr`
21			`set_fcc 0x2 2`
22			`fcbltlr fcc2,0,2`
23
24			`set_spr_addr bad,lr`
25			`set_fcc 0x3 3`
26			`fcbltlr fcc3,0,3`
27
28			`set_spr_addr ok5,lr`
29			`set_fcc 0x4 0`
30			`fcbltlr fcc0,0,0`
31			`fail`
32			`ok5:`
33			`set_spr_addr ok6,lr`
34			`set_fcc 0x5 1`
35			`fcbltlr fcc1,0,1`
36			`fail`
37			`ok6:`
38			`set_spr_addr ok7,lr`
39			`set_fcc 0x6 2`
40			`fcbltlr fcc2,0,2`
41			`fail`
42			`ok7:`
43			`set_spr_addr ok8,lr`
44			`set_fcc 0x7 3`
45			`fcbltlr fcc3,0,3`
46			`fail`
47			`ok8:`
48			`set_spr_addr bad,lr`
49			`set_fcc 0x8 0`
50			`fcbltlr fcc0,0,0`
51
52			`set_spr_addr bad,lr`
53			`set_fcc 0x9 1`
54			`fcbltlr fcc1,0,1`
55
56			`set_spr_addr bad,lr`
57			`set_fcc 0xa 2`
58			`fcbltlr fcc2,0,2`
59
60			`set_spr_addr bad,lr`
61			`set_fcc 0xb 3`
62			`fcbltlr fcc3,0,3`
63
64			`set_spr_addr okd,lr`
65			`set_fcc 0xc 0`
66			`fcbltlr fcc0,0,0`
67			`fail`
68			`okd:`
69			`set_spr_addr oke,lr`
70			`set_fcc 0xd 1`
71			`fcbltlr fcc1,0,1`
72			`fail`
73			`oke:`
74			`set_spr_addr okf,lr`
75			`set_fcc 0xe 2`
76			`fcbltlr fcc2,0,2`
77			`fail`
78			`okf:`
79			`set_spr_addr okg,lr`
80			`set_fcc 0xf 3`
81			`fcbltlr fcc3,0,3`
82			`fail`
83			`okg:`
84
85			`; ccond is true`
86			`set_spr_immed 1,lcr`
87			`set_spr_addr bad,lr`
88			`set_fcc 0x0 0`
89			`fcbltlr fcc0,1,0`
90
91			`set_spr_immed 1,lcr`
92			`set_spr_addr bad,lr`
93			`set_fcc 0x1 1`
94			`fcbltlr fcc1,1,1`
95
96			`set_spr_immed 1,lcr`
97			`set_spr_addr bad,lr`
98			`set_fcc 0x2 2`
99			`fcbltlr fcc2,1,2`
100
101			`set_spr_immed 1,lcr`
102			`set_spr_addr bad,lr`
103			`set_fcc 0x3 3`
104			`fcbltlr fcc3,1,3`
105
106			`set_spr_immed 1,lcr`
107			`set_spr_addr okl,lr`
108			`set_fcc 0x4 0`
109			`fcbltlr fcc0,1,0`
110			`fail`
111			`okl:`
112			`set_spr_immed 1,lcr`
113			`set_spr_addr okm,lr`
114			`set_fcc 0x5 1`
115			`fcbltlr fcc1,1,1`
116			`fail`
117			`okm:`
118			`set_spr_immed 1,lcr`
119			`set_spr_addr okn,lr`
120			`set_fcc 0x6 2`
121			`fcbltlr fcc2,1,2`
122			`fail`
123			`okn:`
124			`set_spr_immed 1,lcr`
125			`set_spr_addr oko,lr`
126			`set_fcc 0x7 3`
127			`fcbltlr fcc3,1,3`
128			`fail`
129			`oko:`
130			`set_spr_immed 1,lcr`
131			`set_spr_addr bad,lr`
132			`set_fcc 0x8 0`
133			`fcbltlr fcc0,1,0`
134
135			`set_spr_immed 1,lcr`
136			`set_spr_addr bad,lr`
137			`set_fcc 0x9 1`
138			`fcbltlr fcc1,1,1`
139
140			`set_spr_immed 1,lcr`
141			`set_spr_addr bad,lr`
142			`set_fcc 0xa 2`
143			`fcbltlr fcc2,1,2`
144
145			`set_spr_immed 1,lcr`
146			`set_spr_addr bad,lr`
147			`set_fcc 0xb 3`
148			`fcbltlr fcc3,1,3`
149
150			`set_spr_immed 1,lcr`
151			`set_spr_addr okt,lr`
152			`set_fcc 0xc 0`
153			`fcbltlr fcc0,1,0`
154			`fail`
155			`okt:`
156			`set_spr_immed 1,lcr`
157			`set_spr_addr oku,lr`
158			`set_fcc 0xd 1`
159			`fcbltlr fcc1,1,1`
160			`fail`
161			`oku:`
162			`set_spr_immed 1,lcr`
163			`set_spr_addr okv,lr`
164			`set_fcc 0xe 2`
165			`fcbltlr fcc2,1,2`
166			`fail`
167			`okv:`
168			`set_spr_immed 1,lcr`
169			`set_spr_addr okw,lr`
170			`set_fcc 0xf 3`
171			`fcbltlr fcc3,1,3`
172			`fail`
173			`okw:`
174			`; ccond is false`
175			`set_spr_immed 128,lcr`
176
177			`set_fcc 0x0 0`
178			`fcbltlr fcc0,1,0`
179			`set_fcc 0x1 1`
180			`fcbltlr fcc1,1,1`
181			`set_fcc 0x2 2`
182			`fcbltlr fcc2,1,2`
183			`set_fcc 0x3 3`
184			`fcbltlr fcc3,1,3`
185			`set_fcc 0x4 0`
186			`fcbltlr fcc0,1,0`
187			`set_fcc 0x5 1`
188			`fcbltlr fcc1,1,1`
189			`set_fcc 0x6 2`
190			`fcbltlr fcc2,1,2`
191			`set_fcc 0x7 3`
192			`fcbltlr fcc3,1,3`
193			`set_fcc 0x8 0`
194			`fcbltlr fcc0,1,0`
195			`set_fcc 0x9 1`
196			`fcbltlr fcc1,1,1`
197			`set_fcc 0xa 2`
198			`fcbltlr fcc2,1,2`
199			`set_fcc 0xb 3`
200			`fcbltlr fcc3,1,3`
201			`set_fcc 0xc 0`
202			`fcbltlr fcc0,1,0`
203			`set_fcc 0xd 1`
204			`fcbltlr fcc1,1,1`
205			`set_fcc 0xe 2`
206			`fcbltlr fcc2,1,2`
207			`set_fcc 0xf 3`
208			`fcbltlr fcc3,1,3`
209
210			`; ccond is false`
211			`set_spr_immed 1,lcr`
212			`set_fcc 0x0 0`
213			`fcbltlr fcc0,0,0`
214			`set_spr_immed 1,lcr`
215			`set_fcc 0x1 1`
216			`fcbltlr fcc1,0,1`
217			`set_spr_immed 1,lcr`
218			`set_fcc 0x2 2`
219			`fcbltlr fcc2,0,2`
220			`set_spr_immed 1,lcr`
221			`set_fcc 0x3 3`
222			`fcbltlr fcc3,0,3`
223			`set_spr_immed 1,lcr`
224			`set_fcc 0x4 0`
225			`fcbltlr fcc0,0,0`
226			`set_spr_immed 1,lcr`
227			`set_fcc 0x5 1`
228			`fcbltlr fcc1,0,1`
229			`set_spr_immed 1,lcr`
230			`set_fcc 0x6 2`
231			`fcbltlr fcc2,0,2`
232			`set_spr_immed 1,lcr`
233			`set_fcc 0x7 3`
234			`fcbltlr fcc3,0,3`
235			`set_spr_immed 1,lcr`
236			`set_fcc 0x8 0`
237			`fcbltlr fcc0,0,0`
238			`set_spr_immed 1,lcr`
239			`set_fcc 0x9 1`
240			`fcbltlr fcc1,0,1`
241			`set_spr_immed 1,lcr`
242			`set_fcc 0xa 2`
243			`fcbltlr fcc2,0,2`
244			`set_spr_immed 1,lcr`
245			`set_fcc 0xb 3`
246			`fcbltlr fcc3,0,3`
247			`set_spr_immed 1,lcr`
248			`set_fcc 0xc 0`
249			`fcbltlr fcc0,0,0`
250			`set_spr_immed 1,lcr`
251			`set_fcc 0xd 1`
252			`fcbltlr fcc1,0,1`
253			`set_spr_immed 1,lcr`
254			`set_fcc 0xe 2`
255			`fcbltlr fcc2,0,2`
256			`set_spr_immed 1,lcr`
257			`set_fcc 0xf 3`
258			`fcbltlr fcc3,0,3`
259
260			`pass`
261			`bad:`
262			`fail`