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# frv testcase for fckuge $FCCi,$CCj_float
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fckuge
fckuge:
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x0 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1b9b,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x1 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x2 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x3 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x4 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1b9b,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x5 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x6 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x7 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x8 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0x9 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xa 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xb 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xc 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xd 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xe 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        set_spr_immed   0x1b1b,cccr
        set_fcc         0xf 0
        fckuge          fcc0,cc3
        test_spr_immed  0x1bdb,cccr
 
        pass

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for fckuge $FCCi,$CCj_float`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fckuge`
9			`fckuge:`
10			`set_spr_immed 0x1b1b,cccr`
11			`set_fcc 0x0 0`
12			`fckuge fcc0,cc3`
13			`test_spr_immed 0x1b9b,cccr`
14
15			`set_spr_immed 0x1b1b,cccr`
16			`set_fcc 0x1 0`
17			`fckuge fcc0,cc3`
18			`test_spr_immed 0x1bdb,cccr`
19
20			`set_spr_immed 0x1b1b,cccr`
21			`set_fcc 0x2 0`
22			`fckuge fcc0,cc3`
23			`test_spr_immed 0x1bdb,cccr`
24
25			`set_spr_immed 0x1b1b,cccr`
26			`set_fcc 0x3 0`
27			`fckuge fcc0,cc3`
28			`test_spr_immed 0x1bdb,cccr`
29
30			`set_spr_immed 0x1b1b,cccr`
31			`set_fcc 0x4 0`
32			`fckuge fcc0,cc3`
33			`test_spr_immed 0x1b9b,cccr`
34
35			`set_spr_immed 0x1b1b,cccr`
36			`set_fcc 0x5 0`
37			`fckuge fcc0,cc3`
38			`test_spr_immed 0x1bdb,cccr`
39
40			`set_spr_immed 0x1b1b,cccr`
41			`set_fcc 0x6 0`
42			`fckuge fcc0,cc3`
43			`test_spr_immed 0x1bdb,cccr`
44
45			`set_spr_immed 0x1b1b,cccr`
46			`set_fcc 0x7 0`
47			`fckuge fcc0,cc3`
48			`test_spr_immed 0x1bdb,cccr`
49
50			`set_spr_immed 0x1b1b,cccr`
51			`set_fcc 0x8 0`
52			`fckuge fcc0,cc3`
53			`test_spr_immed 0x1bdb,cccr`
54
55			`set_spr_immed 0x1b1b,cccr`
56			`set_fcc 0x9 0`
57			`fckuge fcc0,cc3`
58			`test_spr_immed 0x1bdb,cccr`
59
60			`set_spr_immed 0x1b1b,cccr`
61			`set_fcc 0xa 0`
62			`fckuge fcc0,cc3`
63			`test_spr_immed 0x1bdb,cccr`
64
65			`set_spr_immed 0x1b1b,cccr`
66			`set_fcc 0xb 0`
67			`fckuge fcc0,cc3`
68			`test_spr_immed 0x1bdb,cccr`
69
70			`set_spr_immed 0x1b1b,cccr`
71			`set_fcc 0xc 0`
72			`fckuge fcc0,cc3`
73			`test_spr_immed 0x1bdb,cccr`
74
75			`set_spr_immed 0x1b1b,cccr`
76			`set_fcc 0xd 0`
77			`fckuge fcc0,cc3`
78			`test_spr_immed 0x1bdb,cccr`
79
80			`set_spr_immed 0x1b1b,cccr`
81			`set_fcc 0xe 0`
82			`fckuge fcc0,cc3`
83			`test_spr_immed 0x1bdb,cccr`
84
85			`set_spr_immed 0x1b1b,cccr`
86			`set_fcc 0xf 0`
87			`fckuge fcc0,cc3`
88			`test_spr_immed 0x1bdb,cccr`
89
90			`pass`

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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fckuge.cgs] - Blame information for rev 330