OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [ftigt.cgs] - Blame information for rev 841

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# frv testcase for ftigt $FCCi_2,$GRi,$s12
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global ftigt
9
ftigt:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_gr_immed    0,gr7
17
 
18
        set_spr_addr    bad,lr
19
        set_fcc         0x0 0
20
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
21
 
22
        set_spr_addr    bad,lr
23
        set_fcc         0x1 0
24
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
25
 
26
        set_psr_et      1
27
        set_spr_addr    ok2,lr
28
        set_fcc         0x2 0
29
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
30
        fail
31
ok2:
32
        set_psr_et      1
33
        set_spr_addr    ok3,lr
34
        set_fcc         0x3 0
35
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
36
        fail
37
ok3:
38
        set_spr_addr    bad,lr
39
        set_fcc         0x4 0
40
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
41
 
42
        set_spr_addr    bad,lr
43
        set_fcc         0x5 0
44
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
45
 
46
        set_psr_et      1
47
        set_spr_addr    ok6,lr
48
        set_fcc         0x6 0
49
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
50
        fail
51
ok6:
52
        set_psr_et      1
53
        set_spr_addr    ok7,lr
54
        set_fcc         0x7 0
55
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
56
        fail
57
ok7:
58
        set_spr_addr    bad,lr
59
        set_fcc         0x8 0
60
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
61
 
62
        set_spr_addr    bad,lr
63
        set_fcc         0x9 0
64
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
65
 
66
        set_psr_et      1
67
        set_spr_addr    oka,lr
68
        set_fcc         0xa 0
69
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
70
        fail
71
oka:
72
        set_psr_et      1
73
        set_spr_addr    okb,lr
74
        set_fcc         0xb 0
75
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
76
        fail
77
okb:
78
        set_spr_addr    bad,lr
79
        set_fcc         0xc 0
80
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
81
 
82
        set_spr_addr    bad,lr
83
        set_fcc         0xd 0
84
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
85
 
86
        set_psr_et      1
87
        set_spr_addr    oke,lr
88
        set_fcc         0xe 0
89
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
90
        fail
91
oke:
92
        set_psr_et      1
93
        set_spr_addr    okf,lr
94
        set_fcc         0xf 0
95
        ftigt           fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
96
        fail
97
okf:
98
        pass
99
bad:
100
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.