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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [h8300/] [brabc.s] - Blame information for rev 841

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1 330 jeremybenn 
# Hitachi H8 testcase 'bra/bc'
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# mach(): h8sx
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# as(h8300):    --defsym sim_cpu=0
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# as(h8300h):   --defsym sim_cpu=1
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# as(h8300s):   --defsym sim_cpu=2
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# as(h8sx):     --defsym sim_cpu=3
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# ld(h8300h):   -m h8300helf
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# ld(h8300s):   -m h8300self
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# ld(h8sx):     -m h8300sxelf
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        .include "testutils.inc"
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        .data
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byte_src:       .byte   0xa5
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        start
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.if (sim_cpu == h8sx)
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brabc_ind_disp8:
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        set_grs_a5a5
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        mov     #byte_src, er1
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        set_ccr_zero
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        ;; bra/bc xx:3, @erd, disp8
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        bra/bc  #1, @er1, .Lpass1:8
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;;;     .word   0x7c10
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;;;     .word   0x4110
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        fail
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.Lpass1:
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        bra/bc  #2, @er1, .Lfail1:8
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;;;     .word   0x7c10
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;;;     .word   0x4202
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        bra     .Lpass2
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.Lfail1:
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        fail
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.Lpass2:
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        test_cc_clear
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        test_h_gr32 0xa5a5a5a5 er0
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        test_h_gr32 byte_src   er1
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        test_h_gr32 0xa5a5a5a5 er2
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        test_h_gr32 0xa5a5a5a5 er3
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        test_h_gr32 0xa5a5a5a5 er4
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        test_h_gr32 0xa5a5a5a5 er5
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        test_h_gr32 0xa5a5a5a5 er6
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        test_h_gr32 0xa5a5a5a5 er7
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brabc_abs8_disp16:
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        set_grs_a5a5
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        mov.b   #0xa5, @0x20:32
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        set_ccr_zero
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        ;; bra/bc xx:3, @aa:8, disp16
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        bra/bc  #1, @0x20:8, .Lpass3:16
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        fail
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.Lpass3:
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        bra/bc  #2, @0x20:8, Lfail:16
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        test_cc_clear
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        test_grs_a5a5
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brabc_abs16_disp16:
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        set_grs_a5a5
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        set_ccr_zero
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        ;; bra/bc xx:3, @aa:16, disp16
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        bra/bc  #1, @byte_src:16, .Lpass5:16
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        fail
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.Lpass5:
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        bra/bc  #2, @byte_src:16, Lfail:16
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        test_cc_clear
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        test_grs_a5a5
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brabs_ind_disp8:
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        set_grs_a5a5
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        mov     #byte_src, er1
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        set_ccr_zero
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        ;; bra/bs xx:3, @erd, disp8
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        bra/bs  #2, @er1, .Lpass7:8
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;;;     .word   0x7c10
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;;;     .word   0x4a10
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        fail
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.Lpass7:
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        bra/bs  #1, @er1, .Lfail3:8
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;;;     .word   0x7c10
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;;;     .word   0x4902
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        bra     .Lpass8
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.Lfail3:
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        fail
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.Lpass8:
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        test_cc_clear
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        test_h_gr32 0xa5a5a5a5 er0
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        test_h_gr32 byte_src   er1
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        test_h_gr32 0xa5a5a5a5 er2
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        test_h_gr32 0xa5a5a5a5 er3
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        test_h_gr32 0xa5a5a5a5 er4
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        test_h_gr32 0xa5a5a5a5 er5
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        test_h_gr32 0xa5a5a5a5 er6
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        test_h_gr32 0xa5a5a5a5 er7
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brabs_abs32_disp16:
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        set_grs_a5a5
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        set_ccr_zero
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        ;; bra/bs xx:3, @aa:32, disp16
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        bra/bs  #2, @byte_src:32, .Lpass9:16
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        fail
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.Lpass9:
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        bra/bs  #1, @byte_src:32, Lfail:16
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        test_cc_clear
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        test_grs_a5a5
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.endif
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        pass
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        exit 0
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Lfail:  fail

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