URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [m32r/] [stb.cgs] - Blame information for rev 835

Go to most recent revision | Details | Compare with Previous | View Log


# m32r testcase for stb $src1,@$src2
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global stb
stb:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 0x1234
 
        stb r5, @r4
 
        ld r4, @r4
        test_h_gr r4, 0x34000000 ; big endian processor
 
        pass
 
data_loc:
        .word 0

Line No.	Rev	Author	Line
1	330	jeremybenn	`# m32r testcase for stb $src1,@$src2`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global stb`
9			`stb:`
10			`mvaddr_h_gr r4, data_loc`
11			`mvi_h_gr r5, 0x1234`
12
13			`stb r5, @r4`
14
15			`ld r4, @r4`
16			`test_h_gr r4, 0x34000000 ; big endian processor`
17
18			`pass`
19
20			`data_loc:`
21			`.word 0`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [m32r/] [stb.cgs] - Blame information for rev 835