OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [fipr.s] - Blame information for rev 841

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# sh testcase for fipr $fvm, $fvn
2
# mach: sh
3
# as(sh):       -defsym sim_cpu=0
4
 
5
        .include "testutils.inc"
6
 
7
        start
8
initv0:
9
        set_grs_a5a5
10
        set_fprs_a5a5
11
        # Load 1 into fr0.
12
        fldi1   fr0
13
        # Load 2 into fr1.
14
        fldi1   fr1
15
        fadd    fr1, fr1
16
        # Load 4 into fr2.
17
        fldi1   fr2
18
        fadd    fr2, fr2
19
        fadd    fr2, fr2
20
        # Load 8 into fr3.
21
        fmov    fr2, fr3
22
        fadd    fr2, fr3
23
 
24
initv8:
25
        fldi1   fr8
26
        fldi0   fr9
27
        fldi1   fr10
28
        fldi0   fr11
29
 
30
        fipr    fv0, fv8
31
test1:
32
        # Result will be in fr11.
33
        assert_fpreg_i  1, fr0
34
        assert_fpreg_i  2, fr1
35
        assert_fpreg_i  4, fr2
36
        assert_fpreg_i  8, fr3
37
        assert_fpreg_x  0xa5a5a5a5, fr4
38
        assert_fpreg_x  0xa5a5a5a5, fr5
39
        assert_fpreg_x  0xa5a5a5a5, fr6
40
        assert_fpreg_x  0xa5a5a5a5, fr7
41
        assert_fpreg_i  1, fr8
42
        assert_fpreg_i  0, fr9
43
        assert_fpreg_i  1, fr10
44
        assert_fpreg_i  5, fr11
45
        assert_fpreg_x  0xa5a5a5a5, fr12
46
        assert_fpreg_x  0xa5a5a5a5, fr13
47
        assert_fpreg_x  0xa5a5a5a5, fr14
48
        assert_fpreg_x  0xa5a5a5a5, fr15
49
 
50
        test_grs_a5a5
51
test_infp:
52
        # Test positive infinity
53
        fldi0   fr11
54
        mov.l   infp, r0
55
        lds     r0, fpul
56
        fsts    fpul, fr0
57
        fipr    fv0, fv8
58
        # fr11 should be plus infinity
59
        assert_fpreg_x  0x7f800000, fr11
60
test_infm:
61
        # Test negitive infinity
62
        fldi0   fr11
63
        mov.l   infm, r0
64
        lds     r0, fpul
65
        fsts    fpul, fr0
66
        fipr    fv0, fv8
67
        # fr11 should be plus infinity
68
        assert_fpreg_x  0xff800000, fr11
69
test_qnanp:
70
        # Test positive qnan
71
        fldi0   fr11
72
        mov.l   qnanp, r0
73
        lds     r0, fpul
74
        fsts    fpul, fr0
75
        fipr    fv0, fv8
76
        # fr11 should be plus qnan (or greater)
77
        flds    fr11, fpul
78
        sts     fpul, r1
79
        cmp/ge  r0, r1
80
        bt      .L0
81
        fail
82
.L0:
83
test_snanp:
84
        # Test positive snan
85
        fldi0   fr11
86
        mov.l   snanp, r0
87
        lds     r0, fpul
88
        fsts    fpul, fr0
89
        fipr    fv0, fv8
90
        # fr11 should be plus snan (or greater)
91
        flds    fr11, fpul
92
        sts     fpul, r1
93
        cmp/ge  r0, r1
94
        bt      .L1
95
        fail
96
.L1:
97
.if 0
98
        # Handling of nan and inf not implemented yet.
99
test_qnanm:
100
        # Test negantive qnan
101
        fldi0   fr11
102
        mov.l   qnanm, r0
103
        lds     r0, fpul
104
        fsts    fpul, fr0
105
        fipr    fv0, fv8
106
        # fr11 should be minus qnan (or less)
107
        flds    fr11, fpul
108
        sts     fpul, r1
109
        cmp/ge  r1, r0
110
        bt      .L2
111
        fail
112
.L2:
113
test_snanm:
114
        # Test negative snan
115
        fldi0   fr11
116
        mov.l   snanm, r0
117
        lds     r0, fpul
118
        fsts    fpul, fr0
119
        fipr    fv0, fv8
120
        # fr11 should be minus snan (or less)
121
        flds    fr11, fpul
122
        sts     fpul, r1
123
        cmp/ge  r1, r0
124
        bt      .L3
125
        fail
126
.L3:
127
.endif
128
        pass
129
        exit 0
130
 
131
        .align 2
132
qnanp:  .long   0x7f800001
133
qnanm:  .long   0xff800001
134
snanp:  .long   0x7fc00000
135
snanm:  .long   0xffc00000
136
infp:   .long   0x7f800000
137
infm:   .long   0xff800000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.