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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [fsca.s] - Blame information for rev 841

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1 330 jeremybenn 
# sh testcase for fsca
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# mach: sh
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# as(sh):       -defsym sim_cpu=0
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        .include "testutils.inc"
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        start
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fsca:
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        set_grs_a5a5
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        set_fprs_a5a5
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        # Start with angle zero
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        mov.l   zero, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 0, fr2
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        assert_fpreg_i 1, fr3
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        mov.l   plus_90, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 1, fr2
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        assert_fpreg_i 0, fr3
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        mov.l   plus_180, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 0, fr2
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        assert_fpreg_i -1, fr3
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        mov.l   plus_270, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i -1, fr2
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        assert_fpreg_i 0, fr3
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        mov.l   plus_360, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 0, fr2
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        assert_fpreg_i 1, fr3
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        mov.l   minus_90, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i -1, fr2
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        assert_fpreg_i 0, fr3
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        mov.l   minus_180, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 0, fr2
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        assert_fpreg_i -1, fr3
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        mov.l   minus_270, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 1, fr2
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        assert_fpreg_i 0, fr3
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        mov.l   minus_360, r0
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        lds     r0, fpul
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        fsca    fpul, dr2
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        assert_fpreg_i 0, fr2
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        assert_fpreg_i 1, fr3
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        assertreg0      0xffff0000
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        set_greg        0xa5a5a5a5, r0
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        test_grs_a5a5
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        test_fpr_a5a5   fr0
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        test_fpr_a5a5   fr1
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        test_fpr_a5a5   fr4
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        test_fpr_a5a5   fr5
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        test_fpr_a5a5   fr6
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        test_fpr_a5a5   fr7
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        test_fpr_a5a5   fr8
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        test_fpr_a5a5   fr9
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        test_fpr_a5a5   fr10
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        test_fpr_a5a5   fr11
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        test_fpr_a5a5   fr12
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        test_fpr_a5a5   fr13
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        test_fpr_a5a5   fr14
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        test_fpr_a5a5   fr15
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        pass
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        exit 0
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                .align 2
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zero:           .long   0
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one_bitty:      .long   1
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plus_90:        .long   0x04000
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plus_180:       .long   0x08000
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plus_270:       .long   0x0c000
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plus_360:       .long   0x10000
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minus_90:       .long   0xffffc000
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minus_180:      .long   0xffff8000
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minus_270:      .long   0xffff4000
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minus_360:      .long   0xffff0000
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minus_1_bitty:  .long   0xffffffff

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