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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [loop.s] - Blame information for rev 841

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# sh testcase for loop control
# mach:  shdsp
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
loop1:
        set_grs_a5a5
 
        ldrs    Loop1_start0+8
        ldre    Loop1_start0+4
        setrc   #5
Loop1_start0:
        add     #1, r1  ! Before loop
        # Loop should execute one instruction five times.
Loop1_begin:
        add     #1, r1  ! Within loop
Loop1_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
        assertreg       0xa5a5a5a5+8, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop2:
        set_grs_a5a5
 
        ldrs    Loop2_start0+6
        ldre    Loop2_start0+4
        setrc   #5
Loop2_start0:
        add     #1, r1  ! Before loop
        # Loop should execute two instructions five times.
Loop2_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop2_end:
        add     #3, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
        assertreg       0xa5a5a5a5+14, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop3:
        set_grs_a5a5
 
        ldrs    Loop3_start0+4
        ldre    Loop3_start0+4
        setrc   #5
Loop3_start0:
        add     #1, r1  ! Before loop
        # Loop should execute three instructions five times.
Loop3_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop3_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
        assertreg       0xa5a5a5a5+18, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop4:
        set_grs_a5a5
 
        ldrs    Loop4_begin
        ldre    Loop4_last3+4
        setrc   #5
        add     #1, r1  ! Before loop
        # Loop should execute four instructions five times.
Loop4_begin:
Loop4_last3:
        add     #1, r1  ! Within loop
Loop4_last2:
        add     #1, r1  ! Within loop
Loop4_last1:
        add     #1, r1  ! Within loop
Loop4_last:
        add     #1, r1  ! Within loop
Loop4_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
        assertreg       0xa5a5a5a5+23, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop5:
        set_grs_a5a5
 
        ldrs    Loop5_begin
        ldre    Loop5_last3+4
        setrc   #5
        add     #1, r1  ! Before loop
        # Loop should execute five instructions five times.
Loop5_begin:
        add     #1, r1  ! Within loop
Loop5_last3:
        add     #1, r1  ! Within loop
Loop5_last2:
        add     #1, r1  ! Within loop
Loop5_last1:
        add     #1, r1  ! Within loop
Loop5_last:
        add     #1, r1  ! Within loop
Loop5_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
        assertreg       0xa5a5a5a5+28, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loopn:
        set_grs_a5a5
 
        ldrs    Loopn_begin
        ldre    Loopn_last3+4
        setrc   #5
        add     #1, r1  ! Before loop
        # Loop should execute n instructions five times.
Loopn_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loopn_last3:
        add     #1, r1  ! Within loop
Loopn_last2:
        add     #1, r1  ! Within loop
Loopn_last1:
        add     #1, r1  ! Within loop
Loopn_last:
        add     #1, r1  ! Within loop
Loopn_end:
        add     #3, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
        assertreg       0xa5a5a5a5+64, r1
 
        set_greg 0xa5a5a5a5, r0
        set_greg 0xa5a5a5a5, r1
        test_grs_a5a5
 
loop1e:
        set_grs_a5a5
 
        ldrs    Loop1e_begin
        ldre    Loop1e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute one instruction five times.
Loop1e_begin:
Loop1e_last:
        add     #1, r1  ! Within loop
Loop1e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
        assertreg       0xa5a5a5a5+8, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop2e:
        set_grs_a5a5
 
        ldrs    Loop2e_begin
        ldre    Loop2e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute two instructions five times.
Loop2e_begin:
        add     #1, r1  ! Within loop
Loop2e_last:
        add     #1, r1  ! Within loop
Loop2e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
        assertreg       0xa5a5a5a5+13, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop3e:
        set_grs_a5a5
 
        ldrs    Loop3e_begin
        ldre    Loop3e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute three instructions five times.
Loop3e_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop3e_last:
        add     #1, r1  ! Within loop
Loop3e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
        assertreg       0xa5a5a5a5+18, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop4e:
        set_grs_a5a5
 
        ldrs    Loop4e_begin
        ldre    Loop4e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute four instructions five times.
Loop4e_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop4e_last:
        add     #1, r1  ! Within loop
Loop4e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
        assertreg       0xa5a5a5a5+23, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop5e:
        set_grs_a5a5
 
        ldrs    Loop5e_begin
        ldre    Loop5e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute five instructions five times.
Loop5e_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop5e_last:
        add     #1, r1  ! Within loop
Loop5e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
        assertreg       0xa5a5a5a5+28, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
loop_n_e:
        set_grs_a5a5
 
        ldrs    Loop_n_e_begin
        ldre    Loop_n_e_last
        ldrc    #5
        add     #1, r1  ! Before loop
        # Loop should execute n instructions five times.
Loop_n_e_begin:
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
        add     #1, r1  ! Within loop
Loop_n_e_last:
        add     #1, r1  ! Within loop
Loop_n_e_end:
        add     #2, r1  ! After loop
 
        # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
        assertreg       0xa5a5a5a5+48, r1
 
        set_greg        0xa5a5a5a5, r0
        set_greg        0xa5a5a5a5, r1
        test_grs_a5a5
 
        pass
 
        exit 0
 

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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [loop.s] - Blame information for rev 841

Line No.	Rev	Author	Line
1	330	jeremybenn	`# sh testcase for loop control`
2			`# mach: shdsp`
3			`# as(shdsp): -defsym sim_cpu=1 -dsp`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`loop1:`
9			`set_grs_a5a5`
10
11			`ldrs Loop1_start0+8`
12			`ldre Loop1_start0+4`
13			`setrc #5`
14			`Loop1_start0:`
15			`add #1, r1 ! Before loop`
16			`# Loop should execute one instruction five times.`
17			`Loop1_begin:`
18			`add #1, r1 ! Within loop`
19			`Loop1_end:`
20			`add #2, r1 ! After loop`
21
22			`# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)`
23			`assertreg 0xa5a5a5a5+8, r1`
24
25			`set_greg 0xa5a5a5a5, r0`
26			`set_greg 0xa5a5a5a5, r1`
27			`test_grs_a5a5`
28
29			`loop2:`
30			`set_grs_a5a5`
31
32			`ldrs Loop2_start0+6`
33			`ldre Loop2_start0+4`
34			`setrc #5`
35			`Loop2_start0:`
36			`add #1, r1 ! Before loop`
37			`# Loop should execute two instructions five times.`
38			`Loop2_begin:`
39			`add #1, r1 ! Within loop`
40			`add #1, r1 ! Within loop`
41			`Loop2_end:`
42			`add #3, r1 ! After loop`
43
44			`# r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)`
45			`assertreg 0xa5a5a5a5+14, r1`
46
47			`set_greg 0xa5a5a5a5, r0`
48			`set_greg 0xa5a5a5a5, r1`
49			`test_grs_a5a5`
50
51			`loop3:`
52			`set_grs_a5a5`
53
54			`ldrs Loop3_start0+4`
55			`ldre Loop3_start0+4`
56			`setrc #5`
57			`Loop3_start0:`
58			`add #1, r1 ! Before loop`
59			`# Loop should execute three instructions five times.`
60			`Loop3_begin:`
61			`add #1, r1 ! Within loop`
62			`add #1, r1 ! Within loop`
63			`add #1, r1 ! Within loop`
64			`Loop3_end:`
65			`add #2, r1 ! After loop`
66
67			`# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)`
68			`assertreg 0xa5a5a5a5+18, r1`
69
70			`set_greg 0xa5a5a5a5, r0`
71			`set_greg 0xa5a5a5a5, r1`
72			`test_grs_a5a5`
73
74			`loop4:`
75			`set_grs_a5a5`
76
77			`ldrs Loop4_begin`
78			`ldre Loop4_last3+4`
79			`setrc #5`
80			`add #1, r1 ! Before loop`
81			`# Loop should execute four instructions five times.`
82			`Loop4_begin:`
83			`Loop4_last3:`
84			`add #1, r1 ! Within loop`
85			`Loop4_last2:`
86			`add #1, r1 ! Within loop`
87			`Loop4_last1:`
88			`add #1, r1 ! Within loop`
89			`Loop4_last:`
90			`add #1, r1 ! Within loop`
91			`Loop4_end:`
92			`add #2, r1 ! After loop`
93
94			`# r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)`
95			`assertreg 0xa5a5a5a5+23, r1`
96
97			`set_greg 0xa5a5a5a5, r0`
98			`set_greg 0xa5a5a5a5, r1`
99			`test_grs_a5a5`
100
101			`loop5:`
102			`set_grs_a5a5`
103
104			`ldrs Loop5_begin`
105			`ldre Loop5_last3+4`
106			`setrc #5`
107			`add #1, r1 ! Before loop`
108			`# Loop should execute five instructions five times.`
109			`Loop5_begin:`
110			`add #1, r1 ! Within loop`
111			`Loop5_last3:`
112			`add #1, r1 ! Within loop`
113			`Loop5_last2:`
114			`add #1, r1 ! Within loop`
115			`Loop5_last1:`
116			`add #1, r1 ! Within loop`
117			`Loop5_last:`
118			`add #1, r1 ! Within loop`
119			`Loop5_end:`
120			`add #2, r1 ! After loop`
121
122			`# r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)`
123			`assertreg 0xa5a5a5a5+28, r1`
124
125			`set_greg 0xa5a5a5a5, r0`
126			`set_greg 0xa5a5a5a5, r1`
127			`test_grs_a5a5`
128
129			`loopn:`
130			`set_grs_a5a5`
131
132			`ldrs Loopn_begin`
133			`ldre Loopn_last3+4`
134			`setrc #5`
135			`add #1, r1 ! Before loop`
136			`# Loop should execute n instructions five times.`
137			`Loopn_begin:`
138			`add #1, r1 ! Within loop`
139			`add #1, r1 ! Within loop`
140			`add #1, r1 ! Within loop`
141			`add #1, r1 ! Within loop`
142			`add #1, r1 ! Within loop`
143			`add #1, r1 ! Within loop`
144			`add #1, r1 ! Within loop`
145			`add #1, r1 ! Within loop`
146			`Loopn_last3:`
147			`add #1, r1 ! Within loop`
148			`Loopn_last2:`
149			`add #1, r1 ! Within loop`
150			`Loopn_last1:`
151			`add #1, r1 ! Within loop`
152			`Loopn_last:`
153			`add #1, r1 ! Within loop`
154			`Loopn_end:`
155			`add #3, r1 ! After loop`
156
157			`# r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)`
158			`assertreg 0xa5a5a5a5+64, r1`
159
160			`set_greg 0xa5a5a5a5, r0`
161			`set_greg 0xa5a5a5a5, r1`
162			`test_grs_a5a5`
163
164			`loop1e:`
165			`set_grs_a5a5`
166
167			`ldrs Loop1e_begin`
168			`ldre Loop1e_last`
169			`ldrc #5`
170			`add #1, r1 ! Before loop`
171			`# Loop should execute one instruction five times.`
172			`Loop1e_begin:`
173			`Loop1e_last:`
174			`add #1, r1 ! Within loop`
175			`Loop1e_end:`
176			`add #2, r1 ! After loop`
177
178			`# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)`
179			`assertreg 0xa5a5a5a5+8, r1`
180
181			`set_greg 0xa5a5a5a5, r0`
182			`set_greg 0xa5a5a5a5, r1`
183			`test_grs_a5a5`
184
185			`loop2e:`
186			`set_grs_a5a5`
187
188			`ldrs Loop2e_begin`
189			`ldre Loop2e_last`
190			`ldrc #5`
191			`add #1, r1 ! Before loop`
192			`# Loop should execute two instructions five times.`
193			`Loop2e_begin:`
194			`add #1, r1 ! Within loop`
195			`Loop2e_last:`
196			`add #1, r1 ! Within loop`
197			`Loop2e_end:`
198			`add #2, r1 ! After loop`
199
200			`# r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)`
201			`assertreg 0xa5a5a5a5+13, r1`
202
203			`set_greg 0xa5a5a5a5, r0`
204			`set_greg 0xa5a5a5a5, r1`
205			`test_grs_a5a5`
206
207			`loop3e:`
208			`set_grs_a5a5`
209
210			`ldrs Loop3e_begin`
211			`ldre Loop3e_last`
212			`ldrc #5`
213			`add #1, r1 ! Before loop`
214			`# Loop should execute three instructions five times.`
215			`Loop3e_begin:`
216			`add #1, r1 ! Within loop`
217			`add #1, r1 ! Within loop`
218			`Loop3e_last:`
219			`add #1, r1 ! Within loop`
220			`Loop3e_end:`
221			`add #2, r1 ! After loop`
222
223			`# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)`
224			`assertreg 0xa5a5a5a5+18, r1`
225
226			`set_greg 0xa5a5a5a5, r0`
227			`set_greg 0xa5a5a5a5, r1`
228			`test_grs_a5a5`
229
230			`loop4e:`
231			`set_grs_a5a5`
232
233			`ldrs Loop4e_begin`
234			`ldre Loop4e_last`
235			`ldrc #5`
236			`add #1, r1 ! Before loop`
237			`# Loop should execute four instructions five times.`
238			`Loop4e_begin:`
239			`add #1, r1 ! Within loop`
240			`add #1, r1 ! Within loop`
241			`add #1, r1 ! Within loop`
242			`Loop4e_last:`
243			`add #1, r1 ! Within loop`
244			`Loop4e_end:`
245			`add #2, r1 ! After loop`
246
247			`# r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)`
248			`assertreg 0xa5a5a5a5+23, r1`
249
250			`set_greg 0xa5a5a5a5, r0`
251			`set_greg 0xa5a5a5a5, r1`
252			`test_grs_a5a5`
253
254			`loop5e:`
255			`set_grs_a5a5`
256
257			`ldrs Loop5e_begin`
258			`ldre Loop5e_last`
259			`ldrc #5`
260			`add #1, r1 ! Before loop`
261			`# Loop should execute five instructions five times.`
262			`Loop5e_begin:`
263			`add #1, r1 ! Within loop`
264			`add #1, r1 ! Within loop`
265			`add #1, r1 ! Within loop`
266			`add #1, r1 ! Within loop`
267			`Loop5e_last:`
268			`add #1, r1 ! Within loop`
269			`Loop5e_end:`
270			`add #2, r1 ! After loop`
271
272			`# r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)`
273			`assertreg 0xa5a5a5a5+28, r1`
274
275			`set_greg 0xa5a5a5a5, r0`
276			`set_greg 0xa5a5a5a5, r1`
277			`test_grs_a5a5`
278
279			`loop_n_e:`
280			`set_grs_a5a5`
281
282			`ldrs Loop_n_e_begin`
283			`ldre Loop_n_e_last`
284			`ldrc #5`
285			`add #1, r1 ! Before loop`
286			`# Loop should execute n instructions five times.`
287			`Loop_n_e_begin:`
288			`add #1, r1 ! Within loop`
289			`add #1, r1 ! Within loop`
290			`add #1, r1 ! Within loop`
291			`add #1, r1 ! Within loop`
292			`add #1, r1 ! Within loop`
293			`add #1, r1 ! Within loop`
294			`add #1, r1 ! Within loop`
295			`add #1, r1 ! Within loop`
296			`Loop_n_e_last:`
297			`add #1, r1 ! Within loop`
298			`Loop_n_e_end:`
299			`add #2, r1 ! After loop`
300
301			`# r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)`
302			`assertreg 0xa5a5a5a5+48, r1`
303
304			`set_greg 0xa5a5a5a5, r0`
305			`set_greg 0xa5a5a5a5, r1`
306			`test_grs_a5a5`
307
308			`pass`
309
310			`exit 0`
311