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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [mov.s] - Blame information for rev 330

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Line No. Rev Author Line
1 330 jeremybenn 
# sh testcase for all mov.[bwl] instructions
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# mach: sh
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# as(sh):       -defsym sim_cpu=0
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        .include "testutils.inc"
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        .align 2
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_lsrc:  .long   0x55555555
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_wsrc:  .long   0x55550000
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_bsrc:  .long   0x55000000
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        .align 2
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_ldst:  .long   0
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_wdst:  .long   0
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_bdst:  .long   0
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        start
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movb_disp12_reg:        # Test 8-bit @(disp12,gr) -> gr
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        set_grs_a5a5
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        mov.l   bsrc, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.b   @(444,r1), r2
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        assertreg _bsrc-444, r1
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        assertreg 0x55, r2
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movb_reg_disp12:        # Test 8-bit gr -> @(disp12,gr)
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        set_grs_a5a5
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        mov.l   bdst, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.b   r2, @(444,r1)
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        assertreg _bdst-444, r1
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        assertmem _bdst, 0xa5000000
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movw_disp12_reg:        # Test 16-bit @(disp12,gr) -> gr
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        set_grs_a5a5
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        mov.l   wsrc, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.w   @(444,r1), r2
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        assertreg _wsrc-444, r1
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        assertreg 0x5555, r2
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movw_reg_disp12:        # Test 16-bit gr -> @(disp12,gr)
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        set_grs_a5a5
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        mov.l   wdst, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.w   r2, @(444,r1)
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        assertreg _wdst-444, r1
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        assertmem _wdst, 0xa5a50000
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movl_disp12_reg:        # Test 32-bit @(disp12,gr) -> gr
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        set_grs_a5a5
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        mov.l   lsrc, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.l   @(444,r1), r2
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        assertreg _lsrc-444, r1
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        assertreg 0x55555555, r2
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movl_reg_disp12:        # Test 32-bit gr -> @(disp12,gr)
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        set_grs_a5a5
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        mov.l   ldst, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        add     #-111, r1
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        mov.l   r2, @(444,r1)
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        assertreg _ldst-444, r1
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        assertmem _ldst, 0xa5a5a5a5
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        test_gr_a5a5 r0
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        test_gr_a5a5 r2
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        test_gr_a5a5 r3
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        test_gr_a5a5 r4
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        test_gr_a5a5 r5
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        test_gr_a5a5 r6
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        test_gr_a5a5 r7
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        test_gr_a5a5 r8
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        test_gr_a5a5 r9
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        test_gr_a5a5 r10
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        test_gr_a5a5 r11
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        test_gr_a5a5 r12
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        test_gr_a5a5 r13
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        test_gr_a5a5 r14
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        pass
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        exit 0
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lsrc:   .long _lsrc
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wsrc:   .long _wsrc
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bsrc:   .long _bsrc
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ldst:   .long _ldst
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wdst:   .long _wdst
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bdst:   .long _bdst
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