OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [pinc.s] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# sh testcase for pinc
2
# mach: shdsp
3
# as(shdsp):    -defsym sim_cpu=1 -dsp
4
 
5
        .include "testutils.inc"
6
 
7
        start
8
 
9
pincx:
10
        set_grs_a5a5
11
        lds     r0, a0
12
        pcopy   a0, a1
13
        lds     r0, x0
14
        lds     r0, x1
15
        lds     r0, y0
16
        lds     r0, y1
17
        pcopy   x0, m0
18
        pcopy   y1, m1
19
 
20
        pinc    x0, y0
21
        assert_sreg     0xa5a60000, y0
22
 
23
        test_grs_a5a5
24
        assert_sreg     0xa5a5a5a5, x0
25
        assert_sreg     0xa5a5a5a5, x1
26
        assert_sreg     0xa5a5a5a5, y1
27
        assert_sreg     0xa5a5a5a5, a0
28
        assert_sreg2    0xa5a5a5a5, a1
29
        assert_sreg2    0xa5a5a5a5, m0
30
        assert_sreg2    0xa5a5a5a5, m1
31
 
32
pincy:
33
        set_grs_a5a5
34
        lds     r0, a0
35
        pcopy   a0, a1
36
        lds     r0, x0
37
        lds     r0, x1
38
        lds     r0, y0
39
        lds     r0, y1
40
        pcopy   x0, m0
41
        pcopy   y1, m1
42
 
43
        pinc    y0, x0
44
        assert_sreg     0xa5a60000, x0
45
 
46
        test_grs_a5a5
47
        assert_sreg     0xa5a5a5a5, y0
48
        assert_sreg     0xa5a5a5a5, x1
49
        assert_sreg     0xa5a5a5a5, y1
50
        assert_sreg     0xa5a5a5a5, a0
51
        assert_sreg2    0xa5a5a5a5, a1
52
        assert_sreg2    0xa5a5a5a5, m0
53
        assert_sreg2    0xa5a5a5a5, m1
54
 
55
dct_pincx:
56
        set_grs_a5a5
57
        lds     r0, a0
58
        pcopy   a0, a1
59
        lds     r0, x0
60
        lds     r0, x1
61
        lds     r0, y0
62
        lds     r0, y1
63
        pcopy   x0, m0
64
        pcopy   y1, m1
65
 
66
        set_dcfalse
67
        dct     pinc    x0, y0
68
        assert_sreg     0xa5a5a5a5, y0
69
        set_dctrue
70
        dct     pinc    x0, y0
71
        assert_sreg     0xa5a60000, y0
72
 
73
        test_grs_a5a5
74
        assert_sreg     0xa5a5a5a5, x0
75
        assert_sreg     0xa5a5a5a5, x1
76
        assert_sreg     0xa5a5a5a5, y1
77
        assert_sreg     0xa5a5a5a5, a0
78
        assert_sreg2    0xa5a5a5a5, a1
79
        assert_sreg2    0xa5a5a5a5, m0
80
        assert_sreg2    0xa5a5a5a5, m1
81
 
82
dcf_pincy:
83
        set_grs_a5a5
84
        lds     r0, a0
85
        pcopy   a0, a1
86
        lds     r0, x0
87
        lds     r0, x1
88
        lds     r0, y0
89
        lds     r0, y1
90
        pcopy   x0, m0
91
        pcopy   y1, m1
92
 
93
        set_dctrue
94
        dcf     pinc    y0, x0
95
        assert_sreg     0xa5a5a5a5, x0
96
        set_dcfalse
97
        dcf     pinc    y0, x0
98
        assert_sreg     0xa5a60000, x0
99
 
100
        test_grs_a5a5
101
        assert_sreg     0xa5a5a5a5, x1
102
        assert_sreg     0xa5a5a5a5, y0
103
        assert_sreg     0xa5a5a5a5, y1
104
        assert_sreg     0xa5a5a5a5, a0
105
        assert_sreg2    0xa5a5a5a5, a1
106
        assert_sreg2    0xa5a5a5a5, m0
107
        assert_sreg2    0xa5a5a5a5, m1
108
 
109
        pass
110
        exit 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.