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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [shlr16.s] - Blame information for rev 841

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# sh testcase for shlr16
# mach: all
# as(sh):       -defsym sim_cpu=0
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
 
shrl16:
        set_grs_a5a5
        shlr16 r0
        assertreg0 0xa5a5
        shlr16 r0
        assertreg0 0
 
        set_greg 0xa5a5a5a5, r0
        test_grs_a5a5
        pass
        exit 0

Line No.	Rev	Author	Line
1	330	jeremybenn	`# sh testcase for shlr16`
2			`# mach: all`
3			`# as(sh): -defsym sim_cpu=0`
4			`# as(shdsp): -defsym sim_cpu=1 -dsp`
5
6			`.include "testutils.inc"`
7
8			`start`
9
10			`shrl16:`
11			`set_grs_a5a5`
12			`shlr16 r0`
13			`assertreg0 0xa5a5`
14			`shlr16 r0`
15			`assertreg0 0`
16
17			`set_greg 0xa5a5a5a5, r0`
18			`test_grs_a5a5`
19			`pass`
20			`exit 0`

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[/] [openrisc/] [trunk/] [gnu-stable/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [shlr16.s] - Blame information for rev 841