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[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [libgloss/] [bfin/] [include/] [defBF548.h] - Blame information for rev 853

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Line No. Rev Author Line
1 207 jeremybenn 
/*
2 
 * The authors hereby grant permission to use, copy, modify, distribute,
3 
 * and license this software and its documentation for any purpose, provided
4 
 * that existing copyright notices are retained in all copies and that this
5 
 * notice is included verbatim in any distributions. No written agreement,
6 
 * license, or royalty fee is required for any of the authorized uses.
7 
 * Modifications to this software may be copyrighted by their authors
8 
 * and need not follow the licensing terms described here, provided that
9 
 * the new terms are clearly indicated on the first page of each file where
10 
 * they apply.
11 
 */
12 
 
13 
/*
14 
** defBF548.h
15 
**
16 
** Copyright (C) 2008, 2009 Analog Devices, Inc.
17 
**
18 
************************************************************************************
19 
**
20 
** This include file contains a list of macro "defines" to enable the programmer
21 
** to use symbolic names for register-access and bit-manipulation.
22 
**
23 
**/
24 
#ifndef _DEF_BF548_H
25 
#define _DEF_BF548_H
26 
 
27 
/* Include all Core registers and bit definitions */
28 
#include <def_LPBlackfin.h>
29 
 
30 
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
31 
 
32 
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
33 
#include <defBF54x_base.h>
34 
 
35 
#ifdef _MISRA_RULES
36 
#pragma diag(push)
37 
#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
38 
#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
39 
#endif /* _MISRA_RULES */
40 
 
41 
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
42 
 
43 
/* Timer Registers */
44 
 
45 
#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
46 
#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
47 
#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
48 
#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
49 
#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
50 
#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
51 
#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
52 
#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
53 
#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
54 
#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
55 
#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
56 
#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
57 
 
58 
/* Timer Group of 3 Registers */
59 
 
60 
#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
61 
#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
62 
#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
63 
 
64 
/* SPORT0 Registers */
65 
 
66 
#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
67 
#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
68 
#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
69 
#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
70 
#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
71 
#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
72 
#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
73 
#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
74 
#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
75 
#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
76 
#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
77 
#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
78 
#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
79 
#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
80 
#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
81 
#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
82 
#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
83 
#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
84 
#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
85 
#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
86 
#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
87 
#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
88 
 
89 
/* EPPI0 Registers */
90 
 
91 
#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
92 
#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
93 
#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
94 
#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
95 
#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
96 
#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
97 
#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
98 
#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
99 
#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
100 
#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
101 
#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
102 
#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
103 
#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
104 
#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
105 
 
106 
/* UART2 Registers */
107 
 
108 
#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
109 
#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
110 
#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
111 
#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
112 
#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
113 
#define                        UART2_LSR  0xffc02114   /* Line Status Register */
114 
#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
115 
#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
116 
#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
117 
#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
118 
#define                        UART2_THR  0xffc02128   /* Transmit Hold Register */
119 
#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
120 
 
121 
/* Two Wire Interface Registers (TWI1) */
122 
 
123 
#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
124 
#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
125 
#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
126 
#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
127 
#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
128 
#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
129 
#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
130 
#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
131 
#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
132 
#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
133 
#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
134 
#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
135 
#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
136 
#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
137 
#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
138 
#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
139 
 
140 
/* SPI2  Registers */
141 
 
142 
#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
143 
#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
144 
#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
145 
#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
146 
#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
147 
#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
148 
#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
149 
 
150 
/* CAN Controller 1 Config 1 Registers */
151 
 
152 
#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
153 
#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
154 
#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
155 
#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
156 
#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
157 
#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
158 
#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
159 
#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
160 
#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
161 
#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
162 
#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
163 
#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
164 
#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
165 
 
166 
/* CAN Controller 1 Config 2 Registers */
167 
 
168 
#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
169 
#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
170 
#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
171 
#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
172 
#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
173 
#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
174 
#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
175 
#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
176 
#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
177 
#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
178 
#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
179 
#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
180 
#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
181 
 
182 
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
183 
 
184 
#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
185 
#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
186 
#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
187 
#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
188 
#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
189 
#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
190 
#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
191 
#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
192 
#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
193 
#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
194 
#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
195 
#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
196 
#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
197 
#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
198 
#define                        CAN1_UCRC  0xffc032c8   /* Universal Counter Reload/Capture Register */
199 
#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
200 
 
201 
/* CAN Controller 1 Mailbox Acceptance Registers */
202 
 
203 
#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
204 
#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
205 
#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
206 
#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
207 
#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
208 
#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
209 
#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
210 
#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
211 
#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
212 
#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
213 
#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
214 
#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
215 
#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
216 
#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
217 
#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
218 
#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
219 
#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
220 
#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
221 
#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
222 
#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
223 
#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
224 
#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
225 
#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
226 
#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
227 
#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
228 
#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
229 
#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
230 
#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
231 
#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
232 
#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
233 
#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
234 
#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
235 
 
236 
/* CAN Controller 1 Mailbox Acceptance Registers */
237 
 
238 
#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
239 
#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
240 
#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
241 
#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
242 
#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
243 
#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
244 
#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
245 
#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
246 
#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
247 
#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
248 
#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
249 
#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
250 
#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
251 
#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
252 
#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
253 
#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
254 
#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
255 
#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
256 
#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
257 
#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
258 
#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
259 
#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
260 
#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
261 
#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
262 
#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
263 
#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
264 
#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
265 
#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
266 
#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
267 
#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
268 
#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
269 
#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
270 
 
271 
/* CAN Controller 1 Mailbox Data Registers */
272 
 
273 
#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
274 
#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
275 
#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
276 
#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
277 
#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
278 
#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
279 
#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
280 
#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
281 
#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
282 
#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
283 
#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
284 
#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
285 
#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
286 
#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
287 
#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
288 
#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
289 
#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
290 
#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
291 
#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
292 
#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
293 
#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
294 
#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
295 
#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
296 
#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
297 
#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
298 
#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
299 
#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
300 
#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
301 
#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
302 
#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
303 
#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
304 
#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
305 
#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
306 
#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
307 
#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
308 
#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
309 
#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
310 
#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
311 
#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
312 
#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
313 
#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
314 
#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
315 
#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
316 
#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
317 
#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
318 
#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
319 
#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
320 
#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
321 
#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
322 
#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
323 
#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
324 
#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
325 
#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
326 
#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
327 
#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
328 
#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
329 
#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
330 
#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
331 
#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
332 
#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
333 
#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
334 
#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
335 
#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
336 
#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
337 
#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
338 
#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
339 
#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
340 
#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
341 
#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
342 
#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
343 
#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
344 
#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
345 
#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
346 
#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
347 
#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
348 
#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
349 
#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
350 
#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
351 
#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
352 
#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
353 
#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
354 
#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
355 
#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
356 
#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
357 
#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
358 
#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
359 
#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
360 
#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
361 
#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
362 
#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
363 
#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
364 
#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
365 
#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
366 
#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
367 
#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
368 
#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
369 
#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
370 
#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
371 
#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
372 
#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
373 
#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
374 
#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
375 
#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
376 
#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
377 
#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
378 
#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
379 
#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
380 
#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
381 
#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
382 
#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
383 
#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
384 
#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
385 
#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
386 
#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
387 
#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
388 
#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
389 
#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
390 
#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
391 
#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
392 
#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
393 
#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
394 
#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
395 
#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
396 
#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
397 
#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
398 
#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
399 
#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
400 
#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
401 
 
402 
/* CAN Controller 1 Mailbox Data Registers */
403 
 
404 
#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
405 
#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
406 
#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
407 
#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
408 
#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
409 
#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
410 
#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
411 
#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
412 
#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
413 
#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
414 
#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
415 
#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
416 
#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
417 
#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
418 
#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
419 
#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
420 
#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
421 
#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
422 
#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
423 
#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
424 
#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
425 
#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
426 
#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
427 
#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
428 
#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
429 
#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
430 
#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
431 
#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
432 
#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
433 
#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
434 
#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
435 
#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
436 
#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
437 
#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
438 
#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
439 
#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
440 
#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
441 
#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
442 
#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
443 
#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
444 
#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
445 
#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
446 
#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
447 
#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
448 
#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
449 
#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
450 
#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
451 
#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
452 
#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
453 
#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
454 
#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
455 
#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
456 
#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
457 
#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
458 
#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
459 
#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
460 
#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
461 
#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
462 
#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
463 
#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
464 
#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
465 
#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
466 
#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
467 
#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
468 
#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
469 
#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
470 
#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
471 
#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
472 
#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
473 
#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
474 
#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
475 
#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
476 
#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
477 
#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
478 
#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
479 
#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
480 
#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
481 
#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
482 
#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
483 
#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
484 
#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
485 
#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
486 
#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
487 
#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
488 
#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
489 
#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
490 
#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
491 
#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
492 
#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
493 
#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
494 
#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
495 
#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
496 
#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
497 
#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
498 
#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
499 
#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
500 
#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
501 
#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
502 
#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
503 
#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
504 
#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
505 
#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
506 
#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
507 
#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
508 
#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
509 
#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
510 
#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
511 
#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
512 
#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
513 
#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
514 
#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
515 
#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
516 
#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
517 
#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
518 
#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
519 
#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
520 
#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
521 
#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
522 
#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
523 
#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
524 
#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
525 
#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
526 
#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
527 
#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
528 
#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
529 
#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
530 
#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
531 
#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
532 
 
533 
/* ATAPI Registers */
534 
 
535 
#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
536 
#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
537 
#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
538 
#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
539 
#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
540 
#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
541 
#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
542 
#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
543 
#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
544 
#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
545 
#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
546 
#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
547 
#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
548 
#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
549 
#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
550 
#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
551 
#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
552 
#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
553 
#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
554 
#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
555 
#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
556 
#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
557 
#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
558 
#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
559 
#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
560 
 
561 
/* SDH Registers */
562 
 
563 
#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
564 
#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
565 
#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
566 
#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
567 
#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
568 
#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
569 
#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
570 
#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
571 
#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
572 
#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
573 
#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
574 
#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
575 
#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
576 
#define                       SDH_STATUS  0xffc03934   /* SDH Status */
577 
#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
578 
#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
579 
#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
580 
#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
581 
#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
582 
#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
583 
#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
584 
#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
585 
#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
586 
#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
587 
#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
588 
#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
589 
#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
590 
#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
591 
#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
592 
#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
593 
#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
594 
 
595 
/* HOST Port Registers */
596 
 
597 
#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
598 
#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
599 
#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
600 
 
601 
/* USB Control Registers */
602 
 
603 
#define                        USB_FADDR  0xffc03c00   /* Function address register */
604 
#define                        USB_POWER  0xffc03c04   /* Power management register */
605 
#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
606 
#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
607 
#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
608 
#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
609 
#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
610 
#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
611 
#define                        USB_FRAME  0xffc03c20   /* USB frame number */
612 
#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
613 
#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
614 
#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
615 
#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
616 
 
617 
/* USB Packet Control Registers */
618 
 
619 
#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
620 
#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
621 
#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
622 
#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
623 
#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
624 
#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
625 
#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
626 
#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
627 
#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
628 
#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
629 
#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
630 
#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
631 
#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
632 
 
633 
/* USB Endpoint FIFO Registers */
634 
 
635 
#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
636 
#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
637 
#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
638 
#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
639 
#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
640 
#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
641 
#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
642 
#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
643 
 
644 
/* USB OTG Control Registers */
645 
 
646 
#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
647 
#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
648 
#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
649 
 
650 
/* USB Phy Control Registers */
651 
 
652 
#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
653 
#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
654 
#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
655 
#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
656 
#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
657 
 
658 
/* (APHY_CNTRL is for ADI usage only) */
659 
 
660 
#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
661 
 
662 
/* (APHY_CALIB is for ADI usage only) */
663 
 
664 
#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
665 
#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
666 
 
667 
/* (PHY_TEST is for ADI usage only) */
668 
 
669 
#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
670 
#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
671 
#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
672 
 
673 
/* USB Endpoint 0 Control Registers */
674 
 
675 
#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
676 
#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
677 
#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
678 
#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
679 
#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
680 
#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
681 
#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
682 
#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
683 
#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
684 
 
685 
/* USB Endpoint 1 Control Registers */
686 
 
687 
#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
688 
#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
689 
#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
690 
#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
691 
#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
692 
#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
693 
#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
694 
#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
695 
#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
696 
#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
697 
 
698 
/* USB Endpoint 2 Control Registers */
699 
 
700 
#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
701 
#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
702 
#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
703 
#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
704 
#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
705 
#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
706 
#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
707 
#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
708 
#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
709 
#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
710 
 
711 
/* USB Endpoint 3 Control Registers */
712 
 
713 
#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
714 
#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
715 
#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
716 
#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
717 
#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
718 
#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
719 
#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
720 
#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
721 
#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
722 
#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
723 
 
724 
/* USB Endpoint 4 Control Registers */
725 
 
726 
#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
727 
#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
728 
#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
729 
#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
730 
#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
731 
#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
732 
#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
733 
#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
734 
#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
735 
#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
736 
 
737 
/* USB Endpoint 5 Control Registers */
738 
 
739 
#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
740 
#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
741 
#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
742 
#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
743 
#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
744 
#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
745 
#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
746 
#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
747 
#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
748 
#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
749 
 
750 
/* USB Endpoint 6 Control Registers */
751 
 
752 
#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
753 
#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
754 
#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
755 
#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
756 
#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
757 
#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
758 
#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
759 
#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
760 
#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
761 
#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
762 
 
763 
/* USB Endpoint 7 Control Registers */
764 
 
765 
#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
766 
#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
767 
#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
768 
#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
769 
#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
770 
#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
771 
#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
772 
#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
773 
#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
774 
#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
775 
#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
776 
#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
777 
 
778 
/* USB Channel 0 Config Registers */
779 
 
780 
#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
781 
#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
782 
#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
783 
#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
784 
#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
785 
 
786 
/* USB Channel 1 Config Registers */
787 
 
788 
#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
789 
#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
790 
#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
791 
#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
792 
#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
793 
 
794 
/* USB Channel 2 Config Registers */
795 
 
796 
#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
797 
#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
798 
#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
799 
#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
800 
#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
801 
 
802 
/* USB Channel 3 Config Registers */
803 
 
804 
#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
805 
#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
806 
#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
807 
#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
808 
#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
809 
 
810 
/* USB Channel 4 Config Registers */
811 
 
812 
#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
813 
#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
814 
#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
815 
#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
816 
#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
817 
 
818 
/* USB Channel 5 Config Registers */
819 
 
820 
#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
821 
#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
822 
#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
823 
#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
824 
#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
825 
 
826 
/* USB Channel 6 Config Registers */
827 
 
828 
#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
829 
#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
830 
#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
831 
#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
832 
#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
833 
 
834 
/* USB Channel 7 Config Registers */
835 
 
836 
#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
837 
#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
838 
#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
839 
#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
840 
#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
841 
 
842 
/* Keypad Registers */
843 
 
844 
#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
845 
#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
846 
#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
847 
#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
848 
#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
849 
#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
850 
 
851 
/* Pixel Compositor (PIXC) Registers */
852 
 
853 
#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
854 
#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
855 
#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
856 
#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
857 
#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
858 
#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
859 
#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
860 
#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
861 
#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
862 
#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
863 
#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
864 
#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
865 
#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
866 
#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
867 
#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
868 
#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
869 
#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
870 
#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
871 
#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
872 
 
873 
/* ********************************************************** */
874 
/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
875 
/*     and MULTI BIT READ MACROS                              */
876 
/* ********************************************************** */
877 
 
878 
/* Bit masks for PIXC_CTL */
879 
 
880 
#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
881 
#define                  nPIXC_EN  0x0
882 
#define                  OVR_A_EN  0x2        /* Overlay A Enable */
883 
#define                 nOVR_A_EN  0x0
884 
#define                  OVR_B_EN  0x4        /* Overlay B Enable */
885 
#define                 nOVR_B_EN  0x0
886 
#define                  IMG_FORM  0x8        /* Image Data Format */
887 
#define                 nIMG_FORM  0x0
888 
#define                  OVR_FORM  0x10       /* Overlay Data Format */
889 
#define                 nOVR_FORM  0x0
890 
#define                  OUT_FORM  0x20       /* Output Data Format */
891 
#define                 nOUT_FORM  0x0
892 
#define                   UDS_MOD  0x40       /* Resampling Mode */
893 
#define                  nUDS_MOD  0x0
894 
#define                     TC_EN  0x80       /* Transparent Color Enable */
895 
#define                    nTC_EN  0x0
896 
#define                  IMG_STAT  0x300      /* Image FIFO Status */
897 
#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
898 
#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
899 
 
900 
/* Bit masks for PIXC_AHSTART */
901 
 
902 
#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
903 
 
904 
/* Bit masks for PIXC_AHEND */
905 
 
906 
#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
907 
 
908 
/* Bit masks for PIXC_AVSTART */
909 
 
910 
#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
911 
 
912 
/* Bit masks for PIXC_AVEND */
913 
 
914 
#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
915 
 
916 
/* Bit masks for PIXC_ATRANSP */
917 
 
918 
#define                  A_TRANSP  0xf        /* Transparency Value */
919 
 
920 
/* Bit masks for PIXC_BHSTART */
921 
 
922 
#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
923 
 
924 
/* Bit masks for PIXC_BHEND */
925 
 
926 
#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
927 
 
928 
/* Bit masks for PIXC_BVSTART */
929 
 
930 
#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
931 
 
932 
/* Bit masks for PIXC_BVEND */
933 
 
934 
#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
935 
 
936 
/* Bit masks for PIXC_BTRANSP */
937 
 
938 
#define                  B_TRANSP  0xf        /* Transparency Value */
939 
 
940 
/* Bit masks for PIXC_INTRSTAT */
941 
 
942 
#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
943 
#define               nOVR_INT_EN  0x0
944 
#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
945 
#define               nFRM_INT_EN  0x0
946 
#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
947 
#define             nOVR_INT_STAT  0x0
948 
#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
949 
#define             nFRM_INT_STAT  0x0
950 
 
951 
/* Bit masks for PIXC_RYCON */
952 
 
953 
#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
954 
#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
955 
#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
956 
#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
957 
#define                 nRY_MULT4  0x0
958 
 
959 
/* Bit masks for PIXC_GUCON */
960 
 
961 
#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
962 
#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
963 
#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
964 
#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
965 
#define                 nGU_MULT4  0x0
966 
 
967 
/* Bit masks for PIXC_BVCON */
968 
 
969 
#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
970 
#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
971 
#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
972 
#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
973 
#define                 nBV_MULT4  0x0
974 
 
975 
/* Bit masks for PIXC_CCBIAS */
976 
 
977 
#define                       A14  0x3ff      /* A14 in the Bias Vector */
978 
#define                       A24  0xffc00    /* A24 in the Bias Vector */
979 
#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
980 
 
981 
/* Bit masks for PIXC_TC */
982 
 
983 
#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
984 
#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
985 
#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
986 
 
987 
/* Bit masks for HOST_CONTROL */
988 
 
989 
#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
990 
#define                nHOSTDP_EN  0x0
991 
#define                HOSTDP_END  0x2        /* Host Endianess */
992 
#define               nHOSTDP_END  0x0
993 
#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
994 
#define         nHOSTDP_DATA_SIZE  0x0
995 
#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
996 
#define               nHOSTDP_RST  0x0
997 
#define                  HRDY_OVR  0x20       /* HRDY Override */
998 
#define                 nHRDY_OVR  0x0
999 
#define                  INT_MODE  0x40       /* Interrupt Mode */
1000 
#define                 nINT_MODE  0x0
1001 
#define                     BT_EN  0x80       /* Bus Timeout Enable */
1002 
#define                    nBT_EN  0x0
1003 
#define                       EHW  0x100      /* Enable Host Write */
1004 
#define                      nEHW  0x0
1005 
#define                       EHR  0x200      /* Enable Host Read */
1006 
#define                      nEHR  0x0
1007 
#define                       BDR  0x400      /* Burst DMA Requests */
1008 
#define                      nBDR  0x0
1009 
 
1010 
/* Bit masks for HOST_STATUS */
1011 
 
1012 
#define                   DMA_RDY  0x1        /* DMA Ready */
1013 
#define                  nDMA_RDY  0x0
1014 
#define                  FIFOFULL  0x2        /* FIFO Full */
1015 
#define                 nFIFOFULL  0x0
1016 
#define                 FIFOEMPTY  0x4        /* FIFO Empty */
1017 
#define                nFIFOEMPTY  0x0
1018 
#define                 DMA_CMPLT  0x8        /* DMA Complete */
1019 
#define                nDMA_CMPLT  0x0
1020 
#define                      HSHK  0x10       /* Host Handshake */
1021 
#define                     nHSHK  0x0
1022 
#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
1023 
#define              nHOSTDP_TOUT  0x0
1024 
#define                      HIRQ  0x40       /* Host Interrupt Request */
1025 
#define                     nHIRQ  0x0
1026 
#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
1027 
#define               nALLOW_CNFG  0x0
1028 
#define                   DMA_DIR  0x100      /* DMA Direction */
1029 
#define                  nDMA_DIR  0x0
1030 
#define                       BTE  0x200      /* Bus Timeout Enabled */
1031 
#define                      nBTE  0x0
1032 
 
1033 
/* Bit masks for HOST_TIMEOUT */
1034 
 
1035 
#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
1036 
 
1037 
/* Bit masks for KPAD_CTL */
1038 
 
1039 
#define                   KPAD_EN  0x1        /* Keypad Enable */
1040 
#define                  nKPAD_EN  0x0
1041 
#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
1042 
#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
1043 
#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
1044 
#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
1045 
 
1046 
#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
1047 
#define                KPAD_COLEN  0xe000     /* Column Enable Width */
1048 
 
1049 
#ifdef _MISRA_RULES
1050 
#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
1051 
#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
1052 
#else
1053 
#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
1054 
#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
1055 
#endif /* _MISRA_RULES */
1056 
 
1057 
 
1058 
/* Bit masks for KPAD_PRESCALE */
1059 
 
1060 
#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
1061 
 
1062 
#ifdef _MISRA_RULES
1063 
#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
1064 
#else
1065 
#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
1066 
#endif /* _MISRA_RULES */
1067 
 
1068 
 
1069 
/* Bit masks for KPAD_MSEL */
1070 
 
1071 
#define                DBON_SCALE  0xff       /* Debounce Scale Value */
1072 
#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
1073 
 
1074 
#ifdef _MISRA_RULES
1075 
#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
1076 
#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
1077 
#else
1078 
#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
1079 
#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
1080 
#endif /* _MISRA_RULES */
1081 
 
1082 
 
1083 
/* Bit masks for KPAD_ROWCOL */
1084 
 
1085 
#define                  KPAD_ROW  0xff       /* Rows Pressed */
1086 
#define                  KPAD_COL  0xff00     /* Columns Pressed */
1087 
 
1088 
/* Bit masks for KPAD_STAT */
1089 
 
1090 
#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
1091 
#define                 nKPAD_IRQ  0x0
1092 
#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
1093 
#define              KPAD_PRESSED  0x8        /* Key press current status */
1094 
#define             nKPAD_PRESSED  0x0
1095 
 
1096 
/* Bit masks for KPAD_SOFTEVAL */
1097 
 
1098 
#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
1099 
#define          nKPAD_SOFTEVAL_E  0x0
1100 
#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
1101 
#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
1102 
#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
1103 
#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
1104 
 
1105 
/* Bit masks for SDH_COMMAND */
1106 
 
1107 
#define                   CMD_IDX  0x3f       /* Command Index */
1108 
#define                   CMD_RSP  0x40       /* Response */
1109 
#define                  nCMD_RSP  0x0
1110 
#define                 CMD_L_RSP  0x80       /* Long Response */
1111 
#define                nCMD_L_RSP  0x0
1112 
#define                 CMD_INT_E  0x100      /* Command Interrupt */
1113 
#define                nCMD_INT_E  0x0
1114 
#define                CMD_PEND_E  0x200      /* Command Pending */
1115 
#define               nCMD_PEND_E  0x0
1116 
#define                     CMD_E  0x400      /* Command Enable */
1117 
#define                    nCMD_E  0x0
1118 
 
1119 
/* Bit masks for SDH_PWR_CTL */
1120 
 
1121 
#define                    PWR_ON  0x3        /* Power On */
1122 
#if 0
1123 
#define                       TBD  0x3c       /* TBD */
1124 
#endif
1125 
#define                 SD_CMD_OD  0x40       /* Open Drain Output */
1126 
#define                nSD_CMD_OD  0x0
1127 
#define                   ROD_CTL  0x80       /* Rod Control */
1128 
#define                  nROD_CTL  0x0
1129 
 
1130 
/* Bit masks for SDH_CLK_CTL */
1131 
 
1132 
#define                    CLKDIV  0xff       /* MC_CLK Divisor */
1133 
#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
1134 
#define                    nCLK_E  0x0
1135 
#define                  PWR_SV_E  0x200      /* Power Save Enable */
1136 
#define                 nPWR_SV_E  0x0
1137 
#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
1138 
#define            nCLKDIV_BYPASS  0x0
1139 
#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
1140 
#define                 nWIDE_BUS  0x0
1141 
 
1142 
/* Bit masks for SDH_RESP_CMD */
1143 
 
1144 
#define                  RESP_CMD  0x3f       /* Response Command */
1145 
 
1146 
/* Bit masks for SDH_DATA_CTL */
1147 
 
1148 
#define                     DTX_E  0x1        /* Data Transfer Enable */
1149 
#define                    nDTX_E  0x0
1150 
#define                   DTX_DIR  0x2        /* Data Transfer Direction */
1151 
#define                  nDTX_DIR  0x0
1152 
#define                  DTX_MODE  0x4        /* Data Transfer Mode */
1153 
#define                 nDTX_MODE  0x0
1154 
#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
1155 
#define                nDTX_DMA_E  0x0
1156 
#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
1157 
 
1158 
/* Bit masks for SDH_STATUS */
1159 
 
1160 
#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
1161 
#define             nCMD_CRC_FAIL  0x0
1162 
#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
1163 
#define             nDAT_CRC_FAIL  0x0
1164 
#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
1165 
#define              nCMD_TIMEOUT  0x0
1166 
#define               DAT_TIMEOUT  0x8        /* Data Time Out */
1167 
#define              nDAT_TIMEOUT  0x0
1168 
#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
1169 
#define              nTX_UNDERRUN  0x0
1170 
#define                RX_OVERRUN  0x20       /* Receive Overrun */
1171 
#define               nRX_OVERRUN  0x0
1172 
#define              CMD_RESP_END  0x40       /* CMD Response End */
1173 
#define             nCMD_RESP_END  0x0
1174 
#define                  CMD_SENT  0x80       /* CMD Sent */
1175 
#define                 nCMD_SENT  0x0
1176 
#define                   DAT_END  0x100      /* Data End */
1177 
#define                  nDAT_END  0x0
1178 
#define             START_BIT_ERR  0x200      /* Start Bit Error */
1179 
#define            nSTART_BIT_ERR  0x0
1180 
#define               DAT_BLK_END  0x400      /* Data Block End */
1181 
#define              nDAT_BLK_END  0x0
1182 
#define                   CMD_ACT  0x800      /* CMD Active */
1183 
#define                  nCMD_ACT  0x0
1184 
#define                    TX_ACT  0x1000     /* Transmit Active */
1185 
#define                   nTX_ACT  0x0
1186 
#define                    RX_ACT  0x2000     /* Receive Active */
1187 
#define                   nRX_ACT  0x0
1188 
#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
1189 
#define             nTX_FIFO_STAT  0x0
1190 
#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
1191 
#define             nRX_FIFO_STAT  0x0
1192 
#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
1193 
#define             nTX_FIFO_FULL  0x0
1194 
#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
1195 
#define             nRX_FIFO_FULL  0x0
1196 
#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
1197 
#define             nTX_FIFO_ZERO  0x0
1198 
#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
1199 
#define              nRX_DAT_ZERO  0x0
1200 
#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
1201 
#define               nTX_DAT_RDY  0x0
1202 
#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
1203 
#define              nRX_FIFO_RDY  0x0
1204 
 
1205 
/* Bit masks for SDH_STATUS_CLR */
1206 
 
1207 
#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
1208 
#define        nCMD_CRC_FAIL_STAT  0x0
1209 
#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
1210 
#define        nDAT_CRC_FAIL_STAT  0x0
1211 
#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
1212 
#define         nCMD_TIMEOUT_STAT  0x0
1213 
#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
1214 
#define         nDAT_TIMEOUT_STAT  0x0
1215 
#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
1216 
#define         nTX_UNDERRUN_STAT  0x0
1217 
#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
1218 
#define          nRX_OVERRUN_STAT  0x0
1219 
#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
1220 
#define        nCMD_RESP_END_STAT  0x0
1221 
#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
1222 
#define            nCMD_SENT_STAT  0x0
1223 
#define              DAT_END_STAT  0x100      /* Data End Status */
1224 
#define             nDAT_END_STAT  0x0
1225 
#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
1226 
#define       nSTART_BIT_ERR_STAT  0x0
1227 
#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
1228 
#define         nDAT_BLK_END_STAT  0x0
1229 
 
1230 
/* Bit masks for SDH_MASK0 */
1231 
 
1232 
#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
1233 
#define        nCMD_CRC_FAIL_MASK  0x0
1234 
#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
1235 
#define        nDAT_CRC_FAIL_MASK  0x0
1236 
#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
1237 
#define         nCMD_TIMEOUT_MASK  0x0
1238 
#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
1239 
#define         nDAT_TIMEOUT_MASK  0x0
1240 
#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
1241 
#define         nTX_UNDERRUN_MASK  0x0
1242 
#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
1243 
#define          nRX_OVERRUN_MASK  0x0
1244 
#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
1245 
#define        nCMD_RESP_END_MASK  0x0
1246 
#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
1247 
#define            nCMD_SENT_MASK  0x0
1248 
#define              DAT_END_MASK  0x100      /* Data End Mask */
1249 
#define             nDAT_END_MASK  0x0
1250 
#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
1251 
#define       nSTART_BIT_ERR_MASK  0x0
1252 
#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
1253 
#define         nDAT_BLK_END_MASK  0x0
1254 
#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
1255 
#define             nCMD_ACT_MASK  0x0
1256 
#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
1257 
#define              nTX_ACT_MASK  0x0
1258 
#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
1259 
#define              nRX_ACT_MASK  0x0
1260 
#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
1261 
#define        nTX_FIFO_STAT_MASK  0x0
1262 
#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
1263 
#define        nRX_FIFO_STAT_MASK  0x0
1264 
#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
1265 
#define        nTX_FIFO_FULL_MASK  0x0
1266 
#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
1267 
#define        nRX_FIFO_FULL_MASK  0x0
1268 
#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
1269 
#define        nTX_FIFO_ZERO_MASK  0x0
1270 
#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
1271 
#define         nRX_DAT_ZERO_MASK  0x0
1272 
#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
1273 
#define          nTX_DAT_RDY_MASK  0x0
1274 
#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
1275 
#define         nRX_FIFO_RDY_MASK  0x0
1276 
 
1277 
/* Bit masks for SDH_FIFO_CNT */
1278 
 
1279 
#define                FIFO_COUNT  0x7fff     /* FIFO Count */
1280 
 
1281 
/* Bit masks for SDH_E_STATUS */
1282 
 
1283 
#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
1284 
#define             nSDIO_INT_DET  0x0
1285 
#define               SD_CARD_DET  0x10       /* SD Card Detect */
1286 
#define              nSD_CARD_DET  0x0
1287 
 
1288 
/* Bit masks for SDH_E_MASK */
1289 
 
1290 
#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
1291 
#define                 nSDIO_MSK  0x0
1292 
#define                   SCD_MSK  0x40       /* Mask Card Detect */
1293 
#define                  nSCD_MSK  0x0
1294 
 
1295 
/* Bit masks for SDH_CFG */
1296 
 
1297 
#define                   CLKS_EN  0x1        /* Clocks Enable */
1298 
#define                  nCLKS_EN  0x0
1299 
#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
1300 
#define                     nSD4E  0x0
1301 
#define                       MWE  0x8        /* Moving Window Enable */
1302 
#define                      nMWE  0x0
1303 
#define                    SD_RST  0x10       /* SDMMC Reset */
1304 
#define                   nSD_RST  0x0
1305 
#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
1306 
#define                nPUP_SDDAT  0x0
1307 
#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
1308 
#define               nPUP_SDDAT3  0x0
1309 
#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
1310 
#define                nPD_SDDAT3  0x0
1311 
 
1312 
/* Bit masks for SDH_RD_WAIT_EN */
1313 
 
1314 
#define                       RWR  0x1        /* Read Wait Request */
1315 
#define                      nRWR  0x0
1316 
 
1317 
/* Bit masks for ATAPI_CONTROL */
1318 
 
1319 
#define                 PIO_START  0x1        /* Start PIO/Reg Op */
1320 
#define                nPIO_START  0x0
1321 
#define               MULTI_START  0x2        /* Start Multi-DMA Op */
1322 
#define              nMULTI_START  0x0
1323 
#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
1324 
#define              nULTRA_START  0x0
1325 
#define                  XFER_DIR  0x8        /* Transfer Direction */
1326 
#define                 nXFER_DIR  0x0
1327 
#define                  IORDY_EN  0x10       /* IORDY Enable */
1328 
#define                 nIORDY_EN  0x0
1329 
#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
1330 
#define               nFIFO_FLUSH  0x0
1331 
#define                  SOFT_RST  0x40       /* Soft Reset */
1332 
#define                 nSOFT_RST  0x0
1333 
#define                   DEV_RST  0x80       /* Device Reset */
1334 
#define                  nDEV_RST  0x0
1335 
#define                TFRCNT_RST  0x100      /* Trans Count Reset */
1336 
#define               nTFRCNT_RST  0x0
1337 
#define               END_ON_TERM  0x200      /* End/Terminate Select */
1338 
#define              nEND_ON_TERM  0x0
1339 
#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
1340 
#define              nPIO_USE_DMA  0x0
1341 
#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
1342 
 
1343 
/* Bit masks for ATAPI_STATUS */
1344 
 
1345 
#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
1346 
#define              nPIO_XFER_ON  0x0
1347 
#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
1348 
#define            nMULTI_XFER_ON  0x0
1349 
#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
1350 
#define            nULTRA_XFER_ON  0x0
1351 
#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
1352 
 
1353 
/* Bit masks for ATAPI_DEV_ADDR */
1354 
 
1355 
#define                  DEV_ADDR  0x1f       /* Device Address */
1356 
 
1357 
/* Bit masks for ATAPI_INT_MASK */
1358 
 
1359 
#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
1360 
#define       nATAPI_DEV_INT_MASK  0x0
1361 
#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
1362 
#define            nPIO_DONE_MASK  0x0
1363 
#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
1364 
#define          nMULTI_DONE_MASK  0x0
1365 
#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
1366 
#define         nUDMAIN_DONE_MASK  0x0
1367 
#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
1368 
#define        nUDMAOUT_DONE_MASK  0x0
1369 
#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
1370 
#define      nHOST_TERM_XFER_MASK  0x0
1371 
#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
1372 
#define          nMULTI_TERM_MASK  0x0
1373 
#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
1374 
#define         nUDMAIN_TERM_MASK  0x0
1375 
#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
1376 
#define        nUDMAOUT_TERM_MASK  0x0
1377 
 
1378 
/* Bit masks for ATAPI_INT_STATUS */
1379 
 
1380 
#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
1381 
#define            nATAPI_DEV_INT  0x0
1382 
#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
1383 
#define             nPIO_DONE_INT  0x0
1384 
#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
1385 
#define           nMULTI_DONE_INT  0x0
1386 
#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
1387 
#define          nUDMAIN_DONE_INT  0x0
1388 
#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
1389 
#define         nUDMAOUT_DONE_INT  0x0
1390 
#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
1391 
#define       nHOST_TERM_XFER_INT  0x0
1392 
#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
1393 
#define           nMULTI_TERM_INT  0x0
1394 
#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
1395 
#define          nUDMAIN_TERM_INT  0x0
1396 
#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
1397 
#define         nUDMAOUT_TERM_INT  0x0
1398 
 
1399 
/* Bit masks for ATAPI_LINE_STATUS */
1400 
 
1401 
#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
1402 
#define               nATAPI_INTR  0x0
1403 
#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
1404 
#define               nATAPI_DASP  0x0
1405 
#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
1406 
#define               nATAPI_CS0N  0x0
1407 
#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
1408 
#define               nATAPI_CS1N  0x0
1409 
#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
1410 
#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
1411 
#define             nATAPI_DMAREQ  0x0
1412 
#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
1413 
#define            nATAPI_DMAACKN  0x0
1414 
#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
1415 
#define              nATAPI_DIOWN  0x0
1416 
#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
1417 
#define              nATAPI_DIORN  0x0
1418 
#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
1419 
#define              nATAPI_IORDY  0x0
1420 
 
1421 
/* Bit masks for ATAPI_SM_STATE */
1422 
 
1423 
#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
1424 
#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
1425 
#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
1426 
#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
1427 
 
1428 
/* Bit masks for ATAPI_TERMINATE */
1429 
 
1430 
#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
1431 
#define          nATAPI_HOST_TERM  0x0
1432 
 
1433 
/* Bit masks for ATAPI_REG_TIM_0 */
1434 
 
1435 
#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
1436 
#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
1437 
 
1438 
/* Bit masks for ATAPI_PIO_TIM_0 */
1439 
 
1440 
#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
1441 
#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
1442 
#define                    T4_REG  0xf000     /* DIOW data hold */
1443 
 
1444 
/* Bit masks for ATAPI_PIO_TIM_1 */
1445 
 
1446 
#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
1447 
 
1448 
/* Bit masks for ATAPI_MULTI_TIM_0 */
1449 
 
1450 
#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
1451 
#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
1452 
 
1453 
/* Bit masks for ATAPI_MULTI_TIM_1 */
1454 
 
1455 
#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
1456 
#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
1457 
 
1458 
/* Bit masks for ATAPI_MULTI_TIM_2 */
1459 
 
1460 
#define                        TH  0xff       /* Selects DIOW data hold */
1461 
#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
1462 
 
1463 
/* Bit masks for ATAPI_ULTRA_TIM_0 */
1464 
 
1465 
#define                      TACK  0xff       /* Selects setup and hold times for TACK */
1466 
#define                      TENV  0xff00     /* Selects envelope time */
1467 
 
1468 
/* Bit masks for ATAPI_ULTRA_TIM_1 */
1469 
 
1470 
#define                      TDVS  0xff       /* Selects data valid setup time */
1471 
#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
1472 
 
1473 
/* Bit masks for ATAPI_ULTRA_TIM_2 */
1474 
 
1475 
#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1476 
#define                      TMLI  0xff00     /* Selects interlock time */
1477 
 
1478 
/* Bit masks for ATAPI_ULTRA_TIM_3 */
1479 
 
1480 
#define                      TZAH  0xff       /* Selects minimum delay required for output */
1481 
#define               READY_PAUSE  0xff00     /* Selects ready to pause */
1482 
 
1483 
/* Bit masks for TIMER_ENABLE1 */
1484 
 
1485 
#define                    TIMEN8  0x1        /* Timer 8 Enable */
1486 
#define                   nTIMEN8  0x0
1487 
#define                    TIMEN9  0x2        /* Timer 9 Enable */
1488 
#define                   nTIMEN9  0x0
1489 
#define                   TIMEN10  0x4        /* Timer 10 Enable */
1490 
#define                  nTIMEN10  0x0
1491 
 
1492 
/* Bit masks for TIMER_DISABLE1 */
1493 
 
1494 
#define                   TIMDIS8  0x1        /* Timer 8 Disable */
1495 
#define                  nTIMDIS8  0x0
1496 
#define                   TIMDIS9  0x2        /* Timer 9 Disable */
1497 
#define                  nTIMDIS9  0x0
1498 
#define                  TIMDIS10  0x4        /* Timer 10 Disable */
1499 
#define                 nTIMDIS10  0x0
1500 
 
1501 
/* Bit masks for TIMER_STATUS1 */
1502 
 
1503 
#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
1504 
#define                   nTIMIL8  0x0
1505 
#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
1506 
#define                   nTIMIL9  0x0
1507 
#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
1508 
#define                  nTIMIL10  0x0
1509 
#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
1510 
#define                nTOVF_ERR8  0x0
1511 
#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
1512 
#define                nTOVF_ERR9  0x0
1513 
#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
1514 
#define               nTOVF_ERR10  0x0
1515 
#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
1516 
#define                    nTRUN8  0x0
1517 
#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
1518 
#define                    nTRUN9  0x0
1519 
#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
1520 
#define                   nTRUN10  0x0
1521 
 
1522 
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1523 
 
1524 
/* Bit masks for USB_FADDR */
1525 
 
1526 
#define          FUNCTION_ADDRESS  0x7f       /* Function address */
1527 
 
1528 
/* Bit masks for USB_POWER */
1529 
 
1530 
#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
1531 
#define          nENABLE_SUSPENDM  0x0
1532 
#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
1533 
#define             nSUSPEND_MODE  0x0
1534 
#define               RESUME_MODE  0x4        /* DMA Mode */
1535 
#define              nRESUME_MODE  0x0
1536 
#define                     RESET  0x8        /* Reset indicator */
1537 
#define                    nRESET  0x0
1538 
#define                   HS_MODE  0x10       /* High Speed mode indicator */
1539 
#define                  nHS_MODE  0x0
1540 
#define                 HS_ENABLE  0x20       /* high Speed Enable */
1541 
#define                nHS_ENABLE  0x0
1542 
#define                 SOFT_CONN  0x40       /* Soft connect */
1543 
#define                nSOFT_CONN  0x0
1544 
#define                ISO_UPDATE  0x80       /* Isochronous update */
1545 
#define               nISO_UPDATE  0x0
1546 
 
1547 
/* Bit masks for USB_INTRTX */
1548 
 
1549 
#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
1550 
#define                   nEP0_TX  0x0
1551 
#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
1552 
#define                   nEP1_TX  0x0
1553 
#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
1554 
#define                   nEP2_TX  0x0
1555 
#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
1556 
#define                   nEP3_TX  0x0
1557 
#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
1558 
#define                   nEP4_TX  0x0
1559 
#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
1560 
#define                   nEP5_TX  0x0
1561 
#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
1562 
#define                   nEP6_TX  0x0
1563 
#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
1564 
#define                   nEP7_TX  0x0
1565 
 
1566 
/* Bit masks for USB_INTRRX */
1567 
 
1568 
#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
1569 
#define                   nEP1_RX  0x0
1570 
#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
1571 
#define                   nEP2_RX  0x0
1572 
#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
1573 
#define                   nEP3_RX  0x0
1574 
#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
1575 
#define                   nEP4_RX  0x0
1576 
#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
1577 
#define                   nEP5_RX  0x0
1578 
#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
1579 
#define                   nEP6_RX  0x0
1580 
#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
1581 
#define                   nEP7_RX  0x0
1582 
 
1583 
/* Bit masks for USB_INTRTXE */
1584 
 
1585 
#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
1586 
#define                 nEP0_TX_E  0x0
1587 
#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
1588 
#define                 nEP1_TX_E  0x0
1589 
#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
1590 
#define                 nEP2_TX_E  0x0
1591 
#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
1592 
#define                 nEP3_TX_E  0x0
1593 
#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
1594 
#define                 nEP4_TX_E  0x0
1595 
#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
1596 
#define                 nEP5_TX_E  0x0
1597 
#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
1598 
#define                 nEP6_TX_E  0x0
1599 
#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
1600 
#define                 nEP7_TX_E  0x0
1601 
 
1602 
/* Bit masks for USB_INTRRXE */
1603 
 
1604 
#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
1605 
#define                 nEP1_RX_E  0x0
1606 
#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
1607 
#define                 nEP2_RX_E  0x0
1608 
#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
1609 
#define                 nEP3_RX_E  0x0
1610 
#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
1611 
#define                 nEP4_RX_E  0x0
1612 
#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
1613 
#define                 nEP5_RX_E  0x0
1614 
#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
1615 
#define                 nEP6_RX_E  0x0
1616 
#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
1617 
#define                 nEP7_RX_E  0x0
1618 
 
1619 
/* Bit masks for USB_INTRUSB */
1620 
 
1621 
#define                 SUSPEND_B  0x1        /* Suspend indicator */
1622 
#define                nSUSPEND_B  0x0
1623 
#define                  RESUME_B  0x2        /* Resume indicator */
1624 
#define                 nRESUME_B  0x0
1625 
#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
1626 
#define         nRESET_OR_BABLE_B  0x0
1627 
#define                     SOF_B  0x8        /* Start of frame */
1628 
#define                    nSOF_B  0x0
1629 
#define                    CONN_B  0x10       /* Connection indicator */
1630 
#define                   nCONN_B  0x0
1631 
#define                  DISCON_B  0x20       /* Disconnect indicator */
1632 
#define                 nDISCON_B  0x0
1633 
#define             SESSION_REQ_B  0x40       /* Session Request */
1634 
#define            nSESSION_REQ_B  0x0
1635 
#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
1636 
#define             nVBUS_ERROR_B  0x0
1637 
 
1638 
/* Bit masks for USB_INTRUSBE */
1639 
 
1640 
#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
1641 
#define               nSUSPEND_BE  0x0
1642 
#define                 RESUME_BE  0x2        /* Resume indicator int enable */
1643 
#define                nRESUME_BE  0x0
1644 
#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
1645 
#define        nRESET_OR_BABLE_BE  0x0
1646 
#define                    SOF_BE  0x8        /* Start of frame int enable */
1647 
#define                   nSOF_BE  0x0
1648 
#define                   CONN_BE  0x10       /* Connection indicator int enable */
1649 
#define                  nCONN_BE  0x0
1650 
#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
1651 
#define                nDISCON_BE  0x0
1652 
#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
1653 
#define           nSESSION_REQ_BE  0x0
1654 
#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
1655 
#define            nVBUS_ERROR_BE  0x0
1656 
 
1657 
/* Bit masks for USB_FRAME */
1658 
 
1659 
#define              FRAME_NUMBER  0x7ff      /* Frame number */
1660 
 
1661 
/* Bit masks for USB_INDEX */
1662 
 
1663 
#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
1664 
 
1665 
/* Bit masks for USB_GLOBAL_CTL */
1666 
 
1667 
#define                GLOBAL_ENA  0x1        /* enables USB module */
1668 
#define               nGLOBAL_ENA  0x0
1669 
#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
1670 
#define               nEP1_TX_ENA  0x0
1671 
#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
1672 
#define               nEP2_TX_ENA  0x0
1673 
#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
1674 
#define               nEP3_TX_ENA  0x0
1675 
#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
1676 
#define               nEP4_TX_ENA  0x0
1677 
#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
1678 
#define               nEP5_TX_ENA  0x0
1679 
#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
1680 
#define               nEP6_TX_ENA  0x0
1681 
#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
1682 
#define               nEP7_TX_ENA  0x0
1683 
#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
1684 
#define               nEP1_RX_ENA  0x0
1685 
#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
1686 
#define               nEP2_RX_ENA  0x0
1687 
#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
1688 
#define               nEP3_RX_ENA  0x0
1689 
#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
1690 
#define               nEP4_RX_ENA  0x0
1691 
#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
1692 
#define               nEP5_RX_ENA  0x0
1693 
#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
1694 
#define               nEP6_RX_ENA  0x0
1695 
#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
1696 
#define               nEP7_RX_ENA  0x0
1697 
 
1698 
/* Bit masks for USB_OTG_DEV_CTL */
1699 
 
1700 
#define                   SESSION  0x1        /* session indicator */
1701 
#define                  nSESSION  0x0
1702 
#define                  HOST_REQ  0x2        /* Host negotiation request */
1703 
#define                 nHOST_REQ  0x0
1704 
#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
1705 
#define                nHOST_MODE  0x0
1706 
#define                     VBUS0  0x8        /* Vbus level indicator[0] */
1707 
#define                    nVBUS0  0x0
1708 
#define                     VBUS1  0x10       /* Vbus level indicator[1] */
1709 
#define                    nVBUS1  0x0
1710 
#define                     LSDEV  0x20       /* Low-speed indicator */
1711 
#define                    nLSDEV  0x0
1712 
#define                     FSDEV  0x40       /* Full or High-speed indicator */
1713 
#define                    nFSDEV  0x0
1714 
#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
1715 
#define                 nB_DEVICE  0x0
1716 
 
1717 
/* Bit masks for USB_OTG_VBUS_IRQ */
1718 
 
1719 
#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
1720 
#define            nDRIVE_VBUS_ON  0x0
1721 
#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
1722 
#define           nDRIVE_VBUS_OFF  0x0
1723 
#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
1724 
#define          nCHRG_VBUS_START  0x0
1725 
#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
1726 
#define            nCHRG_VBUS_END  0x0
1727 
#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
1728 
#define       nDISCHRG_VBUS_START  0x0
1729 
#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
1730 
#define         nDISCHRG_VBUS_END  0x0
1731 
 
1732 
/* Bit masks for USB_OTG_VBUS_MASK */
1733 
 
1734 
#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
1735 
#define        nDRIVE_VBUS_ON_ENA  0x0
1736 
#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
1737 
#define       nDRIVE_VBUS_OFF_ENA  0x0
1738 
#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
1739 
#define      nCHRG_VBUS_START_ENA  0x0
1740 
#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
1741 
#define        nCHRG_VBUS_END_ENA  0x0
1742 
#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
1743 
#define   nDISCHRG_VBUS_START_ENA  0x0
1744 
#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
1745 
#define     nDISCHRG_VBUS_END_ENA  0x0
1746 
 
1747 
/* Bit masks for USB_CSR0 */
1748 
 
1749 
#define                  RXPKTRDY  0x1        /* data packet receive indicator */
1750 
#define                 nRXPKTRDY  0x0
1751 
#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
1752 
#define                 nTXPKTRDY  0x0
1753 
#define                STALL_SENT  0x4        /* STALL handshake sent */
1754 
#define               nSTALL_SENT  0x0
1755 
#define                   DATAEND  0x8        /* Data end indicator */
1756 
#define                  nDATAEND  0x0
1757 
#define                  SETUPEND  0x10       /* Setup end */
1758 
#define                 nSETUPEND  0x0
1759 
#define                 SENDSTALL  0x20       /* Send STALL handshake */
1760 
#define                nSENDSTALL  0x0
1761 
#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
1762 
#define        nSERVICED_RXPKTRDY  0x0
1763 
#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
1764 
#define        nSERVICED_SETUPEND  0x0
1765 
#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
1766 
#define                nFLUSHFIFO  0x0
1767 
#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
1768 
#define         nSTALL_RECEIVED_H  0x0
1769 
#define                SETUPPKT_H  0x8        /* send Setup token host mode */
1770 
#define               nSETUPPKT_H  0x0
1771 
#define                   ERROR_H  0x10       /* timeout error indicator host mode */
1772 
#define                  nERROR_H  0x0
1773 
#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
1774 
#define                 nREQPKT_H  0x0
1775 
#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
1776 
#define              nSTATUSPKT_H  0x0
1777 
#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
1778 
#define            nNAK_TIMEOUT_H  0x0
1779 
 
1780 
/* Bit masks for USB_COUNT0 */
1781 
 
1782 
#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
1783 
 
1784 
/* Bit masks for USB_NAKLIMIT0 */
1785 
 
1786 
#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
1787 
 
1788 
/* Bit masks for USB_TX_MAX_PACKET */
1789 
 
1790 
#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
1791 
 
1792 
/* Bit masks for USB_RX_MAX_PACKET */
1793 
 
1794 
#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
1795 
 
1796 
/* Bit masks for USB_TXCSR */
1797 
 
1798 
#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
1799 
#define               nTXPKTRDY_T  0x0
1800 
#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
1801 
#define         nFIFO_NOT_EMPTY_T  0x0
1802 
#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
1803 
#define               nUNDERRUN_T  0x0
1804 
#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
1805 
#define              nFLUSHFIFO_T  0x0
1806 
#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
1807 
#define             nSTALL_SEND_T  0x0
1808 
#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
1809 
#define             nSTALL_SENT_T  0x0
1810 
#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
1811 
#define       nCLEAR_DATATOGGLE_T  0x0
1812 
#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
1813 
#define               nINCOMPTX_T  0x0
1814 
#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
1815 
#define             nDMAREQMODE_T  0x0
1816 
#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
1817 
#define       nFORCE_DATATOGGLE_T  0x0
1818 
#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
1819 
#define             nDMAREQ_ENA_T  0x0
1820 
#define                     ISO_T  0x4000     /* enable Isochronous transfers */
1821 
#define                    nISO_T  0x0
1822 
#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
1823 
#define                nAUTOSET_T  0x0
1824 
#define                  ERROR_TH  0x4        /* error condition host mode */
1825 
#define                 nERROR_TH  0x0
1826 
#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
1827 
#define        nSTALL_RECEIVED_TH  0x0
1828 
#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
1829 
#define           nNAK_TIMEOUT_TH  0x0
1830 
 
1831 
/* Bit masks for USB_TXCOUNT */
1832 
 
1833 
#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
1834 
 
1835 
/* Bit masks for USB_RXCSR */
1836 
 
1837 
#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
1838 
#define               nRXPKTRDY_R  0x0
1839 
#define               FIFO_FULL_R  0x2        /* FIFO not empty */
1840 
#define              nFIFO_FULL_R  0x0
1841 
#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
1842 
#define                nOVERRUN_R  0x0
1843 
#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
1844 
#define              nDATAERROR_R  0x0
1845 
#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
1846 
#define              nFLUSHFIFO_R  0x0
1847 
#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
1848 
#define             nSTALL_SEND_R  0x0
1849 
#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
1850 
#define             nSTALL_SENT_R  0x0
1851 
#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
1852 
#define       nCLEAR_DATATOGGLE_R  0x0
1853 
#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
1854 
#define               nINCOMPRX_R  0x0
1855 
#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
1856 
#define             nDMAREQMODE_R  0x0
1857 
#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
1858 
#define                nDISNYET_R  0x0
1859 
#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
1860 
#define             nDMAREQ_ENA_R  0x0
1861 
#define                     ISO_R  0x4000     /* enable Isochronous transfers */
1862 
#define                    nISO_R  0x0
1863 
#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
1864 
#define              nAUTOCLEAR_R  0x0
1865 
#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
1866 
#define                 nERROR_RH  0x0
1867 
#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
1868 
#define                nREQPKT_RH  0x0
1869 
#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
1870 
#define        nSTALL_RECEIVED_RH  0x0
1871 
#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
1872 
#define              nINCOMPRX_RH  0x0
1873 
#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
1874 
#define            nDMAREQMODE_RH  0x0
1875 
#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
1876 
#define               nAUTOREQ_RH  0x0
1877 
 
1878 
/* Bit masks for USB_RXCOUNT */
1879 
 
1880 
#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
1881 
 
1882 
/* Bit masks for USB_TXTYPE */
1883 
 
1884 
#define            TARGET_EP_NO_T  0xf        /* EP number */
1885 
#define                PROTOCOL_T  0xc        /* transfer type */
1886 
 
1887 
/* Bit masks for USB_TXINTERVAL */
1888 
 
1889 
#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
1890 
 
1891 
/* Bit masks for USB_RXTYPE */
1892 
 
1893 
#define            TARGET_EP_NO_R  0xf        /* EP number */
1894 
#define                PROTOCOL_R  0xc        /* transfer type */
1895 
 
1896 
/* Bit masks for USB_RXINTERVAL */
1897 
 
1898 
#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
1899 
 
1900 
/* Bit masks for USB_DMA_INTERRUPT */
1901 
 
1902 
#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
1903 
#define                 nDMA0_INT  0x0
1904 
#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
1905 
#define                 nDMA1_INT  0x0
1906 
#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
1907 
#define                 nDMA2_INT  0x0
1908 
#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
1909 
#define                 nDMA3_INT  0x0
1910 
#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
1911 
#define                 nDMA4_INT  0x0
1912 
#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
1913 
#define                 nDMA5_INT  0x0
1914 
#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
1915 
#define                 nDMA6_INT  0x0
1916 
#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
1917 
#define                 nDMA7_INT  0x0
1918 
 
1919 
/* Bit masks for USB_DMAxCONTROL */
1920 
 
1921 
#define                   DMA_ENA  0x1        /* DMA enable */
1922 
#define                  nDMA_ENA  0x0
1923 
#define                 DIRECTION  0x2        /* direction of DMA transfer */
1924 
#define                nDIRECTION  0x0
1925 
#define                      MODE  0x4        /* DMA Bus error */
1926 
#define                     nMODE  0x0
1927 
#define                   INT_ENA  0x8        /* Interrupt enable */
1928 
#define                  nINT_ENA  0x0
1929 
#define                     EPNUM  0xf0       /* EP number */
1930 
#define                  BUSERROR  0x100      /* DMA Bus error */
1931 
#define                 nBUSERROR  0x0
1932 
 
1933 
/* Bit masks for USB_DMAxADDRHIGH */
1934 
 
1935 
#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
1936 
 
1937 
/* Bit masks for USB_DMAxADDRLOW */
1938 
 
1939 
#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
1940 
 
1941 
/* Bit masks for USB_DMAxCOUNTHIGH */
1942 
 
1943 
#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1944 
 
1945 
/* Bit masks for USB_DMAxCOUNTLOW */
1946 
 
1947 
#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1948 
 
1949 
/* ******************************************* */
1950 
/*     MULTI BIT MACRO ENUMERATIONS            */
1951 
/* ******************************************* */
1952 
 
1953 
#ifdef _MISRA_RULES
1954 
#pragma diag(pop)
1955 
#endif /* _MISRA_RULES */
1956 
 
1957 
#endif /* _DEF_BF548_H */

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