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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* defBF561.h
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*
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* Copyright (C) 2008, 2009 Analog Devices, Inc.
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*
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************************************************************************/
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/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
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#ifndef _DEF_BF561_H
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#define _DEF_BF561_H
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#if !defined(__ADSPBF561__)
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#warning defBF561.h should only be included for BF561 chip.
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#endif
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/* include all Core registers and bit definitions */
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#include <def_LPBlackfin.h>
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4)
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#pragma diag(suppress:misra_rule_19_7)
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#endif /* _MISRA_RULES */
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/*********************************************************************************** */
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/* System MMR Register Map */
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/*********************************************************************************** */
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/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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| 44 |
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#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
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#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
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#define CHIPID 0xFFC00014 /* Device ID Register */
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| 51 |
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define SICA_SWRST 0xFFC00100 /* Software Reset register */
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#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
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#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
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#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
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#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
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#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
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#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
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#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
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#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
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#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
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#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
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#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
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#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
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#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
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#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
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#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
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#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
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#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
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/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
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#define SICB_SWRST 0xFFC01100 /* reserved */
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#define SICB_SYSCR 0xFFC01104 /* reserved */
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#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
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#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
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#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
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#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
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#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
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#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
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| 81 |
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#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
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| 82 |
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#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
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#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
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#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
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#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
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#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
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#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
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#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
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#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
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| 90 |
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| 91 |
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| 92 |
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/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
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#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
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#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
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#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
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| 97 |
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| 98 |
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/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
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#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
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#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
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#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
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| 103 |
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| 104 |
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/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART_THR 0xFFC00400 /* Transmit Holding register */
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#define UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART_LCR 0xFFC0040C /* Line Control Register */
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#define UART_MCR 0xFFC00410 /* Modem Control Register */
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#define UART_LSR 0xFFC00414 /* Line Status Register */
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#define UART_MSR 0xFFC00418 /* Modem Status Register */
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#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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| 118 |
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| 119 |
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
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#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
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#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
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#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
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| 128 |
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| 129 |
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/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
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#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
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#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
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#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
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#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
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| 135 |
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#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
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#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
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#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
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#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
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#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
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#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
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#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
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#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
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#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
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#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
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#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
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#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
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| 150 |
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#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
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#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
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#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
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| 153 |
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#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
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| 155 |
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#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
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#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
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| 157 |
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#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
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| 158 |
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#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
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| 159 |
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| 160 |
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#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
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| 161 |
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#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
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| 162 |
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#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
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| 163 |
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#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
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#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
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| 166 |
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#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
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| 167 |
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#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
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| 168 |
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#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
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| 170 |
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#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
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| 171 |
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#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
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#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
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| 174 |
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/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
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#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
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#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
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| 178 |
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#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
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| 179 |
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#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
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| 180 |
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| 181 |
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#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
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| 182 |
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#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
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| 183 |
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#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
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| 184 |
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#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
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| 185 |
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| 186 |
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#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
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| 187 |
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#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
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| 188 |
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#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
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| 189 |
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#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
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| 190 |
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| 191 |
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#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
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| 192 |
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#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
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| 193 |
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#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
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| 194 |
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#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
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| 195 |
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| 196 |
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#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
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| 197 |
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#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
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| 198 |
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#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
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| 200 |
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| 201 |
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/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
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#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
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| 203 |
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#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
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| 204 |
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#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
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| 205 |
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#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
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| 206 |
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#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
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| 207 |
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#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
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| 208 |
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#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
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| 209 |
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#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
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| 210 |
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#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
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| 211 |
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#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
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| 212 |
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#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
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| 213 |
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#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
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| 214 |
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#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
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| 215 |
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#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
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| 216 |
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#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
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| 217 |
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#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
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| 218 |
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#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
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| 219 |
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| 220 |
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| 221 |
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/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
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| 222 |
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#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
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| 223 |
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#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
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| 224 |
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#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
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| 225 |
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#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
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| 226 |
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#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
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| 227 |
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#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
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| 228 |
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#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
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| 229 |
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#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
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| 230 |
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#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
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| 231 |
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#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
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| 232 |
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#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
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| 233 |
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#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
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| 234 |
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#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
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| 235 |
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#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
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| 236 |
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#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
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| 237 |
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#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
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| 238 |
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#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
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| 239 |
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| 240 |
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| 241 |
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/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
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| 242 |
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#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
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| 243 |
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#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
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| 244 |
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#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
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| 245 |
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#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
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| 246 |
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#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
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| 247 |
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#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
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| 248 |
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#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
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| 249 |
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#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
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| 250 |
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#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
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| 251 |
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#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
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| 252 |
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#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
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| 253 |
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#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
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| 254 |
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#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
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| 255 |
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#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
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| 256 |
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#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
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| 257 |
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#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
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| 258 |
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#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
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| 259 |
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| 260 |
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| 261 |
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/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
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| 262 |
|
|
#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
|
| 263 |
|
|
#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
|
| 264 |
|
|
#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
|
| 265 |
|
|
#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
|
| 266 |
|
|
#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
|
| 267 |
|
|
#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
|
| 268 |
|
|
#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
|
| 269 |
|
|
#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
|
| 270 |
|
|
#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
|
| 271 |
|
|
#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
|
| 272 |
|
|
#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
|
| 273 |
|
|
#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
|
| 274 |
|
|
#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
|
| 275 |
|
|
#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
|
| 276 |
|
|
#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
|
| 277 |
|
|
#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
|
| 278 |
|
|
#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
|
| 279 |
|
|
#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
|
| 280 |
|
|
#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
|
| 281 |
|
|
#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
|
| 282 |
|
|
#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
|
| 283 |
|
|
#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
|
| 284 |
|
|
|
| 285 |
|
|
|
| 286 |
|
|
/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
|
| 287 |
|
|
#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
|
| 288 |
|
|
#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
|
| 289 |
|
|
#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
|
| 290 |
|
|
#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
|
| 291 |
|
|
#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
|
| 292 |
|
|
#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
|
| 293 |
|
|
#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
|
| 294 |
|
|
#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
|
| 295 |
|
|
#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
|
| 296 |
|
|
#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
|
| 297 |
|
|
#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
|
| 298 |
|
|
#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
|
| 299 |
|
|
#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
|
| 300 |
|
|
#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
|
| 301 |
|
|
#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
|
| 302 |
|
|
#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
|
| 303 |
|
|
#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
|
| 304 |
|
|
#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
|
| 305 |
|
|
#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
|
| 306 |
|
|
#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
|
| 307 |
|
|
#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
|
| 308 |
|
|
#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
|
| 309 |
|
|
|
| 310 |
|
|
|
| 311 |
|
|
/* Asynchronous Memory Controller - External Bus Interface Unit */
|
| 312 |
|
|
#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
|
| 313 |
|
|
#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
|
| 314 |
|
|
#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
|
| 318 |
|
|
#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
|
| 319 |
|
|
#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
|
| 320 |
|
|
#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
|
| 321 |
|
|
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
|
| 325 |
|
|
#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
|
| 326 |
|
|
#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
|
| 327 |
|
|
#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
|
| 328 |
|
|
#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
|
| 329 |
|
|
#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
|
|
/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
|
| 333 |
|
|
#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
|
| 334 |
|
|
#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
|
| 335 |
|
|
#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
|
| 336 |
|
|
#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
|
| 337 |
|
|
#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
/*DMA traffic control registers */
|
| 341 |
|
|
#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */
|
| 342 |
|
|
#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
|
| 343 |
|
|
#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */
|
| 344 |
|
|
#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
|
| 348 |
|
|
#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
|
| 349 |
|
|
#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
|
| 350 |
|
|
#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
|
| 351 |
|
|
#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
|
| 352 |
|
|
#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
|
| 353 |
|
|
#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
|
| 354 |
|
|
#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
|
| 355 |
|
|
#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
|
| 356 |
|
|
#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
|
| 357 |
|
|
#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
|
| 358 |
|
|
#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
|
| 359 |
|
|
#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
|
| 360 |
|
|
#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
|
| 361 |
|
|
|
| 362 |
|
|
#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
|
| 363 |
|
|
#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
|
| 364 |
|
|
#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
|
| 365 |
|
|
#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
|
| 366 |
|
|
#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
|
| 367 |
|
|
#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
|
| 368 |
|
|
#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
|
| 369 |
|
|
#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
|
| 370 |
|
|
#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
|
| 371 |
|
|
#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
|
| 372 |
|
|
#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
|
| 373 |
|
|
#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
|
| 374 |
|
|
#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
|
| 375 |
|
|
|
| 376 |
|
|
#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
|
| 377 |
|
|
#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
|
| 378 |
|
|
#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
|
| 379 |
|
|
#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
|
| 380 |
|
|
#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
|
| 381 |
|
|
#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
|
| 382 |
|
|
#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
|
| 383 |
|
|
#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
|
| 384 |
|
|
#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
|
| 385 |
|
|
#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
|
| 386 |
|
|
#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
|
| 387 |
|
|
#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
|
| 388 |
|
|
#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
|
| 389 |
|
|
|
| 390 |
|
|
#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
|
| 391 |
|
|
#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
|
| 392 |
|
|
#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
|
| 393 |
|
|
#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
|
| 394 |
|
|
#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
|
| 395 |
|
|
#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
|
| 396 |
|
|
#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
|
| 397 |
|
|
#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
|
| 398 |
|
|
#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
|
| 399 |
|
|
#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
|
| 400 |
|
|
#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
|
| 401 |
|
|
#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
|
| 402 |
|
|
#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
|
| 403 |
|
|
|
| 404 |
|
|
#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
|
| 405 |
|
|
#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
|
| 406 |
|
|
#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
|
| 407 |
|
|
#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
|
| 408 |
|
|
#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
|
| 409 |
|
|
#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
|
| 410 |
|
|
#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
|
| 411 |
|
|
#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
|
| 412 |
|
|
#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
|
| 413 |
|
|
#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
|
| 414 |
|
|
#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
|
| 415 |
|
|
#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
|
| 416 |
|
|
#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
|
| 417 |
|
|
|
| 418 |
|
|
#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
|
| 419 |
|
|
#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
|
| 420 |
|
|
#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
|
| 421 |
|
|
#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
|
| 422 |
|
|
#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
|
| 423 |
|
|
#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
|
| 424 |
|
|
#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
|
| 425 |
|
|
#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
|
| 426 |
|
|
#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
|
| 427 |
|
|
#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
|
| 428 |
|
|
#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
|
| 429 |
|
|
#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
|
| 430 |
|
|
#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
|
| 431 |
|
|
|
| 432 |
|
|
#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
|
| 433 |
|
|
#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
|
| 434 |
|
|
#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
|
| 435 |
|
|
#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
|
| 436 |
|
|
#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
|
| 437 |
|
|
#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
|
| 438 |
|
|
#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
|
| 439 |
|
|
#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
|
| 440 |
|
|
#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
|
| 441 |
|
|
#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
|
| 442 |
|
|
#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
|
| 443 |
|
|
#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
|
| 444 |
|
|
#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
|
| 445 |
|
|
|
| 446 |
|
|
#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
|
| 447 |
|
|
#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
|
| 448 |
|
|
#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
|
| 449 |
|
|
#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
|
| 450 |
|
|
#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
|
| 451 |
|
|
#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
|
| 452 |
|
|
#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
|
| 453 |
|
|
#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
|
| 454 |
|
|
#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
|
| 455 |
|
|
#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
|
| 456 |
|
|
#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
|
| 457 |
|
|
#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
|
| 458 |
|
|
#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
|
| 459 |
|
|
|
| 460 |
|
|
#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
|
| 461 |
|
|
#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
|
| 462 |
|
|
#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
|
| 463 |
|
|
#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
|
| 464 |
|
|
#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
|
| 465 |
|
|
#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
|
| 466 |
|
|
#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
|
| 467 |
|
|
#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
|
| 468 |
|
|
#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
|
| 469 |
|
|
#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
|
| 470 |
|
|
#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
|
| 471 |
|
|
#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
|
| 472 |
|
|
#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
|
| 473 |
|
|
|
| 474 |
|
|
#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
|
| 475 |
|
|
#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
|
| 476 |
|
|
#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
|
| 477 |
|
|
#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
|
| 478 |
|
|
#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
|
| 479 |
|
|
#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
|
| 480 |
|
|
#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
|
| 481 |
|
|
#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
|
| 482 |
|
|
#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
|
| 483 |
|
|
#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
|
| 484 |
|
|
#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
|
| 485 |
|
|
#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
|
| 486 |
|
|
#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
|
| 487 |
|
|
|
| 488 |
|
|
#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
|
| 489 |
|
|
#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
|
| 490 |
|
|
#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
|
| 491 |
|
|
#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
|
| 492 |
|
|
#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
|
| 493 |
|
|
#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
|
| 494 |
|
|
#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
|
| 495 |
|
|
#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
|
| 496 |
|
|
#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
|
| 497 |
|
|
#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
|
| 498 |
|
|
#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
|
| 499 |
|
|
#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
|
| 500 |
|
|
#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
|
| 501 |
|
|
|
| 502 |
|
|
#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
|
| 503 |
|
|
#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
|
| 504 |
|
|
#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
|
| 505 |
|
|
#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
|
| 506 |
|
|
#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
|
| 507 |
|
|
#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
|
| 508 |
|
|
#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
|
| 509 |
|
|
#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
|
| 510 |
|
|
#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
|
| 511 |
|
|
#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
|
| 512 |
|
|
#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
|
| 513 |
|
|
#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
|
| 514 |
|
|
#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
|
| 515 |
|
|
|
| 516 |
|
|
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
|
| 517 |
|
|
#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
|
| 518 |
|
|
#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
|
| 519 |
|
|
#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
|
| 520 |
|
|
#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
|
| 521 |
|
|
#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
|
| 522 |
|
|
#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
|
| 523 |
|
|
#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
|
| 524 |
|
|
#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
|
| 525 |
|
|
#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
|
| 526 |
|
|
#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
|
| 527 |
|
|
#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
|
| 528 |
|
|
#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
|
| 529 |
|
|
#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
|
| 530 |
|
|
|
| 531 |
|
|
#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
|
| 532 |
|
|
#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
|
| 533 |
|
|
#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
|
| 534 |
|
|
#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
|
| 535 |
|
|
#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
|
| 536 |
|
|
#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
|
| 537 |
|
|
#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
|
| 538 |
|
|
#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
|
| 539 |
|
|
#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
|
| 540 |
|
|
#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
|
| 541 |
|
|
#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
|
| 542 |
|
|
#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
|
| 543 |
|
|
#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
|
| 544 |
|
|
|
| 545 |
|
|
#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
|
| 546 |
|
|
#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
|
| 547 |
|
|
#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
|
| 548 |
|
|
#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
|
| 549 |
|
|
#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
|
| 550 |
|
|
#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
|
| 551 |
|
|
#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
|
| 552 |
|
|
#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
|
| 553 |
|
|
#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
|
| 554 |
|
|
#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
|
| 555 |
|
|
#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
|
| 556 |
|
|
#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
|
| 557 |
|
|
#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
|
| 558 |
|
|
|
| 559 |
|
|
#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
|
| 560 |
|
|
#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
|
| 561 |
|
|
#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
|
| 562 |
|
|
#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
|
| 563 |
|
|
#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
|
| 564 |
|
|
#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
|
| 565 |
|
|
#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
|
| 566 |
|
|
#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
|
| 567 |
|
|
#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
|
| 568 |
|
|
#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
|
| 569 |
|
|
#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
|
| 570 |
|
|
#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
|
| 571 |
|
|
#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
|
| 575 |
|
|
#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
|
| 576 |
|
|
#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
|
| 577 |
|
|
#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
|
| 578 |
|
|
#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
|
| 579 |
|
|
#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
|
| 580 |
|
|
#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
|
| 581 |
|
|
#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
|
| 582 |
|
|
#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
|
| 583 |
|
|
#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
|
| 584 |
|
|
#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
|
| 585 |
|
|
#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
|
| 586 |
|
|
#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
|
| 587 |
|
|
#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
|
| 588 |
|
|
|
| 589 |
|
|
#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
|
| 590 |
|
|
#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
|
| 591 |
|
|
#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
|
| 592 |
|
|
#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
|
| 593 |
|
|
#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
|
| 594 |
|
|
#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
|
| 595 |
|
|
#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
|
| 596 |
|
|
#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
|
| 597 |
|
|
#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
|
| 598 |
|
|
#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
|
| 599 |
|
|
#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
|
| 600 |
|
|
#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
|
| 601 |
|
|
#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
|
| 602 |
|
|
|
| 603 |
|
|
#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
|
| 604 |
|
|
#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
|
| 605 |
|
|
#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
|
| 606 |
|
|
#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
|
| 607 |
|
|
#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
|
| 608 |
|
|
#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
|
| 609 |
|
|
#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
|
| 610 |
|
|
#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
|
| 611 |
|
|
#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
|
| 612 |
|
|
#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
|
| 613 |
|
|
#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
|
| 614 |
|
|
#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
|
| 615 |
|
|
#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
|
| 616 |
|
|
|
| 617 |
|
|
#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
|
| 618 |
|
|
#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
|
| 619 |
|
|
#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
|
| 620 |
|
|
#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
|
| 621 |
|
|
#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
|
| 622 |
|
|
#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
|
| 623 |
|
|
#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
|
| 624 |
|
|
#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
|
| 625 |
|
|
#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
|
| 626 |
|
|
#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
|
| 627 |
|
|
#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
|
| 628 |
|
|
#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
|
| 629 |
|
|
#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
|
| 630 |
|
|
|
| 631 |
|
|
#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
|
| 632 |
|
|
#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
|
| 633 |
|
|
#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
|
| 634 |
|
|
#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
|
| 635 |
|
|
#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
|
| 636 |
|
|
#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
|
| 637 |
|
|
#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
|
| 638 |
|
|
#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
|
| 639 |
|
|
#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
|
| 640 |
|
|
#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
|
| 641 |
|
|
#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
|
| 642 |
|
|
#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
|
| 643 |
|
|
#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
|
| 644 |
|
|
|
| 645 |
|
|
#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
|
| 646 |
|
|
#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
|
| 647 |
|
|
#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
|
| 648 |
|
|
#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
|
| 649 |
|
|
#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
|
| 650 |
|
|
#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
|
| 651 |
|
|
#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
|
| 652 |
|
|
#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
|
| 653 |
|
|
#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
|
| 654 |
|
|
#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
|
| 655 |
|
|
#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
|
| 656 |
|
|
#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
|
| 657 |
|
|
#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
|
| 658 |
|
|
|
| 659 |
|
|
#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
|
| 660 |
|
|
#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
|
| 661 |
|
|
#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
|
| 662 |
|
|
#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
|
| 663 |
|
|
#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
|
| 664 |
|
|
#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
|
| 665 |
|
|
#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
|
| 666 |
|
|
#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
|
| 667 |
|
|
#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
|
| 668 |
|
|
#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
|
| 669 |
|
|
#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
|
| 670 |
|
|
#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
|
| 671 |
|
|
#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
|
| 672 |
|
|
|
| 673 |
|
|
#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
|
| 674 |
|
|
#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
|
| 675 |
|
|
#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
|
| 676 |
|
|
#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
|
| 677 |
|
|
#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
|
| 678 |
|
|
#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
|
| 679 |
|
|
#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
|
| 680 |
|
|
#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
|
| 681 |
|
|
#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
|
| 682 |
|
|
#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
|
| 683 |
|
|
#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
|
| 684 |
|
|
#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
|
| 685 |
|
|
#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
|
| 686 |
|
|
|
| 687 |
|
|
#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
|
| 688 |
|
|
#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
|
| 689 |
|
|
#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
|
| 690 |
|
|
#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
|
| 691 |
|
|
#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
|
| 692 |
|
|
#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
|
| 693 |
|
|
#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
|
| 694 |
|
|
#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
|
| 695 |
|
|
#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
|
| 696 |
|
|
#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
|
| 697 |
|
|
#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
|
| 698 |
|
|
#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
|
| 699 |
|
|
#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
|
| 700 |
|
|
|
| 701 |
|
|
#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
|
| 702 |
|
|
#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
|
| 703 |
|
|
#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
|
| 704 |
|
|
#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
|
| 705 |
|
|
#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
|
| 706 |
|
|
#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
|
| 707 |
|
|
#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
|
| 708 |
|
|
#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
|
| 709 |
|
|
#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
|
| 710 |
|
|
#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
|
| 711 |
|
|
#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
|
| 712 |
|
|
#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
|
| 713 |
|
|
#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
|
| 714 |
|
|
|
| 715 |
|
|
#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
|
| 716 |
|
|
#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
|
| 717 |
|
|
#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
|
| 718 |
|
|
#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
|
| 719 |
|
|
#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
|
| 720 |
|
|
#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
|
| 721 |
|
|
#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
|
| 722 |
|
|
#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
|
| 723 |
|
|
#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
|
| 724 |
|
|
#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
|
| 725 |
|
|
#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
|
| 726 |
|
|
#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
|
| 727 |
|
|
#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
|
| 728 |
|
|
|
| 729 |
|
|
#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
|
| 730 |
|
|
#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
|
| 731 |
|
|
#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
|
| 732 |
|
|
#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
|
| 733 |
|
|
#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
|
| 734 |
|
|
#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
|
| 735 |
|
|
#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
|
| 736 |
|
|
#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
|
| 737 |
|
|
#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
|
| 738 |
|
|
#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
|
| 739 |
|
|
#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
|
| 740 |
|
|
#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
|
| 741 |
|
|
#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
|
| 742 |
|
|
|
| 743 |
|
|
|
| 744 |
|
|
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
|
| 745 |
|
|
#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
|
| 746 |
|
|
#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
|
| 747 |
|
|
#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
|
| 748 |
|
|
#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
|
| 749 |
|
|
#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
|
| 750 |
|
|
#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
|
| 751 |
|
|
#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
|
| 752 |
|
|
#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
|
| 753 |
|
|
#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
|
| 754 |
|
|
#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
|
| 755 |
|
|
#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
|
| 756 |
|
|
#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
|
| 757 |
|
|
#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
|
| 758 |
|
|
|
| 759 |
|
|
#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
|
| 760 |
|
|
#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
|
| 761 |
|
|
#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
|
| 762 |
|
|
#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
|
| 763 |
|
|
#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
|
| 764 |
|
|
#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
|
| 765 |
|
|
#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
|
| 766 |
|
|
#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
|
| 767 |
|
|
#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
|
| 768 |
|
|
#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
|
| 769 |
|
|
#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
|
| 770 |
|
|
#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
|
| 771 |
|
|
#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
|
| 772 |
|
|
|
| 773 |
|
|
#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
|
| 774 |
|
|
#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
|
| 775 |
|
|
#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
|
| 776 |
|
|
#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
|
| 777 |
|
|
#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
|
| 778 |
|
|
#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
|
| 779 |
|
|
#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
|
| 780 |
|
|
#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
|
| 781 |
|
|
#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
|
| 782 |
|
|
#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
|
| 783 |
|
|
#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
|
| 784 |
|
|
#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
|
| 785 |
|
|
#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
|
| 786 |
|
|
|
| 787 |
|
|
#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
|
| 788 |
|
|
#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
|
| 789 |
|
|
#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
|
| 790 |
|
|
#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
|
| 791 |
|
|
#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
|
| 792 |
|
|
#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
|
| 793 |
|
|
#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
|
| 794 |
|
|
#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
|
| 795 |
|
|
#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
|
| 796 |
|
|
#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
|
| 797 |
|
|
#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
|
| 798 |
|
|
#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
|
| 799 |
|
|
#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
|
| 800 |
|
|
|
| 801 |
|
|
|
| 802 |
|
|
|
| 803 |
|
|
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
|
| 804 |
|
|
#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
|
| 805 |
|
|
#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
|
| 806 |
|
|
#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
|
| 807 |
|
|
#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
|
| 808 |
|
|
#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
|
| 809 |
|
|
#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
|
| 810 |
|
|
#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
|
| 811 |
|
|
#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
|
| 812 |
|
|
#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
|
| 813 |
|
|
#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
|
| 814 |
|
|
#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
|
| 815 |
|
|
#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
|
| 816 |
|
|
|
| 817 |
|
|
#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
|
| 818 |
|
|
#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
|
| 819 |
|
|
#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
|
| 820 |
|
|
#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
|
| 821 |
|
|
#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
|
| 822 |
|
|
#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
|
| 823 |
|
|
#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
|
| 824 |
|
|
#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
|
| 825 |
|
|
#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
|
| 826 |
|
|
#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
|
| 827 |
|
|
#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
|
| 828 |
|
|
#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
|
| 829 |
|
|
|
| 830 |
|
|
#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
|
| 831 |
|
|
#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
|
| 832 |
|
|
#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
|
| 833 |
|
|
#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
|
| 834 |
|
|
#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
|
| 835 |
|
|
#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
|
| 836 |
|
|
#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
|
| 837 |
|
|
#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
|
| 838 |
|
|
#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
|
| 839 |
|
|
#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
|
| 840 |
|
|
#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
|
| 841 |
|
|
#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
|
| 842 |
|
|
|
| 843 |
|
|
#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
|
| 844 |
|
|
#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
|
| 845 |
|
|
#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
|
| 846 |
|
|
#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
|
| 847 |
|
|
#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
|
| 848 |
|
|
#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
|
| 849 |
|
|
#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
|
| 850 |
|
|
#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
|
| 851 |
|
|
#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
|
| 852 |
|
|
#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
|
| 853 |
|
|
#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
|
| 854 |
|
|
#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
|
| 855 |
|
|
|
| 856 |
|
|
|
| 857 |
|
|
|
| 858 |
|
|
/*********************************************************************************** */
|
| 859 |
|
|
/* System MMR Register Bits */
|
| 860 |
|
|
/******************************************************************************* */
|
| 861 |
|
|
|
| 862 |
|
|
/* ********************* PLL AND RESET MASKS ************************ */
|
| 863 |
|
|
|
| 864 |
|
|
/* PLL_CTL Masks */
|
| 865 |
|
|
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
|
| 866 |
|
|
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
|
| 867 |
|
|
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
|
| 868 |
|
|
#define STOPCK_OFF 0x0008 /* Core clock off */
|
| 869 |
|
|
#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing */
|
| 870 |
|
|
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
|
| 871 |
|
|
#define BYPASS 0x0100 /* Bypass the PLL */
|
| 872 |
|
|
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
|
| 873 |
|
|
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
|
| 874 |
|
|
#define IN_DELAY 0x0040 /* Add 200ps Delay on EBIU Inputs */
|
| 875 |
|
|
#define OUT_DELAY 0x0080 /* Add 200ps Delay on EBIU Outputs */
|
| 876 |
|
|
#define SPORT_HYS 0x8000 /* Add 250mV Hysteresis to SPORT Inputs */
|
| 877 |
|
|
|
| 878 |
|
|
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
|
| 879 |
|
|
#ifdef _MISRA_RULES
|
| 880 |
|
|
#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
| 881 |
|
|
#else
|
| 882 |
|
|
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
| 883 |
|
|
#endif /* _MISRA_RULES */
|
| 884 |
|
|
|
| 885 |
|
|
/* PLL_DIV Masks */
|
| 886 |
|
|
#define SSEL 0x000F /* System Select */
|
| 887 |
|
|
#define CSEL 0x0030 /* Core Select */
|
| 888 |
|
|
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
|
| 889 |
|
|
|
| 890 |
|
|
/* PLL_DIV Macros */
|
| 891 |
|
|
#ifdef _MISRA_RULES
|
| 892 |
|
|
#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
| 893 |
|
|
#else
|
| 894 |
|
|
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
| 895 |
|
|
#endif /* _MISRA_RULES */
|
| 896 |
|
|
|
| 897 |
|
|
/* PLL_STAT Macros */
|
| 898 |
|
|
#define VSTAT 0x0080 /* Voltage Regulator Status: Regulator at programmed voltage */
|
| 899 |
|
|
#define CORE_IDLE 0x0040 /* processor is in the IDLE operating mode */
|
| 900 |
|
|
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
|
| 901 |
|
|
#define SLEEP 0x0010 /* processor is in the Sleep operating mode */
|
| 902 |
|
|
#define DEEP_SLEEP 0x0008 /* processor is in the Deep Sleep operating mode */
|
| 903 |
|
|
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
|
| 904 |
|
|
#define FULL_ON 0x0002 /* Processor In Full On Mode */
|
| 905 |
|
|
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
| 906 |
|
|
|
| 907 |
|
|
|
| 908 |
|
|
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
|
| 909 |
|
|
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
|
| 910 |
|
|
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
|
| 911 |
|
|
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
|
| 912 |
|
|
|
| 913 |
|
|
/* SWRST Mask */
|
| 914 |
|
|
#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
|
| 915 |
|
|
#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
|
| 916 |
|
|
#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
|
| 917 |
|
|
#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
|
| 918 |
|
|
#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
|
| 919 |
|
|
#define SWRST_OCCURRED 0x8000 /* SWRST Status */
|
| 920 |
|
|
|
| 921 |
|
|
/* VR_CTL Masks */
|
| 922 |
|
|
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
|
| 923 |
|
|
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
|
| 924 |
|
|
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
|
| 925 |
|
|
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
|
| 926 |
|
|
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
|
| 927 |
|
|
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
| 928 |
|
|
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
|
| 929 |
|
|
|
| 930 |
|
|
|
| 931 |
|
|
#define GAIN 0x000C /* Voltage Level Gain */
|
| 932 |
|
|
#define GAIN_5 0x0000 /* GAIN = 5 */
|
| 933 |
|
|
#define GAIN_10 0x0004 /* GAIN = 10 */
|
| 934 |
|
|
#define GAIN_20 0x0008 /* GAIN = 20 */
|
| 935 |
|
|
#define GAIN_50 0x000C /* GAIN = 50 */
|
| 936 |
|
|
|
| 937 |
|
|
#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
|
| 938 |
|
|
#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
|
| 939 |
|
|
#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
|
| 940 |
|
|
#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
|
| 941 |
|
|
#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
|
| 942 |
|
|
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
|
| 943 |
|
|
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
|
| 944 |
|
|
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
|
| 945 |
|
|
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
|
| 946 |
|
|
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
|
| 947 |
|
|
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
|
| 948 |
|
|
|
| 949 |
|
|
/* SYSCR Masks */
|
| 950 |
|
|
#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
|
| 951 |
|
|
#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
|
| 952 |
|
|
#define BMODE_SPIHOST 0x0002 /* Boot from SPI0 host (slave mode) */
|
| 953 |
|
|
#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
|
| 954 |
|
|
|
| 955 |
|
|
|
| 956 |
|
|
|
| 957 |
|
|
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
|
| 958 |
|
|
|
| 959 |
|
|
/* SICu_IARv Masks */
|
| 960 |
|
|
/* u = A or B */
|
| 961 |
|
|
/* v = 0 to 7 */
|
| 962 |
|
|
/* w = 0 or 1 */
|
| 963 |
|
|
|
| 964 |
|
|
/* Per_number = 0 to 63 */
|
| 965 |
|
|
/* IVG_number = 7 to 15 */
|
| 966 |
|
|
#define Peripheral_IVG(Per_number, IVG_number) \
|
| 967 |
|
|
( (IVG_number) -7) << ( ((Per_number)%8) *4) /* Peripheral #Per_number assigned IVG #IVG_number */
|
| 968 |
|
|
/* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
|
| 969 |
|
|
/* r0.h = hi(Peripheral_IVG(62, 10)); */
|
| 970 |
|
|
|
| 971 |
|
|
|
| 972 |
|
|
|
| 973 |
|
|
/* SICx_IMASKw Masks */
|
| 974 |
|
|
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
|
| 975 |
|
|
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
| 976 |
|
|
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
|
| 977 |
|
|
#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
|
| 978 |
|
|
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
|
| 979 |
|
|
|
| 980 |
|
|
/* SIC_IWR Masks */
|
| 981 |
|
|
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
| 982 |
|
|
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
|
| 983 |
|
|
/* x = pos 0 to 31, for 32-63 use value-32 */
|
| 984 |
|
|
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
|
| 985 |
|
|
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
|
| 986 |
|
|
|
| 987 |
|
|
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
|
| 988 |
|
|
#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
|
| 989 |
|
|
#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt Request */
|
| 990 |
|
|
|
| 991 |
|
|
|
| 992 |
|
|
|
| 993 |
|
|
/* ********* WATCHDOG TIMER MASKS ******************** */
|
| 994 |
|
|
|
| 995 |
|
|
/* Watchdog Timer WDOG_CTL Register Masks */
|
| 996 |
|
|
|
| 997 |
|
|
#ifdef _MISRA_RULES
|
| 998 |
|
|
#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
|
| 999 |
|
|
#else
|
| 1000 |
|
|
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
|
| 1001 |
|
|
#endif /* _MISRA_RULES */
|
| 1002 |
|
|
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
|
| 1003 |
|
|
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
|
| 1004 |
|
|
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
|
| 1005 |
|
|
#define WDEV_NONE 0x0006 /* no event on roll over */
|
| 1006 |
|
|
#define WDEN 0x0FF0 /* enable watchdog */
|
| 1007 |
|
|
#define WDDIS 0x0AD0 /* disable watchdog */
|
| 1008 |
|
|
#define WDRO 0x8000 /* watchdog rolled over latch */
|
| 1009 |
|
|
|
| 1010 |
|
|
/* depreciated WDOG_CTL Register Masks for legacy code */
|
| 1011 |
|
|
|
| 1012 |
|
|
|
| 1013 |
|
|
#define ICTL WDEV
|
| 1014 |
|
|
#define ENABLE_RESET WDEV_RESET
|
| 1015 |
|
|
#define WDOG_RESET WDEV_RESET
|
| 1016 |
|
|
#define ENABLE_NMI WDEV_NMI
|
| 1017 |
|
|
#define WDOG_NMI WDEV_NMI
|
| 1018 |
|
|
#define ENABLE_GPI WDEV_GPI
|
| 1019 |
|
|
#define WDOG_GPI WDEV_GPI
|
| 1020 |
|
|
#define DISABLE_EVT WDEV_NONE
|
| 1021 |
|
|
#define WDOG_NONE WDEV_NONE
|
| 1022 |
|
|
|
| 1023 |
|
|
#define TMR_EN WDEN
|
| 1024 |
|
|
#define WDOG_DISABLE WDDIS
|
| 1025 |
|
|
#define TRO WDRO
|
| 1026 |
|
|
|
| 1027 |
|
|
|
| 1028 |
|
|
|
| 1029 |
|
|
/* ***************************** UART CONTROLLER MASKS ********************** */
|
| 1030 |
|
|
|
| 1031 |
|
|
/* UART_LCR Register */
|
| 1032 |
|
|
|
| 1033 |
|
|
#define DLAB 0x80
|
| 1034 |
|
|
#define SB 0x40
|
| 1035 |
|
|
#define STP 0x20
|
| 1036 |
|
|
#define EPS 0x10
|
| 1037 |
|
|
#define PEN 0x08
|
| 1038 |
|
|
#define STB 0x04
|
| 1039 |
|
|
#ifdef _MISRA_RULES
|
| 1040 |
|
|
#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
|
| 1041 |
|
|
#else
|
| 1042 |
|
|
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
| 1043 |
|
|
#endif /* _MISRA_RULES */
|
| 1044 |
|
|
|
| 1045 |
|
|
#define DLAB_P 0x07
|
| 1046 |
|
|
#define SB_P 0x06
|
| 1047 |
|
|
#define STP_P 0x05
|
| 1048 |
|
|
#define EPS_P 0x04
|
| 1049 |
|
|
#define PEN_P 0x03
|
| 1050 |
|
|
#define STB_P 0x02
|
| 1051 |
|
|
#define WLS_P1 0x01
|
| 1052 |
|
|
#define WLS_P0 0x00
|
| 1053 |
|
|
|
| 1054 |
|
|
/* UART_MCR Register */
|
| 1055 |
|
|
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
|
| 1056 |
|
|
#define LOOP_ENA_P 0x04
|
| 1057 |
|
|
|
| 1058 |
|
|
/* UART_LSR Register */
|
| 1059 |
|
|
#define TEMT 0x40
|
| 1060 |
|
|
#define THRE 0x20
|
| 1061 |
|
|
#define BI 0x10
|
| 1062 |
|
|
#define FE 0x08
|
| 1063 |
|
|
#define PE 0x04
|
| 1064 |
|
|
#define OE 0x02
|
| 1065 |
|
|
#define DR 0x01
|
| 1066 |
|
|
|
| 1067 |
|
|
#define TEMP_P 0x06
|
| 1068 |
|
|
#define THRE_P 0x05
|
| 1069 |
|
|
#define BI_P 0x04
|
| 1070 |
|
|
#define FE_P 0x03
|
| 1071 |
|
|
#define PE_P 0x02
|
| 1072 |
|
|
#define OE_P 0x01
|
| 1073 |
|
|
#define DR_P 0x00
|
| 1074 |
|
|
|
| 1075 |
|
|
/* UART_IER Register */
|
| 1076 |
|
|
#define ELSI 0x04
|
| 1077 |
|
|
#define ETBEI 0x02
|
| 1078 |
|
|
#define ERBFI 0x01
|
| 1079 |
|
|
|
| 1080 |
|
|
#define ELSI_P 0x02
|
| 1081 |
|
|
#define ETBEI_P 0x01
|
| 1082 |
|
|
#define ERBFI_P 0x00
|
| 1083 |
|
|
|
| 1084 |
|
|
/* UART_IIR Register */
|
| 1085 |
|
|
#ifdef _MISRA_RULES
|
| 1086 |
|
|
#define STATUS(x) (((x) << 1) & 0x06u)
|
| 1087 |
|
|
#else
|
| 1088 |
|
|
#define STATUS(x) (((x) << 1) & 0x06)
|
| 1089 |
|
|
#endif /* _MISRA_RULES */
|
| 1090 |
|
|
#define NINT 0x01
|
| 1091 |
|
|
#define STATUS_P1 0x02
|
| 1092 |
|
|
#define STATUS_P0 0x01
|
| 1093 |
|
|
#define NINT_P 0x00
|
| 1094 |
|
|
|
| 1095 |
|
|
/* UART_GCTL Register */
|
| 1096 |
|
|
#define FFE 0x20
|
| 1097 |
|
|
#define FPE 0x10
|
| 1098 |
|
|
#define RPOLC 0x08
|
| 1099 |
|
|
#define TPOLC 0x04
|
| 1100 |
|
|
#define IREN 0x02
|
| 1101 |
|
|
#define UCEN 0x01
|
| 1102 |
|
|
|
| 1103 |
|
|
#define FFE_P 0x05
|
| 1104 |
|
|
#define FPE_P 0x04
|
| 1105 |
|
|
#define RPOLC_P 0x03
|
| 1106 |
|
|
#define TPOLC_P 0x02
|
| 1107 |
|
|
#define IREN_P 0x01
|
| 1108 |
|
|
#define UCEN_P 0x00
|
| 1109 |
|
|
|
| 1110 |
|
|
/* ********** SERIAL PORT MASKS ********************** */
|
| 1111 |
|
|
|
| 1112 |
|
|
/* SPORTx_TCR1 Masks */
|
| 1113 |
|
|
#define TSPEN 0x0001 /* TX enable */
|
| 1114 |
|
|
#define ITCLK 0x0002 /* Internal TX Clock Select */
|
| 1115 |
|
|
#define TDTYPE 0x000C /* TX Data Formatting Select */
|
| 1116 |
|
|
#define TLSBIT 0x0010 /* TX Bit Order */
|
| 1117 |
|
|
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
|
| 1118 |
|
|
#define TFSR 0x0400 /* TX Frame Sync Required Select */
|
| 1119 |
|
|
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
|
| 1120 |
|
|
#define LTFS 0x1000 /* Low TX Frame Sync Select */
|
| 1121 |
|
|
#define LATFS 0x2000 /* Late TX Frame Sync Select */
|
| 1122 |
|
|
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
|
| 1123 |
|
|
|
| 1124 |
|
|
/* SPORTx_TCR2 Masks */
|
| 1125 |
|
|
#define SLEN 0x001F /*TX Word Length */
|
| 1126 |
|
|
#define TXSE 0x0100 /*TX Secondary Enable */
|
| 1127 |
|
|
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
|
| 1128 |
|
|
#define TRFST 0x0400 /*TX Right-First Data Order */
|
| 1129 |
|
|
|
| 1130 |
|
|
/* SPORTx_RCR1 Masks */
|
| 1131 |
|
|
#define RSPEN 0x0001 /* RX enable */
|
| 1132 |
|
|
#define IRCLK 0x0002 /* Internal RX Clock Select */
|
| 1133 |
|
|
#define RDTYPE 0x000C /* RX Data Formatting Select */
|
| 1134 |
|
|
#define RULAW 0x0008 /* u-Law enable */
|
| 1135 |
|
|
#define RALAW 0x000C /* A-Law enable */
|
| 1136 |
|
|
#define RLSBIT 0x0010 /* RX Bit Order */
|
| 1137 |
|
|
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
|
| 1138 |
|
|
#define RFSR 0x0400 /* RX Frame Sync Required Select */
|
| 1139 |
|
|
#define LRFS 0x1000 /* Low RX Frame Sync Select */
|
| 1140 |
|
|
#define LARFS 0x2000 /* Late RX Frame Sync Select */
|
| 1141 |
|
|
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
|
| 1142 |
|
|
|
| 1143 |
|
|
/* SPORTx_RCR2 Masks */
|
| 1144 |
|
|
#define SLEN 0x001F /*RX Word Length */
|
| 1145 |
|
|
#define RXSE 0x0100 /*RX Secondary Enable */
|
| 1146 |
|
|
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
|
| 1147 |
|
|
#define RRFST 0x0400 /*Right-First Data Order */
|
| 1148 |
|
|
|
| 1149 |
|
|
/*SPORTx_STAT Masks */
|
| 1150 |
|
|
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
|
| 1151 |
|
|
#define RUVF 0x0002 /*RX Underflow Status */
|
| 1152 |
|
|
#define ROVF 0x0004 /*RX Overflow Status */
|
| 1153 |
|
|
#define TXF 0x0008 /*TX FIFO Full Status */
|
| 1154 |
|
|
#define TUVF 0x0010 /*TX Underflow Status */
|
| 1155 |
|
|
#define TOVF 0x0020 /*TX Overflow Status */
|
| 1156 |
|
|
#define TXHRE 0x0040 /*TX Hold Register Empty */
|
| 1157 |
|
|
|
| 1158 |
|
|
/*SPORTx_MCMC1 Masks */
|
| 1159 |
|
|
#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
|
| 1160 |
|
|
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
|
| 1161 |
|
|
|
| 1162 |
|
|
/*SPORTx_MCMC2 Masks */
|
| 1163 |
|
|
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
|
| 1164 |
|
|
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
|
| 1165 |
|
|
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
|
| 1166 |
|
|
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
|
| 1167 |
|
|
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
|
| 1168 |
|
|
#define MFD 0x0000F000 /*Multichannel Frame Delay */
|
| 1169 |
|
|
|
| 1170 |
|
|
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
|
| 1171 |
|
|
|
| 1172 |
|
|
/*// PPI_CONTROL Masks */
|
| 1173 |
|
|
#define PORT_EN 0x00000001 /* PPI Port Enable */
|
| 1174 |
|
|
#define PORT_DIR 0x00000002 /* PPI Port Direction */
|
| 1175 |
|
|
#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
|
| 1176 |
|
|
#define PORT_CFG 0x00000030 /* PPI Port Configuration */
|
| 1177 |
|
|
#define FLD_SEL 0x00000040 /* PPI Active Field Select */
|
| 1178 |
|
|
#define PACK_EN 0x00000080 /* PPI Packing Mode */
|
| 1179 |
|
|
#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
|
| 1180 |
|
|
#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
|
| 1181 |
|
|
#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
|
| 1182 |
|
|
#define DLENGTH 0x00003800 /* PPI Data Length */
|
| 1183 |
|
|
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
|
| 1184 |
|
|
#ifdef _MISRA_RULES
|
| 1185 |
|
|
#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
|
| 1186 |
|
|
#else
|
| 1187 |
|
|
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
|
| 1188 |
|
|
#endif /* _MISRA_RULES */
|
| 1189 |
|
|
#define POL 0x0000C000 /* PPI Signal Polarities */
|
| 1190 |
|
|
|
| 1191 |
|
|
|
| 1192 |
|
|
/*// PPI_STATUS Masks */
|
| 1193 |
|
|
#define FLD 0x00000400 /* Field Indicator */
|
| 1194 |
|
|
#define FT_ERR 0x00000800 /* Frame Track Error */
|
| 1195 |
|
|
#define OVR 0x00001000 /* FIFO Overflow Error */
|
| 1196 |
|
|
#define UNDR 0x00002000 /* FIFO Underrun Error */
|
| 1197 |
|
|
#define ERR_DET 0x00004000 /* Error Detected Indicator */
|
| 1198 |
|
|
#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
|
| 1199 |
|
|
|
| 1200 |
|
|
/* ********** DMA CONTROLLER MASKS *********************8 */
|
| 1201 |
|
|
|
| 1202 |
|
|
/*//DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
|
| 1203 |
|
|
#define DMAEN 0x00000001 /* Channel Enable */
|
| 1204 |
|
|
#define WNR 0x00000002 /* Channel Direction (W/R*) */
|
| 1205 |
|
|
#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
|
| 1206 |
|
|
#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
|
| 1207 |
|
|
#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
|
| 1208 |
|
|
#define DMA2D 0x00000010 /* 2D/1D* Mode */
|
| 1209 |
|
|
#define RESTART 0x00000020 /* Restart */
|
| 1210 |
|
|
#define DI_SEL 0x00000040 /* Data Interrupt Select */
|
| 1211 |
|
|
#define DI_EN 0x00000080 /* Data Interrupt Enable */
|
| 1212 |
|
|
#define NDSIZE 0x00000900 /* Next Descriptor Size */
|
| 1213 |
|
|
#define FLOW 0x00007000 /* Flow Control */
|
| 1214 |
|
|
|
| 1215 |
|
|
|
| 1216 |
|
|
#define DMAEN_P 0 /* Channel Enable */
|
| 1217 |
|
|
#define WNR_P 1 /* Channel Direction (W/R*) */
|
| 1218 |
|
|
#define DMA2D_P 4 /* 2D/1D* Mode */
|
| 1219 |
|
|
#define RESTART_P 5 /* Restart */
|
| 1220 |
|
|
#define DI_SEL_P 6 /* Data Interrupt Select */
|
| 1221 |
|
|
#define DI_EN_P 7 /* Data Interrupt Enable */
|
| 1222 |
|
|
|
| 1223 |
|
|
/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
|
| 1224 |
|
|
|
| 1225 |
|
|
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
|
| 1226 |
|
|
#define DMA_ERR 0x00000002 /* DMA Error Indicator */
|
| 1227 |
|
|
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
|
| 1228 |
|
|
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
|
| 1229 |
|
|
|
| 1230 |
|
|
#define DMA_DONE_P 0 /* DMA Done Indicator */
|
| 1231 |
|
|
#define DMA_ERR_P 1 /* DMA Error Indicator */
|
| 1232 |
|
|
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
|
| 1233 |
|
|
#define DMA_RUN_P 3 /* DMA Running Indicator */
|
| 1234 |
|
|
|
| 1235 |
|
|
/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
|
| 1236 |
|
|
|
| 1237 |
|
|
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
|
| 1238 |
|
|
#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
|
| 1239 |
|
|
#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
|
| 1240 |
|
|
#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
|
| 1241 |
|
|
#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
|
| 1242 |
|
|
#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
|
| 1243 |
|
|
#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
|
| 1244 |
|
|
#define PMAP 0x00007000 /* DMA Peripheral Map Field */
|
| 1245 |
|
|
|
| 1246 |
|
|
/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
|
| 1247 |
|
|
|
| 1248 |
|
|
/* PWM Timer bit definitions */
|
| 1249 |
|
|
|
| 1250 |
|
|
/* TIMER_ENABLE Register */
|
| 1251 |
|
|
#define TIMEN0 0x0001
|
| 1252 |
|
|
#define TIMEN1 0x0002
|
| 1253 |
|
|
#define TIMEN2 0x0004
|
| 1254 |
|
|
#define TIMEN3 0x0008
|
| 1255 |
|
|
#define TIMEN4 0x0010
|
| 1256 |
|
|
#define TIMEN5 0x0020
|
| 1257 |
|
|
#define TIMEN6 0x0040
|
| 1258 |
|
|
#define TIMEN7 0x0080
|
| 1259 |
|
|
#define TIMEN8 0x0001
|
| 1260 |
|
|
#define TIMEN9 0x0002
|
| 1261 |
|
|
#define TIMEN10 0x0004
|
| 1262 |
|
|
#define TIMEN11 0x0008
|
| 1263 |
|
|
|
| 1264 |
|
|
#define TIMEN0_P 0x00
|
| 1265 |
|
|
#define TIMEN1_P 0x01
|
| 1266 |
|
|
#define TIMEN2_P 0x02
|
| 1267 |
|
|
#define TIMEN3_P 0x03
|
| 1268 |
|
|
#define TIMEN4_P 0x04
|
| 1269 |
|
|
#define TIMEN5_P 0x05
|
| 1270 |
|
|
#define TIMEN6_P 0x06
|
| 1271 |
|
|
#define TIMEN7_P 0x07
|
| 1272 |
|
|
#define TIMEN8_P 0x00
|
| 1273 |
|
|
#define TIMEN9_P 0x01
|
| 1274 |
|
|
#define TIMEN10_P 0x02
|
| 1275 |
|
|
#define TIMEN11_P 0x03
|
| 1276 |
|
|
|
| 1277 |
|
|
/* TIMER_DISABLE Register */
|
| 1278 |
|
|
#define TIMDIS0 0x0001
|
| 1279 |
|
|
#define TIMDIS1 0x0002
|
| 1280 |
|
|
#define TIMDIS2 0x0004
|
| 1281 |
|
|
#define TIMDIS3 0x0008
|
| 1282 |
|
|
#define TIMDIS4 0x0010
|
| 1283 |
|
|
#define TIMDIS5 0x0020
|
| 1284 |
|
|
#define TIMDIS6 0x0040
|
| 1285 |
|
|
#define TIMDIS7 0x0080
|
| 1286 |
|
|
#define TIMDIS8 0x0001
|
| 1287 |
|
|
#define TIMDIS9 0x0002
|
| 1288 |
|
|
#define TIMDIS10 0x0004
|
| 1289 |
|
|
#define TIMDIS11 0x0008
|
| 1290 |
|
|
|
| 1291 |
|
|
#define TIMDIS0_P 0x00
|
| 1292 |
|
|
#define TIMDIS1_P 0x01
|
| 1293 |
|
|
#define TIMDIS2_P 0x02
|
| 1294 |
|
|
#define TIMDIS3_P 0x03
|
| 1295 |
|
|
#define TIMDIS4_P 0x04
|
| 1296 |
|
|
#define TIMDIS5_P 0x05
|
| 1297 |
|
|
#define TIMDIS6_P 0x06
|
| 1298 |
|
|
#define TIMDIS7_P 0x07
|
| 1299 |
|
|
#define TIMDIS8_P 0x00
|
| 1300 |
|
|
#define TIMDIS9_P 0x01
|
| 1301 |
|
|
#define TIMDIS10_P 0x02
|
| 1302 |
|
|
#define TIMDIS11_P 0x03
|
| 1303 |
|
|
|
| 1304 |
|
|
/* TIMER_STATUS Register */
|
| 1305 |
|
|
#define TIMIL0 0x00000001
|
| 1306 |
|
|
#define TIMIL1 0x00000002
|
| 1307 |
|
|
#define TIMIL2 0x00000004
|
| 1308 |
|
|
#define TIMIL3 0x00000008
|
| 1309 |
|
|
#define TIMIL4 0x00010000
|
| 1310 |
|
|
#define TIMIL5 0x00020000
|
| 1311 |
|
|
#define TIMIL6 0x00040000
|
| 1312 |
|
|
#define TIMIL7 0x00080000
|
| 1313 |
|
|
#define TIMIL8 0x0001
|
| 1314 |
|
|
#define TIMIL9 0x0002
|
| 1315 |
|
|
#define TIMIL10 0x0004
|
| 1316 |
|
|
#define TIMIL11 0x0008
|
| 1317 |
|
|
#define TOVF_ERR0 0x00000010
|
| 1318 |
|
|
#define TOVF_ERR1 0x00000020
|
| 1319 |
|
|
#define TOVF_ERR2 0x00000040
|
| 1320 |
|
|
#define TOVF_ERR3 0x00000080
|
| 1321 |
|
|
#define TOVF_ERR4 0x00100000
|
| 1322 |
|
|
#define TOVF_ERR5 0x00200000
|
| 1323 |
|
|
#define TOVF_ERR6 0x00400000
|
| 1324 |
|
|
#define TOVF_ERR7 0x00800000
|
| 1325 |
|
|
#define TOVF_ERR8 0x0010
|
| 1326 |
|
|
#define TOVF_ERR9 0x0020
|
| 1327 |
|
|
#define TOVF_ERR10 0x0040
|
| 1328 |
|
|
#define TOVF_ERR11 0x0080
|
| 1329 |
|
|
#define TRUN0 0x00001000
|
| 1330 |
|
|
#define TRUN1 0x00002000
|
| 1331 |
|
|
#define TRUN2 0x00004000
|
| 1332 |
|
|
#define TRUN3 0x00008000
|
| 1333 |
|
|
#define TRUN4 0x10000000
|
| 1334 |
|
|
#define TRUN5 0x20000000
|
| 1335 |
|
|
#define TRUN6 0x40000000
|
| 1336 |
|
|
#define TRUN7 0x80000000
|
| 1337 |
|
|
#define TRUN8 0x1000
|
| 1338 |
|
|
#define TRUN9 0x2000
|
| 1339 |
|
|
#define TRUN10 0x4000
|
| 1340 |
|
|
#define TRUN11 0x8000
|
| 1341 |
|
|
|
| 1342 |
|
|
#define TIMIL0_P 0x00
|
| 1343 |
|
|
#define TIMIL1_P 0x01
|
| 1344 |
|
|
#define TIMIL2_P 0x02
|
| 1345 |
|
|
#define TIMIL3_P 0x03
|
| 1346 |
|
|
#define TIMIL4_P 0x10
|
| 1347 |
|
|
#define TIMIL5_P 0x11
|
| 1348 |
|
|
#define TIMIL6_P 0x12
|
| 1349 |
|
|
#define TIMIL7_P 0x13
|
| 1350 |
|
|
#define TIMIL8_P 0x00
|
| 1351 |
|
|
#define TIMIL9_P 0x01
|
| 1352 |
|
|
#define TIMIL10_P 0x02
|
| 1353 |
|
|
#define TIMIL11_P 0x03
|
| 1354 |
|
|
#define TOVF_ERR0_P 0x04
|
| 1355 |
|
|
#define TOVF_ERR1_P 0x05
|
| 1356 |
|
|
#define TOVF_ERR2_P 0x06
|
| 1357 |
|
|
#define TOVF_ERR3_P 0x07
|
| 1358 |
|
|
#define TOVF_ERR4_P 0x14
|
| 1359 |
|
|
#define TOVF_ERR5_P 0x15
|
| 1360 |
|
|
#define TOVF_ERR6_P 0x16
|
| 1361 |
|
|
#define TOVF_ERR7_P 0x17
|
| 1362 |
|
|
#define TOVF_ERR8_P 0x04
|
| 1363 |
|
|
#define TOVF_ERR9_P 0x05
|
| 1364 |
|
|
#define TOVF_ERR10_P 0x06
|
| 1365 |
|
|
#define TOVF_ERR11_P 0x07
|
| 1366 |
|
|
#define TRUN0_P 0x0C
|
| 1367 |
|
|
#define TRUN1_P 0x0D
|
| 1368 |
|
|
#define TRUN2_P 0x0E
|
| 1369 |
|
|
#define TRUN3_P 0x0F
|
| 1370 |
|
|
#define TRUN4_P 0x1C
|
| 1371 |
|
|
#define TRUN5_P 0x1D
|
| 1372 |
|
|
#define TRUN6_P 0x1E
|
| 1373 |
|
|
#define TRUN7_P 0x1F
|
| 1374 |
|
|
#define TRUN8_P 0x0C
|
| 1375 |
|
|
#define TRUN9_P 0x0D
|
| 1376 |
|
|
#define TRUN10_P 0x0E
|
| 1377 |
|
|
#define TRUN11_P 0x0F
|
| 1378 |
|
|
|
| 1379 |
|
|
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
| 1380 |
|
|
#define TOVL_ERR0 TOVF_ERR0
|
| 1381 |
|
|
#define TOVL_ERR1 TOVF_ERR1
|
| 1382 |
|
|
#define TOVL_ERR2 TOVF_ERR2
|
| 1383 |
|
|
#define TOVL_ERR3 TOVF_ERR3
|
| 1384 |
|
|
#define TOVL_ERR4 TOVF_ERR4
|
| 1385 |
|
|
#define TOVL_ERR5 TOVF_ERR5
|
| 1386 |
|
|
#define TOVL_ERR6 TOVF_ERR6
|
| 1387 |
|
|
#define TOVL_ERR7 TOVF_ERR7
|
| 1388 |
|
|
#define TOVL_ERR8 TOVF_ERR8
|
| 1389 |
|
|
#define TOVL_ERR9 TOVF_ERR9
|
| 1390 |
|
|
#define TOVL_ERR10 TOVF_ERR10
|
| 1391 |
|
|
#define TOVL_ERR11 TOVF_ERR11
|
| 1392 |
|
|
#define TOVL_ERR0_P TOVF_ERR0_P
|
| 1393 |
|
|
#define TOVL_ERR1_P TOVF_ERR1_P
|
| 1394 |
|
|
#define TOVL_ERR2_P TOVF_ERR2_P
|
| 1395 |
|
|
#define TOVL_ERR3_P TOVF_ERR3_P
|
| 1396 |
|
|
#define TOVL_ERR4_P TOVF_ERR4_P
|
| 1397 |
|
|
#define TOVL_ERR5_P TOVF_ERR5_P
|
| 1398 |
|
|
#define TOVL_ERR6_P TOVF_ERR6_P
|
| 1399 |
|
|
#define TOVL_ERR7_P TOVF_ERR7_P
|
| 1400 |
|
|
#define TOVL_ERR8_P TOVF_ERR8_P
|
| 1401 |
|
|
#define TOVL_ERR9_P TOVF_ERR9_P
|
| 1402 |
|
|
#define TOVL_ERR10_P TOVF_ERR10_P
|
| 1403 |
|
|
#define TOVL_ERR11_P TOVF_ERR11_P
|
| 1404 |
|
|
|
| 1405 |
|
|
/* TIMERx_CONFIG Registers */
|
| 1406 |
|
|
#define PWM_OUT 0x0001
|
| 1407 |
|
|
#define WDTH_CAP 0x0002
|
| 1408 |
|
|
#define EXT_CLK 0x0003
|
| 1409 |
|
|
#define PULSE_HI 0x0004
|
| 1410 |
|
|
#define PERIOD_CNT 0x0008
|
| 1411 |
|
|
#define IRQ_ENA 0x0010
|
| 1412 |
|
|
#define TIN_SEL 0x0020
|
| 1413 |
|
|
#define OUT_DIS 0x0040
|
| 1414 |
|
|
#define CLK_SEL 0x0080
|
| 1415 |
|
|
#define TOGGLE_HI 0x0100
|
| 1416 |
|
|
#define EMU_RUN 0x0200
|
| 1417 |
|
|
#ifdef _MISRA_RULES
|
| 1418 |
|
|
#define ERR_TYP(x) (((x) & 0x03u) << 14)
|
| 1419 |
|
|
#else
|
| 1420 |
|
|
#define ERR_TYP(x) (((x) & 0x03) << 14)
|
| 1421 |
|
|
#endif /* _MISRA_RULES */
|
| 1422 |
|
|
|
| 1423 |
|
|
#define TMODE_P0 0x00
|
| 1424 |
|
|
#define TMODE_P1 0x01
|
| 1425 |
|
|
#define PULSE_HI_P 0x02
|
| 1426 |
|
|
#define PERIOD_CNT_P 0x03
|
| 1427 |
|
|
#define IRQ_ENA_P 0x04
|
| 1428 |
|
|
#define TIN_SEL_P 0x05
|
| 1429 |
|
|
#define OUT_DIS_P 0x06
|
| 1430 |
|
|
#define CLK_SEL_P 0x07
|
| 1431 |
|
|
#define TOGGLE_HI_P 0x08
|
| 1432 |
|
|
#define EMU_RUN_P 0x09
|
| 1433 |
|
|
#define ERR_TYP_P0 0x0E
|
| 1434 |
|
|
#define ERR_TYP_P1 0x0F
|
| 1435 |
|
|
|
| 1436 |
|
|
|
| 1437 |
|
|
/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
|
| 1438 |
|
|
|
| 1439 |
|
|
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
|
| 1440 |
|
|
#define PF0 0x0001
|
| 1441 |
|
|
#define PF1 0x0002
|
| 1442 |
|
|
#define PF2 0x0004
|
| 1443 |
|
|
#define PF3 0x0008
|
| 1444 |
|
|
#define PF4 0x0010
|
| 1445 |
|
|
#define PF5 0x0020
|
| 1446 |
|
|
#define PF6 0x0040
|
| 1447 |
|
|
#define PF7 0x0080
|
| 1448 |
|
|
#define PF8 0x0100
|
| 1449 |
|
|
#define PF9 0x0200
|
| 1450 |
|
|
#define PF10 0x0400
|
| 1451 |
|
|
#define PF11 0x0800
|
| 1452 |
|
|
#define PF12 0x1000
|
| 1453 |
|
|
#define PF13 0x2000
|
| 1454 |
|
|
#define PF14 0x4000
|
| 1455 |
|
|
#define PF15 0x8000
|
| 1456 |
|
|
|
| 1457 |
|
|
|
| 1458 |
|
|
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
|
| 1459 |
|
|
#define PF0_P 0
|
| 1460 |
|
|
#define PF1_P 1
|
| 1461 |
|
|
#define PF2_P 2
|
| 1462 |
|
|
#define PF3_P 3
|
| 1463 |
|
|
#define PF4_P 4
|
| 1464 |
|
|
#define PF5_P 5
|
| 1465 |
|
|
#define PF6_P 6
|
| 1466 |
|
|
#define PF7_P 7
|
| 1467 |
|
|
#define PF8_P 8
|
| 1468 |
|
|
#define PF9_P 9
|
| 1469 |
|
|
#define PF10_P 10
|
| 1470 |
|
|
#define PF11_P 11
|
| 1471 |
|
|
#define PF12_P 12
|
| 1472 |
|
|
#define PF13_P 13
|
| 1473 |
|
|
#define PF14_P 14
|
| 1474 |
|
|
#define PF15_P 15
|
| 1475 |
|
|
|
| 1476 |
|
|
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
|
| 1477 |
|
|
|
| 1478 |
|
|
/*// SPI_CTL Masks */
|
| 1479 |
|
|
#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
|
| 1480 |
|
|
#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
|
| 1481 |
|
|
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
|
| 1482 |
|
|
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
|
| 1483 |
|
|
#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
|
| 1484 |
|
|
#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
|
| 1485 |
|
|
#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
|
| 1486 |
|
|
#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
|
| 1487 |
|
|
#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
|
| 1488 |
|
|
#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
|
| 1489 |
|
|
#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
|
| 1490 |
|
|
#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
|
| 1491 |
|
|
|
| 1492 |
|
|
/*// SPI_FLG Masks */
|
| 1493 |
|
|
#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1494 |
|
|
#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1495 |
|
|
#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1496 |
|
|
#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1497 |
|
|
#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1498 |
|
|
#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1499 |
|
|
#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1500 |
|
|
#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1501 |
|
|
#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1502 |
|
|
#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1503 |
|
|
#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1504 |
|
|
#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1505 |
|
|
#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1506 |
|
|
#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1507 |
|
|
|
| 1508 |
|
|
/*// SPI_FLG Bit Positions */
|
| 1509 |
|
|
#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1510 |
|
|
#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1511 |
|
|
#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1512 |
|
|
#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1513 |
|
|
#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1514 |
|
|
#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1515 |
|
|
#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1516 |
|
|
#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1517 |
|
|
#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1518 |
|
|
#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1519 |
|
|
#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1520 |
|
|
#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1521 |
|
|
#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1522 |
|
|
#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1523 |
|
|
|
| 1524 |
|
|
/*// SPI_STAT Masks */
|
| 1525 |
|
|
#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
|
| 1526 |
|
|
#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
|
| 1527 |
|
|
#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
|
| 1528 |
|
|
#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 1529 |
|
|
#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
|
| 1530 |
|
|
#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 1531 |
|
|
#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
|
| 1532 |
|
|
|
| 1533 |
|
|
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
|
| 1534 |
|
|
|
| 1535 |
|
|
/* AMGCTL Masks */
|
| 1536 |
|
|
#define AMCKEN 0x0001 /* Enable CLKOUT */
|
| 1537 |
|
|
#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
|
| 1538 |
|
|
#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
|
| 1539 |
|
|
#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
|
| 1540 |
|
|
#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
|
| 1541 |
|
|
#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
|
| 1542 |
|
|
#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
|
| 1543 |
|
|
#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
|
| 1544 |
|
|
#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
|
| 1545 |
|
|
|
| 1546 |
|
|
/* AMGCTL Bit Positions */
|
| 1547 |
|
|
#define AMCKEN_P 0x0000 /* Enable CLKOUT */
|
| 1548 |
|
|
#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
|
| 1549 |
|
|
#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
|
| 1550 |
|
|
#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
|
| 1551 |
|
|
#define B0_PEN_P 0x0004 /* Enable 16-bit packing Bank 0 */
|
| 1552 |
|
|
#define B1_PEN_P 0x0005 /* Enable 16-bit packing Bank 1 */
|
| 1553 |
|
|
#define B2_PEN_P 0x0006 /* Enable 16-bit packing Bank 2 */
|
| 1554 |
|
|
#define B3_PEN_P 0x0007 /* Enable 16-bit packing Bank 3 */
|
| 1555 |
|
|
#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
|
| 1556 |
|
|
|
| 1557 |
|
|
/* AMBCTL0 Masks */
|
| 1558 |
|
|
#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
|
| 1559 |
|
|
#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
|
| 1560 |
|
|
#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
|
| 1561 |
|
|
#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
|
| 1562 |
|
|
#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
|
| 1563 |
|
|
#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
|
| 1564 |
|
|
#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
|
| 1565 |
|
|
#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
|
| 1566 |
|
|
#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
|
| 1567 |
|
|
#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
|
| 1568 |
|
|
#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
|
| 1569 |
|
|
#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
|
| 1570 |
|
|
#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
|
| 1571 |
|
|
#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
|
| 1572 |
|
|
#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
|
| 1573 |
|
|
#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
|
| 1574 |
|
|
#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
|
| 1575 |
|
|
#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
|
| 1576 |
|
|
#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
|
| 1577 |
|
|
#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
|
| 1578 |
|
|
#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
|
| 1579 |
|
|
#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
|
| 1580 |
|
|
#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
|
| 1581 |
|
|
#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
|
| 1582 |
|
|
#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
|
| 1583 |
|
|
#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
|
| 1584 |
|
|
#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
|
| 1585 |
|
|
#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
|
| 1586 |
|
|
#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
|
| 1587 |
|
|
#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
|
| 1588 |
|
|
#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
|
| 1589 |
|
|
#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
|
| 1590 |
|
|
#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
|
| 1591 |
|
|
#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
|
| 1592 |
|
|
#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
|
| 1593 |
|
|
#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
|
| 1594 |
|
|
#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
|
| 1595 |
|
|
#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
|
| 1596 |
|
|
#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
|
| 1597 |
|
|
#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
|
| 1598 |
|
|
#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
|
| 1599 |
|
|
#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
|
| 1600 |
|
|
#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
|
| 1601 |
|
|
#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
|
| 1602 |
|
|
#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
|
| 1603 |
|
|
#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
|
| 1604 |
|
|
#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
|
| 1605 |
|
|
#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
|
| 1606 |
|
|
#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
|
| 1607 |
|
|
#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
|
| 1608 |
|
|
#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1609 |
|
|
#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1610 |
|
|
#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1611 |
|
|
#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1612 |
|
|
#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1613 |
|
|
#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1614 |
|
|
#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1615 |
|
|
#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1616 |
|
|
#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
|
| 1617 |
|
|
#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
|
| 1618 |
|
|
#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
|
| 1619 |
|
|
#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
|
| 1620 |
|
|
#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
|
| 1621 |
|
|
#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
|
| 1622 |
|
|
#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
|
| 1623 |
|
|
#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
|
| 1624 |
|
|
#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
|
| 1625 |
|
|
#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
|
| 1626 |
|
|
#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
|
| 1627 |
|
|
#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
|
| 1628 |
|
|
#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
|
| 1629 |
|
|
#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
|
| 1630 |
|
|
#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
|
| 1631 |
|
|
#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
|
| 1632 |
|
|
#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
|
| 1633 |
|
|
#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
|
| 1634 |
|
|
#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
|
| 1635 |
|
|
#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
|
| 1636 |
|
|
#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
|
| 1637 |
|
|
#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
|
| 1638 |
|
|
#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
|
| 1639 |
|
|
#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
|
| 1640 |
|
|
#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
|
| 1641 |
|
|
#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
|
| 1642 |
|
|
#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
|
| 1643 |
|
|
#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
|
| 1644 |
|
|
#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
|
| 1645 |
|
|
#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
|
| 1646 |
|
|
|
| 1647 |
|
|
/* AMBCTL1 Masks */
|
| 1648 |
|
|
#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
|
| 1649 |
|
|
#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
|
| 1650 |
|
|
#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
|
| 1651 |
|
|
#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
|
| 1652 |
|
|
#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
|
| 1653 |
|
|
#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
|
| 1654 |
|
|
#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1655 |
|
|
#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1656 |
|
|
#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1657 |
|
|
#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1658 |
|
|
#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1659 |
|
|
#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1660 |
|
|
#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1661 |
|
|
#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1662 |
|
|
#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
|
| 1663 |
|
|
#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
|
| 1664 |
|
|
#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
|
| 1665 |
|
|
#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
|
| 1666 |
|
|
#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
|
| 1667 |
|
|
#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
|
| 1668 |
|
|
#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
|
| 1669 |
|
|
#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
|
| 1670 |
|
|
#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
|
| 1671 |
|
|
#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
|
| 1672 |
|
|
#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
|
| 1673 |
|
|
#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
|
| 1674 |
|
|
#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
|
| 1675 |
|
|
#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
|
| 1676 |
|
|
#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
|
| 1677 |
|
|
#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
|
| 1678 |
|
|
#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
|
| 1679 |
|
|
#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
|
| 1680 |
|
|
#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
|
| 1681 |
|
|
#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
|
| 1682 |
|
|
#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
|
| 1683 |
|
|
#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
|
| 1684 |
|
|
#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
|
| 1685 |
|
|
#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
|
| 1686 |
|
|
#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
|
| 1687 |
|
|
#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
|
| 1688 |
|
|
#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
|
| 1689 |
|
|
#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
|
| 1690 |
|
|
#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
|
| 1691 |
|
|
#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
|
| 1692 |
|
|
#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
|
| 1693 |
|
|
#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
|
| 1694 |
|
|
#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
|
| 1695 |
|
|
#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
|
| 1696 |
|
|
#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
|
| 1697 |
|
|
#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
|
| 1698 |
|
|
#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1699 |
|
|
#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1700 |
|
|
#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1701 |
|
|
#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1702 |
|
|
#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1703 |
|
|
#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1704 |
|
|
#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1705 |
|
|
#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1706 |
|
|
#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
|
| 1707 |
|
|
#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
|
| 1708 |
|
|
#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
|
| 1709 |
|
|
#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
|
| 1710 |
|
|
#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
|
| 1711 |
|
|
#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
|
| 1712 |
|
|
#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
|
| 1713 |
|
|
#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
|
| 1714 |
|
|
#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
|
| 1715 |
|
|
#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
|
| 1716 |
|
|
#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
|
| 1717 |
|
|
#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
|
| 1718 |
|
|
#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
|
| 1719 |
|
|
#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
|
| 1720 |
|
|
#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
|
| 1721 |
|
|
#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
|
| 1722 |
|
|
#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
|
| 1723 |
|
|
#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
|
| 1724 |
|
|
#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
|
| 1725 |
|
|
#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
|
| 1726 |
|
|
#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
|
| 1727 |
|
|
#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
|
| 1728 |
|
|
#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
|
| 1729 |
|
|
#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
|
| 1730 |
|
|
#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
|
| 1731 |
|
|
#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
|
| 1732 |
|
|
#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
|
| 1733 |
|
|
#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
|
| 1734 |
|
|
#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
|
| 1735 |
|
|
#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
|
| 1736 |
|
|
|
| 1737 |
|
|
|
| 1738 |
|
|
/* ********************** SDRAM CONTROLLER MASKS *************************** */
|
| 1739 |
|
|
|
| 1740 |
|
|
/* EBIU_SDGCTL Masks */
|
| 1741 |
|
|
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
| 1742 |
|
|
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
| 1743 |
|
|
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
| 1744 |
|
|
#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
|
| 1745 |
|
|
#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
|
| 1746 |
|
|
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
|
| 1747 |
|
|
#define CL 0x0000000C /* SDRAM CAS latency */
|
| 1748 |
|
|
#define PFE 0x00000010 /* Enable SDRAM prefetch */
|
| 1749 |
|
|
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
|
| 1750 |
|
|
#define PASR 0x00000030 /* SDRAM partial array self-refresh */
|
| 1751 |
|
|
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
| 1752 |
|
|
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
| 1753 |
|
|
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
| 1754 |
|
|
#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
|
| 1755 |
|
|
#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
|
| 1756 |
|
|
#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
|
| 1757 |
|
|
#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
|
| 1758 |
|
|
#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
|
| 1759 |
|
|
#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
|
| 1760 |
|
|
#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
|
| 1761 |
|
|
#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
|
| 1762 |
|
|
#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
|
| 1763 |
|
|
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
|
| 1764 |
|
|
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
|
| 1765 |
|
|
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
|
| 1766 |
|
|
#define TRAS 0x000003C0 /* SDRAM tRAS in SCLK cycles */
|
| 1767 |
|
|
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
|
| 1768 |
|
|
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
|
| 1769 |
|
|
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
|
| 1770 |
|
|
#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
|
| 1771 |
|
|
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
|
| 1772 |
|
|
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
|
| 1773 |
|
|
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
|
| 1774 |
|
|
#define TRP 0x00003800 /* SDRAM tRP in SCLK cycles */
|
| 1775 |
|
|
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
|
| 1776 |
|
|
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
|
| 1777 |
|
|
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
|
| 1778 |
|
|
#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
|
| 1779 |
|
|
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
|
| 1780 |
|
|
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
|
| 1781 |
|
|
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
|
| 1782 |
|
|
#define TRCD 0x00030000 /* SDRAM tRCD in SCLK cycles */
|
| 1783 |
|
|
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
|
| 1784 |
|
|
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
|
| 1785 |
|
|
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
|
| 1786 |
|
|
#define TWR 0x00180000 /* SDRAM tWR in SCLK cycles */
|
| 1787 |
|
|
#define PUPSD 0x00200000 /*Power-up start delay */
|
| 1788 |
|
|
#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
|
| 1789 |
|
|
#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
|
| 1790 |
|
|
#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
|
| 1791 |
|
|
#define EBUFE 0x02000000 /* Enable external buffering timing */
|
| 1792 |
|
|
#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
|
| 1793 |
|
|
#define EMREN 0x10000000 /* Extended mode register enable */
|
| 1794 |
|
|
#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
|
| 1795 |
|
|
#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
|
| 1796 |
|
|
|
| 1797 |
|
|
/* EBIU_SDBCTL Masks */
|
| 1798 |
|
|
#define EBSZ 0x000E /* SDRAM external bank size */
|
| 1799 |
|
|
#define EBCAW 0x0030 /* SDRAM external bank column address width */
|
| 1800 |
|
|
#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
|
| 1801 |
|
|
#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 1802 |
|
|
#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
|
| 1803 |
|
|
#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
|
| 1804 |
|
|
#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
|
| 1805 |
|
|
#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 1806 |
|
|
#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
|
| 1807 |
|
|
#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
|
| 1808 |
|
|
#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
|
| 1809 |
|
|
|
| 1810 |
|
|
#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
|
| 1811 |
|
|
#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 1812 |
|
|
#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
|
| 1813 |
|
|
#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
|
| 1814 |
|
|
#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
|
| 1815 |
|
|
#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 1816 |
|
|
#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
|
| 1817 |
|
|
#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
|
| 1818 |
|
|
#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
|
| 1819 |
|
|
|
| 1820 |
|
|
#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
|
| 1821 |
|
|
#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 1822 |
|
|
#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
|
| 1823 |
|
|
#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
|
| 1824 |
|
|
#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
|
| 1825 |
|
|
#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 1826 |
|
|
#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
|
| 1827 |
|
|
#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
|
| 1828 |
|
|
#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
|
| 1829 |
|
|
|
| 1830 |
|
|
#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
|
| 1831 |
|
|
#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 1832 |
|
|
#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
|
| 1833 |
|
|
#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
|
| 1834 |
|
|
#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
|
| 1835 |
|
|
#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 1836 |
|
|
#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
|
| 1837 |
|
|
#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
|
| 1838 |
|
|
#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
|
| 1839 |
|
|
|
| 1840 |
|
|
/* EBIU_SDSTAT Masks */
|
| 1841 |
|
|
#define SDCI 0x00000001 /* SDRAM controller is idle */
|
| 1842 |
|
|
#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
|
| 1843 |
|
|
#define SDPUA 0x00000004 /* SDRAM power up active */
|
| 1844 |
|
|
#define SDRS 0x00000008 /* SDRAM is in reset state */
|
| 1845 |
|
|
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
|
| 1846 |
|
|
#define BGSTAT 0x00000020 /* Bus granted */
|
| 1847 |
|
|
|
| 1848 |
|
|
#ifdef _MISRA_RULES
|
| 1849 |
|
|
#pragma diag(pop)
|
| 1850 |
|
|
#endif /* _MISRA_RULES */
|
| 1851 |
|
|
|
| 1852 |
|
|
#endif /* _DEF_BF561_H */
|
