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jeremybenn |
*** Registers
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GR0 *always zero
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GR1 scratch
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GR2 normal return register
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GR27 Global Data Pointer (Must be set in crt0)
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GR30 SP stack pointer
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GR31 milicode return pointer
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| 9 |
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SR* Space registers
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CR24-31 Temporary Control Registers
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CR14 Vector Table Register (like VBR on an m68020)
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CR0 Put in a count, causes exception when decremented to 0.
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FORTH's magic number is 031240
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***
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Series 700/800
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The following options are also supported:
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-snnn set the initial system load (ISL) start address to
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nnn in the volume label. This is useful when
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building boot media for Series 700/800 systems.
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-lnnn specifies the length in bytes of the ISL code in
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the LIF volume.
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-ennn set the ISL entry point to nnn bytes from the
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beginning of the ISL. For example, specifying -
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e3272 means that the ISL entry point is 3272
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(decimal) bytes from the beginning of the ISL
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object module.
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-Knnn forces the directory start location to be the
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nearest multiple of nnn x 1024 bytes from the
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beginning of the volume. This is necessary for
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booting Series 700/800 systems from LIF media.
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-n xxx Sets the volume name to be xxx.
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lifinit -v64000000 -d64 -nISL10 -K2 -s4096 -l61440 -e5336 this_lif
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# lifcp --
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# -r Forces RAW mode copying. (file type BIN (-23951))
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# -T Sets the file type of the directory entry.
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# -Knnn forces each file copied in to begin on a nnn x
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# 1024-byte boundary from the beginning of the volume
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# Note: the word echoed below MUST be 10 characters exactly.
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#
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(echo "FORTH ") | lifcp -r -T-030001 -K2 - this_lif:AUTO
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| 51 |
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#
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# somxtract infile outfile --
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# converts a series 800 file *only* into a raw image
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It turns out the native cc and our current gcc produce series 700
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output, so in this case it runs till if fills up the hard disk.
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*** rombootlf5 is a FORTH interpreter in a "boot" image. (it won't run on
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the HP742 board)
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lifls -l rombootlf5
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volume ISL10 data size 249984 directory size 8 94/04/20 10:26:36
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filename type start size implement created
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===============================================================
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ISL -12800 16 240 0 94/04/20 10:26:36
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HPUX -12928 256 496 0 94/04/20 10:26:37
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IOMAP -12960 752 1504 0 94/04/20 10:26:37
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AUTO -12289 2256 1 0 94/04/20 10:26:38
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FORTH -12960 2264 208 0 94/04/20 10:26:38
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HPFORTH ASCII 2472 420 0 94/04/20 10:26:38
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BOOTROM ASCII 2896 3849 0 94/04/20 10:26:40
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PAD1 -12290 6752 1172 0 94/04/20 10:26:40
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*** The ISL is only needed when booting the raw hardware. As we're runing
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on a monitor (barely) all we need is a crt0 that initiallizes the GR27
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Global Data Pointer and zero's bss.
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*** Initial Program Load
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--------------------
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From page 11-56, architecture book.
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0x00000000 +------------------------------------+ 0
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| LIF_MAGIC | |
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0x00000004 +------------------------------------+ 4
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0x000000F0 +------------------------------------+ 240
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| IPL_ADDR |
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0x000000F4 +------------------------------------+ 244
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| IPL_SIZE |
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0x000000F8 +------------------------------------+ 248
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| IPL_ENTRY |
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0x000000FC +------------------------------------+ 252
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IPL_ADDR +------------------------------------+ IPL_ADDR
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| Position Independant |
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| IPL Code |
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| (including IPL_CHECKSUM) |
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+------------------------------------+ IPL_ADDR + IPL_SIZE
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+------------------------------------+
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IPL_ADDR 2 Kbyte aligned, nonzero
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IPL_SIZE Multiple of 2Kbytes, <= 256 Kbytes
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IPL_ENTRY Word aligned, less than IPL_SIZE
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Loads at IPL_START
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This is based on Cobra/Coral hardware:
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LED register at 0xf080024
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I/O status register at 0xf0800000
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EEPROM at 0xf0810000 (LAN ID begins at byte 0)
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Here's a dump of the LIF volume header using "xd" (od with hex output)
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*
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00000f0 0000 1000 0000 9800 0000 0000 0000 0000
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^^^^
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This is the size
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*
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0000800 5445 5354 2020 2020 2020 a271 0000 0010
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^^^^ ^^^^ ^^^^ ^^^^ ^^^^ ^^^^<-- this is the ipl offset
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this is the vol name ^^^^<- this is the type
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0000810 0000 0098 9407 1919 1426 8001 0000 0000
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^^^^
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This is the ipl size
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Interupts
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---------
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The vector table is access by %iva (%cr14). The address here must be a
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multiple of 2048. The indexes are:
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1 high-priority
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2 power failure
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3 recovery counter
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4 external interrupt
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5 low-priority machine check
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6 instruction TLB miss/instruction page fault
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7 instruction memory protection
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8 illegal instruction
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9 break instruction
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10 priviledged operation
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11 priviledged register
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12 overflow
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13 conditional
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14 assist exception
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15 data TLB miss fault/data page fault
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16 non access instruction TLB miss fault
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17 non access page TLB miss fault/non access data page fault
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18 data memory protection/unaligned data reference
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19 data memory break
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20 TLB dirty bit
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21 page reference
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22 assist emulation
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23 higher-priority transfer
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24 lower-priority transfe
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25 taken branch
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