OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [libgloss/] [m32c/] [genscript] - Blame information for rev 829

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
#!/bin/sh
2
 
3
# Copyright (c) 2005 Red Hat Incorporated.
4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions are met:
8
#
9
#     Redistributions of source code must retain the above copyright
10
#     notice, this list of conditions and the following disclaimer.
11
#
12
#     Redistributions in binary form must reproduce the above copyright
13
#     notice, this list of conditions and the following disclaimer in the
14
#     documentation and/or other materials provided with the distribution.
15
#
16
#     The name of Red Hat Incorporated may not be used to endorse
17
#     or promote products derived from this software without specific
18
#     prior written permission.
19
#
20
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23
# DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
24
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
27
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
 
31
srcdir="$1"
32
name="$2"
33
ramstart="$3"
34
ramsize="$4"
35
romstart="$5"
36
romsize="$6"
37
vecprefix="$7"
38
 
39
sedcmd="s/RAMSTART/$ramstart/g; s/RAMSIZE/$ramsize/g"
40
sedcmd="$sedcmd; s/ROMSTART/$romstart/g; s/ROMSIZE/$romsize/g"
41
 
42
# .rodata can be left with .text
43
rotext='/IF_ROCOPY/d'
44
# .rodata needs to be with .data
45
rodata='/IF_ROROM/d'
46
 
47
# All sections are put in one region
48
simram='s/LOWROM/RAM/g; s/= .*SIZEOF.*/= 0);/; s/AT>ROM//g'
49
oneram='s/> ROM/> RAM/g;'
50
# RW data needs to be copied to RAM
51
rwonly='s/LOWROM/ROM/g; s/ SIZEOF(.rodata) + //g'
52
# all data needs to be copied to RAM
53
rocopy='s/LOWROM/RAM AT>ROM/g'
54
 
55
case $name:$romstart in
56
  sim*:0 )
57
    # The r8c and m32c simulators have only a single memory region
58
    sedcmd="$sedcmd; $simram; $oneram; $rotext"
59
    ;;
60
  sim*:* )
61
    # This is most likely the m16c simulator
62
    sedcmd="$sedcmd; $simram; $rodata"
63
    ;;
64
  *:0x???? )
65
    # This is most likely the r8c chip
66
    sedcmd="$sedcmd; $rwonly; $rotext"
67
    ;;
68
  m32*:* )
69
    sedcmd="$sedcmd; $rwonly; $rotext"
70
    ;;
71
  *:* )
72
    sedcmd="$sedcmd; $rocopy; $rodata"
73
    ;;
74
esac
75
sedcmd="$sedcmd; /ORIGIN = 0,/d"
76
 
77
sedcmd="$sedcmd; s/VECSTART/${vecprefix}dc/; s/RESETSTART/${vecprefix}fc/"
78
 
79
sed "$sedcmd" < ${srcdir}/m32c.tmpl > ${name}.ld

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.