OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [libgloss/] [mips/] [jmr3904app-java.ld] - Blame information for rev 829

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* Linker script forJMR 3904 board using Java + qthreads */
2
 
3
ENTRY(_start)
4
STARTUP(crt0.o)
5
OUTPUT_ARCH("mips:3000")
6
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
7
GROUP(-lc -ljmr3904 -lgcc -lgcjcoop)
8
SEARCH_DIR(.)
9
__DYNAMIC  =  0;
10
 
11
PROVIDE (_mem_size = 0x100000); /* JMR3904 comes as standard with 512k of RAM */
12
 
13
/* Set the size of the stack for Java with qthreads.  */
14
PROVIDE (_Jv_QthreadsStackSize = 0x10000);
15
 
16
/* PROVIDE (__global = 0); */
17
 
18
/*
19
 * Initalize some symbols to be zero so we can reference them in the
20
 * crt0 without core dumping. These functions are all optional, but
21
 * we do this so we can have our crt0 always use them if they exist.
22
 * This is so BSPs work better when using the crt0 installed with gcc.
23
 * We have to initalize them twice, so we multiple object file
24
 * formats, as some prepend an underscore.
25
 */
26
PROVIDE (hardware_exit_hook = 0);
27
PROVIDE (hardware_hazard_hook = 0);
28
PROVIDE (hardware_init_hook = 0);
29
PROVIDE (software_init_hook = 0);
30
 
31
SECTIONS
32
{
33
  . = 0x80008000;
34
      /* This is NOT the address which fits with the monitor from jmr. */
35
      /* It fits the Cygmon ROMS */
36
  .text : {
37
     _ftext = . ;
38
    KEEP (*(.init))
39
     eprol  =  .;
40
    *(.text)
41
    *(.text.*)
42
    *(.gnu.linkonce.t.*)
43
    *(.mips16.fn.*)
44
    *(.mips16.call.*)
45
    PROVIDE (__runtime_reloc_start = .);
46
    *(.rel.sdata)
47
    PROVIDE (__runtime_reloc_stop = .);
48
    KEEP (*(.fini))
49
     etext  =  .;
50
     _etext  =  .;
51
  }
52
  . = .;
53
  .rodata : {
54
    *(.rdata)
55
    *(.rodata)
56
    *(.rodata.*)
57
    *(.gnu.linkonce.r.*)
58
  }
59
   _fdata = ALIGN(16);
60
  .data : {
61
    *(.data)
62
    *(.data.*)
63
    *(.gnu.linkonce.d.*)
64
    CONSTRUCTORS
65
  }
66
  . = ALIGN(8);
67
  _gp = . + 0x8000;
68
  __global = _gp;
69
  .lit8 : {
70
    *(.lit8)
71
  }
72
  .lit4 : {
73
    *(.lit4)
74
  }
75
  .sdata : {
76
    *(.sdata)
77
    *(.sdata.*)
78
    *(.gnu.linkonce.s.*)
79
  }
80
  . = ALIGN(4);
81
   edata  =  .;
82
   _edata  =  .;
83
   _fbss = .;
84
  .sbss : {
85
    *(.sbss)
86
    *(.sbss.*)
87
    *(.gnu.linkonce.sb.*)
88
    *(.scommon)
89
  }
90
  .bss : {
91
    _bss_start = . ;
92
    *(.bss)
93
    *(.bss.*)
94
    *(.gnu.linkonce.b.*)
95
    *(COMMON)
96
    . += 0x2000 ;  /* 8k bytes of stack. */
97
    __stack = ALIGN(64) ;
98
    . = __stack ;
99
  }
100
 
101
   end = .;
102
   _end = .;
103
 
104
  /* DWARF debug sections.
105
     Symbols in the DWARF debugging sections are relative to
106
     the beginning of the section so we begin them at 0.  */
107
 
108
  /* DWARF 1 */
109
  .debug          0 : { *(.debug) }
110
  .line           0 : { *(.line) }
111
 
112
  /* GNU DWARF 1 extensions */
113
  .debug_srcinfo  0 : { *(.debug_srcinfo) }
114
  .debug_sfnames  0 : { *(.debug_sfnames) }
115
 
116
  /* DWARF 1.1 and DWARF 2 */
117
  .debug_aranges  0 : { *(.debug_aranges) }
118
  .debug_pubnames 0 : { *(.debug_pubnames) }
119
 
120
  /* DWARF 2 */
121
  .debug_info     0 : { *(.debug_info) }
122
  .debug_abbrev   0 : { *(.debug_abbrev) }
123
  .debug_line     0 : { *(.debug_line) }
124
  .debug_frame    0 : { *(.debug_frame) }
125
  .debug_str      0 : { *(.debug_str) }
126
  .debug_loc      0 : { *(.debug_loc) }
127
  .debug_macinfo  0 : { *(.debug_macinfo) }
128
  .debug_ranges   0 : { *(.debug_ranges) }
129
 
130
  /* SGI/MIPS DWARF 2 extensions */
131
  .debug_weaknames 0 : { *(.debug_weaknames) }
132
  .debug_funcnames 0 : { *(.debug_funcnames) }
133
  .debug_typenames 0 : { *(.debug_typenames) }
134
  .debug_varnames  0 : { *(.debug_varnames) }
135
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.