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jeremybenn |
/*-----------------------------------------------------------------------------
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//
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// Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of Xilinx nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//---------------------------------------------------------------------------*/
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.file "xil-crt0.S"
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.section ".got2","aw"
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.align 2
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.LCTOC1 = . + 32768
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.Lsbss_start = .-.LCTOC1
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.long __sbss_start
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.Lsbss_end = .-.LCTOC1
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.long __sbss_end
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.Lbss_start = .-.LCTOC1
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.long __bss_start
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.Lbss_end = .-.LCTOC1
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.long __bss_end
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.Lstack = .-.LCTOC1
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.long __stack
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.Lsda = .-.LCTOC1
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.long _SDA_BASE_ /* address of the first small data area */
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.Lsda2 = .-.LCTOC1
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.long _SDA2_BASE_ /* address of the second small data area */
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.text
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.globl _start
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_start:
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bl __cpu_init /* Initialize the CPU first (BSP provides this) */
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lis 5,.LCTOC1@h
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ori 5,5,.LCTOC1@l
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lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
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lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
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#ifndef SIMULATOR
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/* clear sbss */
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lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */
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lwz 7,.Lsbss_end(5) /* calculate end of the SBSS */
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cmplw 1,6,7
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bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */
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li 0,0 /* zero to clear memory */
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subf 8,6,7 /* number of bytes to zero */
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srwi. 9,8,2 /* number of words to zero */
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beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */
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mtctr 9
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addi 6,6,-4 /* adjust so we can use stwu */
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.Lloopsbss:
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stwu 0,4(6) /* zero sbss */
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bdnz .Lloopsbss
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.Lstbyteloopsbss:
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andi. 9,8,3 /* Calculate how many trailing bytes we have */
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beq 0,.Lenclsbss
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mtctr 9
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addi 6,6,-1 /* adjust, so we can use stbu */
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.Lbyteloopsbss:
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stbu 0,1(6)
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bdnz .Lbyteloopsbss
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.Lenclsbss:
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.Lstclbss:
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/* clear bss */
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lwz 6,.Lbss_start(5) /* calculate beginning of the BSS */
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lwz 7,.Lbss_end(5) /* calculate end of the BSS */
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cmplw 1,6,7
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bc 4,4,.Lenclbss /* If no BSS, no clearing required */
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li 0,0 /* zero to clear memory */
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subf 8,6,7 /* number of bytes to zero */
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srwi. 9,8,2 /* number of words to zero */
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beq .Lstbyteloopbss /* Check if the number of bytes was less than 4 */
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mtctr 9
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addi 6,6,-4 /* adjust so we can use stwu */
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.Lloopbss:
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stwu 0,4(6) /* zero bss */
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bdnz .Lloopbss
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.Lstbyteloopbss:
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andi. 9,8,3 /* Calculate how many trailing bytes we have */
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beq 0,.Lenclbss /* If zero, we are done */
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mtctr 9
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addi 6,6,-1 /* adjust, so we can use stbu */
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.Lbyteloopbss:
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stbu 0,1(6)
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bdnz .Lbyteloopbss
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.Lenclbss:
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#endif /* SIMULATOR */
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/* set stack pointer */
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lwz 1,.Lstack(5) /* stack address */
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/* set up initial stack frame */
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addi 1,1,-8 /* location of back chain */
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lis 0,0
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stw 0,0(1) /* set end of back chain */
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/* initialize base timer to zero */
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mtspr 0x11c,0
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mtspr 0x11d,0
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#ifdef HAVE_XFPU
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/* On the Xilinx PPC405 and PPC440, the MSR
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must be explicitly set to mark the prescence
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of an FPU */
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mfpvr 0
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rlwinm 0,0,0,12,15
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cmpwi 7,0,8192
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mfmsr 0
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ori 0,0,8192
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beq- 7,fpu_init_done
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do_405:
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oris 0,0,512
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fpu_init_done:
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mtmsr 0
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#endif
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#ifdef PROFILING
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/* Setup profiling stuff */
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bl _profile_init
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#endif /* PROFILING */
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/* Call __init */
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bl __init
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/* Let her rip */
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bl main
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/* Invoke the language cleanup functions */
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bl __fini
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#ifdef PROFILING
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/* Cleanup profiling stuff */
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bl _profile_clean
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#endif /* PROFILING */
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/* Call __init */
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/* All done */
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bl exit
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/* Trap has been removed for both simulation and hardware */
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.globl _exit
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_exit:
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b _exit
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.Lstart:
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.size _start,.Lstart-_start
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