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[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [libgloss/] [sparc/] [salib-701.c] - Blame information for rev 829

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Line No. Rev Author Line
1 207 jeremybenn
/* Stand-alone library for Sparclet 701 board
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 *
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 * Copyright (c) 1996 Cygnus Support
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 *
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 * The authors hereby grant permission to use, copy, modify, distribute,
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 * and license this software and its documentation for any purpose, provided
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 * that existing copyright notices are retained in all copies and that this
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 * notice is included verbatim in any distributions. No written agreement,
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 * license, or royalty fee is required for any of the authorized uses.
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 * Modifications to this software may be copyrighted by their authors
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 * and need not follow the licensing terms described here, provided that
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 * the new terms are clearly indicated on the first page of each file where
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 * they apply.
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 */
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#define RAM_BASE                ((unsigned char *)0x12000000) /* Start of cacheable dram */
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#define DCACHE_LINES            128        /* Number of lines in data cache */
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#define DCACHE_LINE_SIZE        16         /* Bytes per data cache line */
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#define DCACHE_BANKS            4          /* 4-way associative */
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#define CACHE_INST_TAG_ADDR     ((unsigned char *)0xc0020000) /* I-Cache tag base address */
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#define ALL_BANKS               0x0000f000 /* Selects all 4 cache banks */
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#define ICACHE_LINES            128        /* Number of lines in inst cache */
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#define ICACHE_LINE_SIZE        32         /* Bytes per inst cache line */
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/* I/O Base addresses */
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#define CACHE_INST_BASE_ADD     0xc0000000
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#define CACHE_DATA_BASE_ADD     0xc8000000
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#define _InstrCacheCtlBase      0xc0000000
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#define _DataCacheCtlBase       0xc8000000
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#define USART_BASE_ADD          0x92000000
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#define USART_BASE_ADRS(n)      (USART_BASE_ADD + ((n)<<21))    /*0..3*/
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/* Serial receiver definitions */
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#define USART_RX_CHAR(n) (*(unsigned char *) (USART_BASE_ADRS(n)  +(2<<19)))
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#define USART_RX_CTRL_BASE_ADRS(n)       (USART_BASE_ADRS(n)+(3<<19))
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#define URSTR(n)        (*(unsigned int *) (USART_RX_CTRL_BASE_ADRS(n)+(2<<15)))
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#define URSTR_CHAR_NUM                  0x1f00  /* Bits 8-12 */
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/* Serial receiver definitions */
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#define USART_TX_CHAR(n)        (*(unsigned char *) (USART_BASE_ADRS(n)+3))
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#define USART_TX_CTRL_BASE_ADRS(n)       (USART_BASE_ADRS(n)+(1<<19))
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#define UTSTR(n)        (*(unsigned int *) (USART_TX_CTRL_BASE_ADRS(n)+(2<<15)))
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#define UTSTR_CHAR_FREE                 0x1f0   /* Bits 4-8 */
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/* Cache definitions */
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#define DCCA_NB_LINES       128         /* Nb of lines of the cache */
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/* Bank number, used for Cache Memory and Cache Tag */
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#define ICCA_B3         0x000008000     /* Bit 15 - 1:Bank3 selected       */
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#define ICCA_B2         0x000004000     /* Bit 14 - 1:Bank2 selected       */
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#define ICCA_B1         0x000002000     /* Bit 13 - 1:Bank1 selected       */
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#define ICCA_B0         0x000001000     /* Bit 12 - 1:Bank0 selected       */
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/* Register address, show which register is to be checked/updated */
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#define ICCACR          0x00000000      /* Bits 17 - 16 - Control register */
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#define ICCAMEM         0x00010000      /* Bits 17 - 16 - Cache memory     */
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#define DCCACR          0x00000000      /* Bits 16 - 15 - Control register */
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/* Instruction Cache Controller Register */
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#define ICCR_DISABLE  0xfffffffe        /* Reset enable bit                 */
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/* Serial I/O routines */
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#define STUB_PORT 1             /* 0 = serial port A;  1 = serial port B */
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static volatile unsigned char *rx_fifo = &USART_RX_CHAR(STUB_PORT);
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static volatile unsigned int *rx_status = &URSTR(STUB_PORT);
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static volatile unsigned char *tx_fifo = &USART_TX_CHAR(STUB_PORT);
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static volatile unsigned int *tx_status = &UTSTR(STUB_PORT);
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/* library-free debug reoutines */
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#ifdef XDEBUG
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#define XDBG_MSG(x) pmsg(x)
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#define XDBG_HEX(x) phex(x)
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#else
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#define XDBG_MSG(x) 
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#define XDBG_HEX(x) 
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#endif
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static int
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rx_rdy()
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{
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  return (*rx_status & URSTR_CHAR_NUM);
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}
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static unsigned char
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rx_char()
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{
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  return *rx_fifo;
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}
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void
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tx_char(char c)
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{
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  *tx_fifo = c;
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}
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static int
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tx_rdy()
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{
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  return (*tx_status & UTSTR_CHAR_FREE);
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}
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int
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getDebugChar()
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{
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  while (!rx_rdy())
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    ;
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  return rx_char();
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}
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void
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putDebugChar(int c)
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{
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  while (!tx_rdy())
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    ;
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  tx_char(c);
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}
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#ifdef XDEBUG
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/* library-free debug reoutines */
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/* print a string */
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void pmsg(char *p)
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{
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    while (*p)
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    {
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        if (*p == '\n')
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            putDebugChar('\r');
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        putDebugChar(*p++);
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    }
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}
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/* print a hex number */
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void phex(long x)
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{
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    char buf[9];
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    int i;
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    buf[8] = '\0';
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    for (i = 7; i >= 0; i--)
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    {
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        char c = x & 0x0f;
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        buf[i] = c < 10 ? c + '0' : c - 10 + 'A';
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        x >>= 4;
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    }
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    pmsg(buf);
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}
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#endif
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/* rdtbr() - read the trap base register */
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unsigned long rdtbr();
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asm("
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        .text
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        .align 4
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        .globl _rdtbr
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_rdtbr:
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        retl
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        mov     %tbr, %o0
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");
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/* wrtbr() - write the trap base register */
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void wrtbr(unsigned long);
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166
asm("
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        .text
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        .align 4
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        .globl _wrtbr
170
_wrtbr:
171
        retl
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        mov     %o0, %tbr
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");
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/* Each entry in the trap vector occupies four words. */
176
 
177
struct trap_entry
178
{
179
  unsigned sethi_filler:10;
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  unsigned sethi_imm22:22;
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  unsigned jmpl_filler:19;
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  unsigned jmpl_simm13:13;
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  unsigned long filler[2];
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};
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extern struct trap_entry fltr_proto;
187
asm ("
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        .data
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        .globl _fltr_proto
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        .align 4
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_fltr_proto:                    ! First level trap routine prototype
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        sethi 0, %l0
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        jmpl 0+%l0, %g0
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        nop
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        nop
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        .text
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        .align 4
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");
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/* copy_vectors - Copy the trap vectors from ROM to RAM, set the TBR register
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   to point to the RAM vectors, and return the address of the RAM vectors.  */
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extern struct trap_entry __trap_vectors[256];   /* defined in matra.ld */
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struct trap_entry *copy_vectors()
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{
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  int i;
209
  struct trap_entry *old = (struct trap_entry *) (rdtbr() & ~0xfff);
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211
  XDBG_MSG("Copying vectors...\n");
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  for (i = 0; i < 256; i++)
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    __trap_vectors[i] = old[i];
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  wrtbr ((unsigned long)__trap_vectors);
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  XDBG_MSG("Done\n");
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  return __trap_vectors;
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}
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void
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disable_cache()
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{
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  unsigned long *ptr;
224
  static unsigned long CACHE_shadow_iccr = 0;   /* Because CR cannot be read */
225
  static unsigned long CACHE_shadow_dccr = 0;   /* Because CR cannot be read */
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  XDBG_MSG("Disabling cache...\n");
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  ptr = (unsigned long*)(CACHE_INST_BASE_ADD | ICCACR);
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  CACHE_shadow_iccr = CACHE_shadow_iccr & ICCR_DISABLE;
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  *ptr = CACHE_shadow_iccr;
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  ptr = (unsigned long*)(CACHE_DATA_BASE_ADD | DCCACR);
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  CACHE_shadow_dccr = CACHE_shadow_dccr & ICCR_DISABLE;
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  *ptr = CACHE_shadow_dccr;
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  XDBG_MSG("Done\n");
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}
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/* Flush the instruction cache.  We need to do this for the debugger stub so
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   that breakpoints, et. al. become visible to the instruction stream after
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   storing them in memory.  FIXME!!
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 */
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243
void
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flush_i_cache ()
245
{
246
  volatile unsigned char *addr;
247
 
248
  /* First, force all dirty items in the data cache to be moved out to real
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     memory.  This is done by making read refs to alternate addresses that will
250
     fill up all four banks for each line.  Note that we actually have to
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     reference 8 locs per line just in case the region of memory we use is one
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     of the areas that needs to be flushed.  */
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254
  for (addr = RAM_BASE;
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       addr < RAM_BASE + (DCACHE_LINES * DCACHE_LINE_SIZE * DCACHE_BANKS) * 2;
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       addr += DCACHE_LINE_SIZE)
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    *addr;                      /* Read the loc */
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259
  /* Now, flush the instruction cache.  */
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261
  for (addr = CACHE_INST_TAG_ADDR + ALL_BANKS;
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       addr <= CACHE_INST_TAG_ADDR + ALL_BANKS + ICACHE_LINES * ICACHE_LINE_SIZE;
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       addr += ICACHE_LINE_SIZE)
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    *(unsigned long *)addr = 0; /* Clr tag entry for all banks on this line */
265
}
266
 
267
/* Setup trap TT to go to ROUTINE. */
268
 
269
void
270
exceptionHandler (int tt, unsigned long routine)
271
{
272
  static struct trap_entry *tb;         /* Trap vector base address */
273
 
274
  if (!tb)
275
    {
276
      tb = copy_vectors();              /* Copy trap vectors to RAM */
277
      disable_cache();                  /* Disable cache  FIXME!! */
278
    }
279
 
280
  XDBG_MSG("Setting exception handler for trap...\n");
281
 
282
  tb[tt] = fltr_proto;
283
 
284
  tb[tt].sethi_imm22 = routine >> 10;
285
  tb[tt].jmpl_simm13 = routine & 0x3ff;
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287
  XDBG_MSG("Done\n");
288
}

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