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jeremybenn |
/*
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* Copyright (c) 1995, 1996 Cygnus Support
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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#define STACK_SIZE 16 * 1024
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#define TRAP_STACK_SIZE 4 * 1024
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#define NUM_REGS 20
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#ifdef SL933
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#define NUMBER_OF_REGISTER_WINDOWS 6
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#else
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#define NUMBER_OF_REGISTER_WINDOWS 8
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#endif
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#if (NUMBER_OF_REGISTER_WINDOWS == 8)
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#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
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#elif (NUMBER_OF_REGISTER_WINDOWS == 16)
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#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */
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#elif (NUMBER_OF_REGISTER_WINDOWS == 32)
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#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */
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#else
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#error "Unsupported number of register windows for this cpu"
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#endif
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/* The traptable has to be the first code in a boot PROM. */
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/*
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* Entry for traps which jump to a programmer-specified trap handler.
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*/
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#define TRAP(_handler) \
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sethi %hi(_handler), %l3 ; \
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jmpl %l3+%lo(_handler), %g0 ; \
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mov %wim, %l0 ; \
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nop
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/* Unexcpected trap will halt the processor by forcing it to error state */
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#if 1
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#define BAD_TRAP ta 0; nop; nop; nop;
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#else
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#define BAD_TRAP \
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mov %psr, l0 ; \
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mov 0x0, %o0 ; \
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sethi %hi(SYM(bad_trap)), l4 ; \
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jmp l4+%lo(SYM(bad_trap));
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#endif
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/* Software trap. Treat as BAD_TRAP for the time being... */
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#if 1
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#define SOFT_TRAP BAD_TRAP
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#else
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#define SOFT_TRAP \
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mov $psr, $l0 ; \
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mov 0x0, $o0 ; \
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sethi $hi(SYM(soft_trap)), l4 ; \
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jmp l4+$lo(SYM(soft_trap));
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#endif
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#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */
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#define TBR_INIT 0
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#define WIM_INIT 2
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#define SP_INIT 0x023ffff0
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/* Macros for reading and writing to arbitrary address spaces. Note that ASI
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must be a constant (sorry, but the SPARC can only specify ASIs as part of an
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instruction. */
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#define read_asi(ASI, LOC) \
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({ \
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unsigned int val; \
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__asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \
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val; \
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})
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#define write_asi(ASI, LOC, VAL) \
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__asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI));
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/*
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* Use this when modifying registers that cause memory to be modified. This
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* will cause GCC to reload all values after this point.
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*/
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#define write_asi_volatile(ASI, LOC, VAL) \
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__asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \
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: "memory");
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#define WRITE_PC(x) registers[PC] = x; registers[NPC] = x + 4;
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/*
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* Processor Status Register (psr)
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*
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* 31 28|27 24|23 20|19 12|11 9|7|6|5|4 0
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* +------+-------+-------+-------+------+-+-+-+--------+
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* | impl | ver | icc | res. | pil | | | | cwp |
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* +------+-------+-------+-------+------+-+-+-+--------+
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* S P E
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* S T
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* if ET = 1, traps are enabled, 0 means disabled.
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* if S = 1, you're in supervisor mode, 0 means user mode.
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* cwp points to the current window.
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*
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* Trap Base Register (tbr)
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*
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* 31 12|11 4|3 0
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* +--------------+--------------+------+
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* | tba | tt | null |
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* +--------------+--------------+------+
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*
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* tba contains the most sig. 20 bits of the tbr base address
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* tt is the trap number.
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*
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* Window Invalid Register (wim)
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* 31 8| 7| 6| 5| 4| 3| 2| 1| 0
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* +-------------+--+--+--+--+--+--+--+--+
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* | res. |w7|w6|w5|w4|w3|w2|w1|w0|
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* +-------------+--+--+--+--+--+--+--+--+
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*/
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