OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [libgloss/] [xc16x/] [trap_handle.c] - Blame information for rev 829

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/*
2
 * Copyright (C) 2006 KPIT Cummins
3
 * Copyright (C) 2009 Conny Marco Menebröcker
4
 * All rights reserved.
5
 *
6
 * Redistribution and use in source and binary forms is permitted
7
 * provided that the above copyright notice and following paragraph are
8
 * duplicated in all such forms.
9
 *
10
 * This file is distributed WITHOUT ANY WARRANTY; without even the implied
11
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12
 */
13
int trap0(int file, unsigned long ptr,int len)
14
{
15
asm volatile("TRAP #3");
16
return len;
17
}
18
 
19
 
20
int trap1(int file, unsigned long ptr,int len)
21
{
22
 asm volatile("TRAP #4");
23
 
24
}
25
 
26
int trap_lseek(int file, unsigned long ptr,int len)
27
{
28
 asm volatile("TRAP #8");
29
 
30
}
31
 
32
 
33
 
34
volatile int opensys(char *name,int flags,int perms)
35
{
36
 #ifndef __xc16xL__
37
        asm volatile("push r11\n"
38
                     "mov r11,r10 \n"
39
                     " mov r10,r9  \n"
40
                     " mov r9,#0x300 \n"
41
                     );
42
 
43
  #endif
44
 
45
asm volatile("trap #5");
46
#ifndef __xc16xL__
47
asm volatile("pop r11");
48
#endif
49
}
50
 
51
volatile int creatsys(char *name,int perms)
52
{
53
 #ifndef __xc16xL__
54
        asm volatile("push r10\n"
55
                     " mov r10,r9  \n"
56
                     " mov r9,#0x300 \n"
57
                     );
58
 
59
  #endif
60
 
61
asm volatile("trap #7");
62
#ifndef __xc16xL__
63
asm volatile("pop r10");
64
#endif
65
}
66
 
67
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.