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[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [crx/] [sys/] [asm.h] - Blame information for rev 859

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1 207 jeremybenn 
/* asm.h -- CRX architecture intrinsic functions
2 
 *
3 
 * Copyright (c) 2004 National Semiconductor Corporation
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 *
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 * The authors hereby grant permission to use, copy, modify, distribute,
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 * and license this software and its documentation for any purpose, provided
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 * that existing copyright notices are retained in all copies and that this
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 * notice is included verbatim in any distributions. No written agreement,
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 * license, or royalty fee is required for any of the authorized uses.
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 * Modifications to this software may be copyrighted by their authors
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 * and need not follow the licensing terms described here, provided that
12 
 * the new terms are clearly indicated on the first page of each file where
13 
 * they apply.
14 
 */
15 
 
16 
#ifndef _ASM
17 
#define _ASM
18 
 
19 
/* Note that immediate input values are not checked for validity. It is
20 
   the user's responsibility to use the intrinsic functions with appropriate
21 
   immediate values. */
22 
 
23 
/* Absolute Instructions */
24 
#define _absb_(src, dest)       __asm__("absb %1, %0" : "=r" (dest) : \
25 
                                   "r" ((char)src) , "0" (dest))
26 
#define _absw_(src, dest)       __asm__("absw %1,%0" : "=r" (dest) : \
27 
                                    "r" ((short)src) , "0" (dest))
28 
#define _absd_(src, dest)       __asm__("absd %1, %0" : "=r" (dest)  : \
29 
                                    "r" ((int)src) , "0" (dest))
30 
 
31 
/* Addition Instructions */
32 
#define _addb_(src, dest)       __asm__("addb %1, %0" : "=r" (dest) : \
33 
                                        "ri" ((unsigned char)src), "0" (dest) : "cc")
34 
#define _addub_(src, dest)      __asm__("addub  %1, %0" : "=r" (dest) : \
35 
                                        "ri" ((unsigned char)src), "0" (dest) : "cc")
36 
#define _addw_(src, dest)       __asm__("addw %1, %0" : "=r" (dest) : \
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                                        "ri" ((unsigned short)src), "0" (dest) : "cc")
38 
#define _adduw_(src, dest)      __asm__("adduw  %1, %0" : "=r" (dest) : \
39 
                                        "ri" ((unsigned short)src), "0" (dest) : "cc")
40 
#define _addd_(src, dest)       __asm__("addd %1, %0" : "=r" (dest) : \
41 
                                        "ri" ((unsigned int)src), "0" (dest) : "cc")
42 
#define _addud_(src, dest)      __asm__("addud  %1, %0" : "=r" (dest) : \
43 
                                        "ri" ((unsigned int)src), "0" (dest) : "cc")
44 
/* Add with Carry */
45 
#define _addcb_(src, dest)      __asm__("addcb  %1, %0" : "=r" (dest) : \
46 
                                        "ri" ((unsigned char)src), "0" (dest) : "cc")
47 
#define _addcw_(src, dest)      __asm__("addcw  %1, %0" : "=r" (dest) : \
48 
                                        "ri" ((unsigned short)src), "0" (dest) : "cc")
49 
#define _addcd_(src, dest)      __asm__("addcd  %1, %0" : "=r" (dest) : \
50 
                                        "ri" ((unsigned int)src), "0" (dest) : "cc")
51 
/* Q-format Add */
52 
#define _addqb_(src, dest)      __asm__("addqb %1, %0" : "=r" (dest) : \
53 
                                        "r" ((unsigned char)src), "0" (dest) : "cc")
54 
#define _addqw_(src, dest)      __asm__("addqw %1, %0" : "=r" (dest) : \
55 
                                        "r" ((unsigned short)src), "0" (dest) : "cc")
56 
#define _addqd_(src, dest)      __asm__("addqd %1, %0" : "=r" (dest) : \
57 
                                        "r" ((unsigned int)src), "0" (dest) : "cc")
58 
 
59 
/* Bitwise Logical AND */
60 
 
61 
#define _andb_(src, dest)  __asm__("andb %1,%0" : "=r" (dest) : \
62 
                                   "ri" ((unsigned char)src) , "0" (dest))
63 
#define _andw_(src, dest)  __asm__("andw %1,%0" : "=r" (dest) : \
64 
                                   "ri" ((unsigned short)src) , "0" (dest))
65 
#define _andd_(src, dest)  __asm__("andd %1,%0" : "=r" (dest) : \
66 
                                  "ri" ((unsigned int)src) , "0" (dest))
67 
 
68 
/* bswap Instruction */
69 
#define _bswap_(src, dest)      __asm__("bswap %1,%0" : "=r" (dest) : \
70 
                                        "r" ((unsigned int)src) , "0" (dest))
71 
/* cbit (clear bit) Instructions */
72 
#define _cbitb_(pos, dest)      __asm__("cbitb %1,%0" : "=mr" (dest) : \
73 
                                        "i" ((unsigned char)pos) , "0" (dest) : "cc")
74 
#define _cbitw_(pos, dest)      __asm__("cbitw %1,%0" : "=mr" (dest) : \
75 
                                        "i" ((unsigned char)pos) , "0" (dest) : "cc")
76 
#define _cbitd_(pos, dest)      __asm__("cbitd %1,%0" : "=r" (dest) : \
77 
                                        "i" ((unsigned char)pos) , "0" (dest) : "cc")
78 
 
79 
/* Compare Instructions */
80 
#define _cmpb_(src1, src2)  __asm__("cmpb %0,%1" : /* no output */  : \
81 
                                    "ri" ((unsigned char)src1) , "r" (src2) : "cc")
82 
#define _cmpw_(src1,src2)  __asm__("cmpw %0,%1" : /* no output */  \
83 
                                   : "ri" ((unsigned short)src1) , "r" (src2) : "cc")
84 
#define _cmpd_(src1,src2)  __asm__("cmpd %0,%1" : /* no output */  \
85 
                                   : "ri" ((unsigned int)src1) , "r" (src2) : "cc")
86 
 
87 
/* cntl Count Leading Ones Instructions */
88 
#define _cntl1b_(src, dest)     __asm__("cntl1b %1,%0" : "=r" (dest) : \
89 
                                        "r" ((char)src) , "0" (dest))
90 
#define _cntl1w_(src, dest)     __asm__("cntl1w %1,%0" : "=r" (dest) : \
91 
                                        "r" ((short)src) , "0" (dest))
92 
#define _cntl1d_(src, dest)     __asm__("cntl1d %1,%0" : "=r" (dest)  : \
93 
                                        "r" ((int)src) , "0" (dest))
94 
 
95 
/* cntl Count Leading Zeros Instructions */
96 
#define _cntl0b_(src, dest)     __asm__("cntl0b %1,%0" : "=r" (dest) : \
97 
                                        "r" ((char)src) , "0" (dest))
98 
#define _cntl0w_(src, dest)     __asm__("cntl0w %1,%0" : "=r" (dest) : \
99 
                                        "r" ((short)src) , "0" (dest))
100 
#define _cntl0d_(src, dest)     __asm__("cntl0d %1,%0" : "=r" (dest)  : \
101 
                                         "r" ((int)src) , "0" (dest))
102 
 
103 
/* cntl Count Leading Signs Instructions */
104 
#define _cntlsb_(src, dest)     __asm__("cntlsb %1,%0" : "=r" (dest) : \
105 
                                        "r" ((char)src) , "0" (dest))
106 
#define _cntlsw_(src, dest)     __asm__("cntlsw %1,%0" : "=r" (dest) : \
107 
                                        "r" ((short)src) , "0" (dest))
108 
#define _cntlsd_(src, dest)     __asm__("cntlsd %1,%0" : "=r" (dest)  : \
109 
                                         "r" ((int)src) , "0" (dest))
110 
 
111 
/* Disable Inerrupts instructions */
112 
#define _di_()       __asm__ volatile ("di\n" :  :  : "cc")
113 
#define _disable_()  __asm__ volatile ("di\n" :  :  : "cc")
114 
 
115 
/* Enable Inerrupts instructions */
116 
#define _ei_()                  __asm__ volatile ("ei\n" :  :  : "cc")
117 
#define _enable_()              __asm__ volatile ("ei\n" :  :  : "cc")
118 
 
119 
/* Enable Inerrupts instructions and Wait */
120 
#define _eiwait_()              __asm__ volatile ("eiwait" :  :  : "cc")
121 
 
122 
/* excp Instructions */
123 
#define _excp_(vector)          __asm__ volatile ("excp " # vector)
124 
 
125 
/* getpid Instruction */
126 
#define _getrfid_(dest)         __asm__("getrfid %0" : "=r" (dest)  : \
127 
                                        /* No input */ : "cc")
128 
 
129 
/* Load Instructions */
130 
#define _loadb_(base,dest)      __asm__("loadb %1,%0" : "=r" (dest) : \
131 
                                        "m" (base) , "0" (dest))
132 
#define _loadw_(base,dest)      __asm__("loadw %1,%0" : "=r" (dest) : \
133 
                                        "m" (base) , "0" (dest))
134 
#define _loadd_(base,dest)      __asm__("loadd %1,%0" : "=r" (dest) : \
135 
                                        "m" (base) , "0" (dest))
136 
 
137 
/* Load Multiple Instructions */
138 
#define _loadm_(src, mask)      __asm__("loadm %0,%1" : /* No output */ : \
139 
                                        "r" ((unsigned int)src) , "i" (mask))
140 
#define _loadmp_(src, mask)     __asm__("loadmp %0,%1" : /* No output */ : \
141 
                                        "r" ((unsigned int)src) , "i" (mask))
142 
 
143 
/* Multiply Accumulate Instrutions */
144 
#define _macsb_(hi, lo, src1, src2)     __asm__("macsb %1,%0" \
145 
                                        : =l (lo), =h (hi) \
146 
                                        : "r" ((char)src1) , "r" (src2))
147 
#define _macsw_(hi, lo, src1, src2)     __asm__("macsw %1,%0" \
148 
                                        : =l (lo), =h (hi) \
149 
                                        : "r" ((short)src1) , "r" (src2))
150 
#define _macsd_(hi, lo, src1, src2)     __asm__("macsd %1,%0" \
151 
                                        : =l (lo), =h (hi) \
152 
                                        : "r" ((int)src1) , "r" (src2))
153 
#define _macub_(hi, lo, src1, src2)     __asm__("macub %1,%0" \
154 
                                        : =l (lo), =h (hi) \
155 
                                        :"r" ((unsigned char)src1) , "r" (src2))
156 
#define _macuw_(hi, lo, src1, src2)     __asm__("macuw %1,%0" \
157 
                                        : =l (lo), =h (hi) \
158 
                                        : "r" ((unsigned short)src1) , "r" (src2))
159 
#define _macud_(hi, lo, src1, src2)     __asm__("macud %1,%0" \
160 
                                        : =l (lo), =h (hi) \
161 
                                        : "r" ((unsigned int)src1) , "r" (src2))
162 
 
163 
/* Q-Format Multiply Accumulate Instrutions */
164 
#define _macqb_(src1, src2)     __asm__("macqb %1,%0" \
165 
                                        : =l (lo), =h (hi) \
166 
                                        :"r" ((char)src1) , "r" (src2))
167 
#define _macqw_(src1, src2)     __asm__("macqw %1,%0" \
168 
                                        : =l (lo), =h (hi) \
169 
                                        :"r" ((short)src1) , "r" (src2))
170 
#define _macqd_(src1, src2)     __asm__("macqd %1,%0" \
171 
                                        : =l (lo), =h (hi) \
172 
                                        :"r" ((int)src1) , "r" (src2))
173 
 
174 
/* Maximum Instructions */
175 
#define _maxsb_(src, dest)      __asm__("maxsb %1,%0" : "=r" (dest) : \
176 
                                        "r" ((char)src) , "0" (dest))
177 
#define _maxsw_(src, dest)      __asm__("maxsw %1,%0" : "=r" (dest) : \
178 
                                        "r" ((short)src) , "0" (dest))
179 
#define _maxsd_(src, dest)      __asm__("maxsd %1,%0" : "=r" (dest)  : \
180 
                                        "r" ((int)src) , "0" (dest))
181 
#define _maxub_(src, dest)      __asm__("maxub %1,%0" : "=r" (dest) : \
182 
                                        "r" ((unsigned char)src) , "0" (dest))
183 
#define _maxuw_(src, dest)      __asm__("maxuw %1,%0" : "=r" (dest) : \
184 
                                        "r" ((unsigned short)src) , "0" (dest))
185 
#define _maxud_(src, dest)      __asm__("maxud %1,%0" : "=r" (dest)  : \
186 
                                        "r" ((unsigned int)src) , "0" (dest))
187 
 
188 
/* Minimum Instructions */
189 
#define _minsb_(src, dest)      __asm__("minsb %1,%0" : "=r" (dest) : \
190 
                                        "r" ((char)src) , "0" (dest))
191 
#define _minsw_(src, dest)      __asm__("minsw %1,%0" : "=r" (dest) : \
192 
                                        "r" ((short)src) , "0" (dest))
193 
#define _minsd_(src, dest)      __asm__("minsd %1,%0" : "=r" (dest)  : \
194 
                                        "r" ((int)src) , "0" (dest))
195 
#define _minub_(src, dest)      __asm__("minub %1,%0" : "=r" (dest) : \
196 
                                        "r" ((unsigned char)src) , "0" (dest))
197 
#define _minuw_(src, dest)      __asm__("minuw %1,%0" : "=r" (dest) : \
198 
                                        "r" ((unsigned short)src) , "0" (dest))
199 
#define _minud_(src, dest)      __asm__("minud %1,%0" : "=r" (dest)  : \
200 
                                        "r" ((unsigned int)src) , "0" (dest))
201 
 
202 
/* Move Instructions */
203 
#define _movb_(src, dest)       __asm__("movb %1,%0" : "=r" (dest) : \
204 
                                        "ri" ((unsigned char)src) , "0" (dest))
205 
#define _movw_(src, dest)       __asm__("movw %1,%0" : "=r" (dest) : \
206 
                                        "ri" ((unsigned short)src) , "0" (dest))
207 
#define _movd_(src, dest)       __asm__("movd %1,%0" : "=r" (dest)  : \
208 
                                        "ri" ((unsigned int)src) , "0" (dest))
209 
 
210 
/* mtpr and mfpr Insturctions */
211 
#define _mtpr_(procregd, src)  __asm__("mtpr\t%0," procregd : /* no output */ : \
212 
                                       "r" (src) : "cc")
213 
#define _mfpr_(procregd, dest) __asm__("mfpr\t" procregd ",%0" : "=r" (dest) : \
214 
                                       /* no input */ "0" (dest) : "cc")
215 
 
216 
/* Multiplication Instructions */
217 
#define _mulsbw_(src, dest)     __asm__("mulsbw %1,%0" : "=r" (dest) : \
218 
                                        "r" ((char)src) , "0" (dest))
219 
#define _mulubw_(src, dest)     __asm__("mulubw %1,%0" : "=r" (dest) : \
220 
                                        "r" ((unsigned char)src) , "0" (dest))
221 
#define _mulswd_(src, dest)     __asm__("mulswd %1,%0" : "=r" (dest) : \
222 
                                        "r" ((short)src) , "0" (dest))
223 
#define _muluwd_(src, dest)     __asm__("muluwd %1,%0" : "=r" (dest) : \
224 
                                        "r" ((unsigned short)src) , "0" (dest))
225 
#define _mulb_(src, dest)       __asm__("mulb %1,%0" : "=r" (dest) : \
226 
                                        "ri" ((char)src) , "0" (dest))
227 
#define _mulw_(src, dest)       __asm__("mulw %1,%0" : "=r" (dest) : \
228 
                                        "ri" ((short)src) , "0" (dest))
229 
#define _muld_(src, dest)       __asm__("muld %1,%0" : "=r" (dest)  : \
230 
                                        "ri" ((int)src) , "0" (dest))
231 
#define _mullsd_(hi, lo, src1, src2)    __asm__("mullsd %2,%3" \
232 
                                        : =l (lo), =h (hi) \
233 
                                        : "r" ((unsigned int)src1) , "r" ((unsigned int)src2))
234 
#define _mullud_(hi, lo, src1, src2)    __asm__("mullud %2,%3" \
235 
                                        : =l (lo), =h (hi) \
236 
                                        : "r" ((int)src1) , "r" ((int)src2))
237 
 
238 
/* Q-Format Multiplication Instructions */
239 
#define _mulqb_(src, dest)      __asm__("mulqb %1,%0" : "=r" (dest) : \
240 
                                        "r" ((char)src) , "0" (dest))
241 
#define _mulqw_(src, dest)      __asm__("mulqw %1,%0" : "=r" (dest) : \
242 
                                        "r" ((short)src) , "0" (dest))
243 
 
244 
/* nop Instruction */
245 
#define _nop_()  __asm__("nop")
246 
 
247 
/* Negate Instructions */
248 
#define _negb_(src, dest)       __asm__("negb %1,%0" : "=r" (dest) : \
249 
                                        "r" ((char)src) , "0" (dest))
250 
#define _negw_(src, dest)       __asm__("negw %1,%0" : "=r" (dest) : \
251 
                                        "r" ((short)src) , "0" (dest))
252 
#define _negd_(src, dest)       __asm__("negd %1,%0" : "=r" (dest) : \
253 
                                        "r" ((int)src) , "0" (dest))
254 
 
255 
/* or Instructions */
256 
#define _orb_(src, dest)        __asm__("orb %1,%0" : "=r" (dest) : \
257 
                                   "ri" ((unsigned char)src) , "0" (dest))
258 
#define _orw_(src, dest)        __asm__("orw %1,%0" : "=r" (dest) : \
259 
                                    "ri" ((unsigned short)src) , "0" (dest))
260 
#define _ord_(src, dest)        __asm__("ord %1,%0" : "=r" (dest)  : \
261 
                                    "ri" ((unsigned int)src) , "0" (dest))
262 
 
263 
/* Pop 1's Count Instructions */
264 
#define _popcntb_(src, dest)    __asm__("popcntb %1,%0" : "=r" (dest) : \
265 
                                        "r" ((char)src) , "0" (dest))
266 
#define _popcntw_(src, dest)    __asm__("popcntw %1,%0" : "=r" (dest) : \
267 
                                        "r" ((short)src) , "0" (dest))
268 
#define _popcntd_(src, dest)    __asm__("popcntd %1,%0" : "=r" (dest)  : \
269 
                                    "r" ((int)src) , "0" (dest))
270 
 
271 
/* Rotate and Mask Instructions */
272 
#define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \
273 
                                                    "=r" (dest) : \
274 
                                                    "i" ((unsigned char) shift), \
275 
                                                    "i" (end), "i" (begin), \
276 
                                                    "r" (src), "0" (dest))
277 
#define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \
278 
                                                    "=r" (dest) : \
279 
                                                    "i" ((unsigned char) shift), \
280 
                                                    "i" (end), "i" (begin), \
281 
                                                    "r" (src), "0" (dest))
282 
 
283 
/* retx Instruction */
284 
#define _retx_()  __asm__("retx")
285 
 
286 
/* Rotate Instructions */
287 
#define _rotb_(shift, dest)  __asm__("rotb %1,%0" : "=r" (dest) : \
288 
                                     "i" ((unsigned char)shift) , "0" (dest))
289 
#define _rotw_(shift, dest)  __asm__("rotw %1,%0" : "=r" (dest) : \
290 
                                     "i" ((unsigned char)shift) , "0" (dest))
291 
#define _rotd_(shift, dest)  __asm__("rotd %1,%0" : "=r" (dest)  : \
292 
                                     "i" ((unsigned char)shift) , "0" (dest))
293 
#define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \
294 
                                     "r" ((unsigned char)shift) , "0" (dest))
295 
#define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \
296 
                                     "r" ((unsigned char)shift) , "0" (dest))
297 
#define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest)  : \
298 
                                     "r" ((unsigned char)shift) , "0" (dest))
299 
#define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \
300 
                                     "r" ((unsigned char)shift) , "0" (dest))
301 
#define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \
302 
                                     "r" ((unsigned char)shift) , "0" (dest))
303 
#define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest)  : \
304 
                                     "r" ((unsigned char)shift) , "0" (dest))
305 
 
306 
/* Set Bit Instructions */
307 
#define _sbitb_(pos,dest)  __asm__("sbitb %1,%0" : "=mr" (dest) : \
308 
                                   "i" ((unsigned char)pos) , "0" (dest) : "cc")
309 
#define _sbitw_(pos,dest)  __asm__("sbitw %1,%0" : "=mr" (dest) : \
310 
                                   "i" ((unsigned char)pos) , "0" (dest) : "cc")
311 
#define _sbitd_(pos,dest)  __asm__("sbitd %1,%0" : "=mr" (dest) : \
312 
                                   "i" ((unsigned char)pos) , "0" (dest) : "cc")
313 
 
314 
/* setrfid Instruction */
315 
#define _setrfid_(src)          __asm__("setrfid %0" : /* No output */  : \
316 
                                        "r" (src) : "cc")
317 
 
318 
/* Sign Extend Instructions */
319 
#define _sextbw_(src, dest)     __asm__("sextbw %1,%0" : "=r" (dest) : \
320 
                                   "r" ((char)src) , "0" (dest) )
321 
#define _sextbd_(src, dest)     __asm__("sextbd %1,%0" : "=r" (dest) : \
322 
                                    "r" ((char)src) , "0" (dest) )
323 
#define _sextwd_(src, dest)     __asm__("sextwd %1,%0" : "=r" (dest) : \
324 
                                    "r" ((short)src) , "0" (dest) )
325 
 
326 
/* Shift Left Logical Instructions */
327 
#define _sllb_(src, dest)       __asm__("sllb %1,%0" : "=r" (dest) : \
328 
                                        "ri" ((unsigned char)src) , "0" (dest))
329 
#define _sllw_(src, dest)       __asm__("sllw %1,%0" : "=r" (dest) : \
330 
                                        "ri" ((unsigned char)src) , "0" (dest))
331 
#define _slld_(src, dest)       __asm__("slld %1,%0" : "=r" (dest)  : \
332 
                                        "ri" ((unsigned char)src) , "0" (dest))
333 
/* Shift Right Arithmetic Instructions */
334 
#define _srab_(src, dest)       __asm__("srab %1,%0" : "=r" (dest) : \
335 
                                        "ri" ((unsigned char)src) , "0" (dest))
336 
#define _sraw_(src, dest)       __asm__("sraw %1,%0" : "=r" (dest) : \
337 
                                        "ri" ((unsigned char)src) , "0" (dest))
338 
#define _srad_(src, dest)       __asm__("srad %1,%0" : "=r" (dest)  : \
339 
                                        "ri" ((unsigned char)src) , "0" (dest))
340 
 
341 
/* Shift Right Logical Instructions */
342 
#define _srlb_(src, dest)       __asm__("srlb %1,%0" : "=r" (dest) : \
343 
                                        "ri" ((unsigned char)src) , "0" (dest))
344 
#define _srlw_(src, dest)       __asm__("srlw %1,%0" : "=r" (dest) : \
345 
                                        "ri" ((unsigned char)src) , "0" (dest))
346 
#define _srld_(src, dest)       __asm__("srld %1,%0" : "=r" (dest)  : \
347 
                                        "ri" ((unsigned char)src) , "0" (dest))
348 
 
349 
/* Store Instructions */
350 
#define _storb_(src,address)    __asm__("storb %1,%0" : "=m" (address) : \
351 
                                        "ri" ((unsigned int)src))
352 
#define _storw_(src,address)    __asm__("storw %1,%0" : "=m" (address) : \
353 
                                        "ri" ((unsigned int)src))
354 
#define _stord_(src,address)    __asm__("stord %1,%0" : "=m" (address) : \
355 
                                        "ri" ((unsigned int)src))
356 
 
357 
/* Store Multiple Instructions */
358 
#define _storm_(mask, src)      __asm__("storm %1,%0" : /* No output here */ : \
359 
                                        "i" (mask) , "r" ((unsigned int)src))
360 
#define _stormp_(mask, src)     __asm__("stormp %1,%0" : /* No output here */ : \
361 
                                        "i" (mask) , "r" ((unsigned int)src))
362 
 
363 
/* Substruct Instructions */
364 
#define _subb_(src, dest)  __asm__("subb        %1, %0" : "=r" (dest) : \
365 
                                   "ri" ((unsigned char)src), "0" (dest) : "cc")
366 
#define _subw_(src, dest)  __asm__("subw        %1, %0" : "=r" (dest) : \
367 
                                   "ri" ((unsigned short)src), "0" (dest) : "cc")
368 
#define _subd_(src, dest)  __asm__("subd        %1, %0" : "=r" (dest) : \
369 
                                   "ri" ((unsigned int)src), "0" (dest) : "cc")
370 
 
371 
/* Substruct with Carry Instructions */
372 
#define _subcb_(src, dest) __asm__("subcb       %1, %0" : "=r" (dest) : \
373 
                                   "ri" ((unsigned char)src), "0" (dest) : "cc")
374 
#define _subcw_(src, dest) __asm__("subcw       %1, %0" : "=r" (dest) : \
375 
                                   "ri" ((unsigned short)src), "0" (dest) : "cc")
376 
#define _subcd_(src, dest) __asm__("subcd       %1, %0" : "=r" (dest) : \
377 
                                   "ri" ((unsigned int)src), "0" (dest) : "cc")
378 
 
379 
/* Q-Format Substruct Instructions */
380 
#define _subqb_(src, dest)      __asm__("subqw %1,%0" : "=r" (dest)  : \
381 
                                        "r" ((char)src) , "0" (dest))
382 
#define _subqw_(src, dest)      __asm__("subqw %1,%0" : "=r" (dest)  : \
383 
                                        "r" ((short)src) , "0" (dest))
384 
#define _subqd_(src, dest)      __asm__("subqd %1,%0" : "=r" (dest)  : \
385 
                                        "r" ((short)src) , "0" (dest))
386 
 
387 
/* Test Bit Instructions */
388 
#define _tbitb_(pos,dest)  __asm__("tbitb %0,%1" : /* No output */ : \
389 
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")
390 
#define _tbitw_(pos,dest)  __asm__("tbitw %0,%1" : /* No output */ : \
391 
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")
392 
#define _tbitd_(pos,dest)  __asm__("tbitd %0,%1" : /* No output */ : \
393 
                                   "i" ((unsigned char)pos) , "rm" (dest) : "cc")
394 
 
395 
/* wait Instruction*/
396 
#define _wait_()                __asm__ volatile ("wait" :  :  : "cc")
397 
 
398 
/* xor Instructions */
399 
#define _xorb_(src, dest)       __asm__("xorb %1,%0" : "=r" (dest) : \
400 
                                   "ri" ((unsigned char)src) , "0" (dest))
401 
#define _xorw_(src, dest)       __asm__("xorw %1,%0" : "=r" (dest) : \
402 
                                    "ri" ((unsigned short)src) , "0" (dest))
403 
#define _xord_(src, dest)       __asm__("xord %1,%0" : "=r" (dest)  : \
404 
                                    "ri" ((unsigned int)src) , "0" (dest))
405 
 
406 
/* Zero Extend Instructions */
407 
#define _zextbw_(src, dest)     __asm__("zextbw %1,%0" : "=r" (dest) : \
408 
                                        "r" ((unsigned char)src) , "0" (dest))
409 
#define _zextbd_(src, dest)     __asm__("zextbd %1,%0" : "=r" (dest) : \
410 
                                        "r" ((unsigned char)src) , "0" (dest))
411 
#define _zextwd_(src, dest)     __asm__("zextwd %1,%0" : "=r" (dest) : \
412 
                                        "r" ((unsigned short)src) , "0" (dest))
413 
 
414 
#define _save_asm_(x) \
415 
  __asm__ volatile (x ::: "memory","cc", \
416 
                    "r0","r1","r2","r3","r4","r5","r6","r7", \
417 
                    "r8","r9","r10","r11","r12","r13")
418 
 
419 
#endif  /* _ASM */
420 
 
421 
 

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