OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [newlib-1.18.0/] [newlib/] [libc/] [machine/] [x86_64/] [x86_64mach.h] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/*
2
 ** This file is distributed WITHOUT ANY WARRANTY; without even the implied
3
 ** warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
4
 */
5
 
6
#ifndef __USER_LABEL_PREFIX__
7
#define __USER_LABEL_PREFIX__ _
8
#endif
9
 
10
#define __REG_PREFIX__ %
11
 
12
/* ANSI concatenation macros.  */
13
 
14
#define CONCAT1(a, b) CONCAT2(a, b)
15
#define CONCAT2(a, b) a##b
16
 
17
/* Use the right prefix for global labels.  */
18
 
19
#define SYM(x) CONCAT1(__USER_LABEL_PREFIX__, x)
20
 
21
/* Use the right prefix for registers.  */
22
 
23
#define REG(x) CONCAT1(__REG_PREFIX__, x)
24
 
25
#define rax REG(rax)
26
#define rbx REG(rbx)
27
#define rcx REG(rcx)
28
#define rdx REG(rdx)
29
#define rsi REG(rsi)
30
#define rdi REG(rdi)
31
#define rbp REG(rbp)
32
#define rsp REG(rsp)
33
 
34
#define r8  REG(r8)
35
#define r9  REG(r9)
36
#define r10 REG(r10)
37
#define r11 REG(r11)
38
#define r12 REG(r12)
39
#define r13 REG(r13)
40
#define r14 REG(r14)
41
#define r15 REG(r15)
42
 
43
#define eax REG(eax)
44
#define ebx REG(ebx)
45
#define ecx REG(ecx)
46
#define edx REG(edx)
47
#define esi REG(esi)
48
#define edi REG(edi)
49
#define ebp REG(ebp)
50
#define esp REG(esp)
51
 
52
#define st0 REG(st)
53
#define st1 REG(st(1))
54
#define st2 REG(st(2))
55
#define st3 REG(st(3))
56
#define st4 REG(st(4))
57
#define st5 REG(st(5))
58
#define st6 REG(st(6))
59
#define st7 REG(st(7))
60
 
61
#define ax REG(ax)
62
#define bx REG(bx)
63
#define cx REG(cx)
64
#define dx REG(dx)
65
 
66
#define ah REG(ah)
67
#define bh REG(bh)
68
#define ch REG(ch)
69
#define dh REG(dh)
70
 
71
#define al REG(al)
72
#define bl REG(bl)
73
#define cl REG(cl)
74
#define dl REG(dl)
75
 
76
#define sil REG(sil)
77
 
78
#define mm1 REG(mm1)
79
#define mm2 REG(mm2)
80
#define mm3 REG(mm3)
81
#define mm4 REG(mm4)
82
#define mm5 REG(mm5)
83
#define mm6 REG(mm6)
84
#define mm7 REG(mm7)
85
 
86
#define xmm0 REG(xmm0)
87
#define xmm1 REG(xmm1)
88
#define xmm2 REG(xmm2)
89
#define xmm3 REG(xmm3)
90
#define xmm4 REG(xmm4)
91
#define xmm5 REG(xmm5)
92
#define xmm6 REG(xmm6)
93
#define xmm7 REG(xmm7)
94
 
95
#define cr0 REG(cr0)
96
#define cr1 REG(cr1)
97
#define cr2 REG(cr2)
98
#define cr3 REG(cr3)
99
#define cr4 REG(cr4)
100
 
101
#ifdef _I386MACH_NEED_SOTYPE_FUNCTION
102
#define SOTYPE_FUNCTION(sym) .type SYM(sym),@function
103
#else
104
#define SOTYPE_FUNCTION(sym)
105
#endif
106
 
107
#ifdef _I386MACH_ALLOW_HW_INTERRUPTS
108
#define        __CLI
109
#define        __STI
110
#else
111
#define __CLI  cli
112
#define __STI  sti
113
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.