URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 185

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, flags are corrected. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
`ifdef OR1200_IMPL_SUB
wire                            cy_sub;
`endif
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_SUB
assign cy_sub = a < b;
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
        casex (alu_op)          // synopsys parallel_case
`else
        casex (alu_op)          // synopsys full_case parallel_case
`endif
                `OR1200_ALUOP_FF1: begin
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                end
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
`endif
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
                end
`endif
                `OR1200_ALUOP_CMOV: begin
                        result = flag ? a : b;
                end
 
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
                        result=result_and;
                end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casex (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casex (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
`ifdef OR1200_IMPL_SUB
        or cy_sub
`endif
`endif
) begin
        casex (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB: begin
                        cyforw = cy_sub;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	141	marcus.erl	`// $Log: or1200_alu.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Defines added, flags are corrected.`
48	10	unneback
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_alu(`
55			`a, b, mult_mac_result, macrc_op,`
56			`alu_op, shrot_op, comp_op,`
57			`cust5_op, cust5_limm,`
58			`result, flagforw, flag_we,`
59			`cyforw, cy_we, carry, flag`
60			`);`
61
62			parameter width = `OR1200_OPERAND_WIDTH;
63
64			`//`
65			`// I/O`
66			`//`
67			`input [width-1:0] a;`
68			`input [width-1:0] b;`
69			`input [width-1:0] mult_mac_result;`
70			`input macrc_op;`
71			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
72			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
73			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
74			`input [4:0] cust5_op;`
75			`input [5:0] cust5_limm;`
76			`output [width-1:0] result;`
77			`output flagforw;`
78			`output flag_we;`
79			`output cyforw;`
80			`output cy_we;`
81			`input carry;`
82			`input flag;`
83
84			`//`
85			`// Internal wires and regs`
86			`//`
87			`reg [width-1:0] result;`
88			`reg [width-1:0] shifted_rotated;`
89			`reg [width-1:0] result_cust5;`
90			`reg flagforw;`
91			`reg flagcomp;`
92			`reg flag_we;`
93			`reg cy_we;`
94			`wire [width-1:0] comp_a;`
95			`wire [width-1:0] comp_b;`
96			`ifdef OR1200_IMPL_ALU_COMP1
97			`wire a_eq_b;`
98			`wire a_lt_b;`
99			`endif
100			`wire [width-1:0] result_sum;`
101			`ifdef OR1200_IMPL_ADDC
102			`wire [width-1:0] result_csum;`
103			`wire cy_csum;`
104			`endif
105			`wire [width-1:0] result_and;`
106			`wire cy_sum;`
107	141	marcus.erl	`ifdef OR1200_IMPL_SUB
108			`wire cy_sub;`
109			`endif
110	10	unneback	`reg cyforw;`
111
112			`//`
113			`// Combinatorial logic`
114			`//`
115			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
116			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
117			`ifdef OR1200_IMPL_ALU_COMP1
118			`assign a_eq_b = (comp_a == comp_b);`
119			`assign a_lt_b = (comp_a < comp_b);`
120			`endif
121	141	marcus.erl	`ifdef OR1200_IMPL_SUB
122			`assign cy_sub = a < b;`
123			`endif
124	10	unneback	`assign {cy_sum, result_sum} = a + b;`
125			`ifdef OR1200_IMPL_ADDC
126	141	marcus.erl	assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
127	10	unneback	`endif
128			`assign result_and = a & b;`
129
130			`//`
131			`// Simulation check for bad ALU behavior`
132			`//`
133			`ifdef OR1200_WARNINGS
134			`// synopsys translate_off`
135			`always @(result) begin`
136			`if (result === 32'bx)`
137			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
138			`end`
139			`// synopsys translate_on`
140			`endif
141
142			`//`
143			`// Central part of the ALU`
144			`//`
145	141	marcus.erl	`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry`
146			`ifdef OR1200_IMPL_ADDC
147			`or result_csum`
148			`endif
149			`) begin`
150	10	unneback	`ifdef OR1200_CASE_DEFAULT
151			`casex (alu_op) // synopsys parallel_case`
152			`else
153			`casex (alu_op) // synopsys full_case parallel_case`
154			`endif
155	141	marcus.erl	`OR1200_ALUOP_FF1: begin
156			`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
157			`end`
158	10	unneback	`OR1200_ALUOP_CUST5 : begin
159			`result = result_cust5;`
160			`end`
161			`OR1200_ALUOP_SHROT : begin
162			`result = shifted_rotated;`
163			`end`
164			`OR1200_ALUOP_ADD : begin
165			`result = result_sum;`
166			`end`
167			`ifdef OR1200_IMPL_ADDC
168			`OR1200_ALUOP_ADDC : begin
169			`result = result_csum;`
170			`end`
171			`endif
172	141	marcus.erl	`ifdef OR1200_IMPL_SUB
173	10	unneback	`OR1200_ALUOP_SUB : begin
174			`result = a - b;`
175			`end`
176	141	marcus.erl	`endif
177	10	unneback	`OR1200_ALUOP_XOR : begin
178			`result = a ^ b;`
179			`end`
180			`OR1200_ALUOP_OR : begin
181			`result = a \| b;`
182			`end`
183			`OR1200_ALUOP_IMM : begin
184			`result = b;`
185			`end`
186			`OR1200_ALUOP_MOVHI : begin
187			`if (macrc_op) begin`
188			`result = mult_mac_result;`
189			`end`
190			`else begin`
191			`result = b << 16;`
192			`end`
193			`end`
194			`ifdef OR1200_MULT_IMPLEMENTED
195			`ifdef OR1200_IMPL_DIV
196			`OR1200_ALUOP_DIV,
197			`OR1200_ALUOP_DIVU,
198			`endif
199			`OR1200_ALUOP_MUL : begin
200			`result = mult_mac_result;`
201			`end`
202			`endif
203	141	marcus.erl	`OR1200_ALUOP_CMOV: begin
204			`result = flag ? a : b;`
205			`end`
206	10	unneback
207			`ifdef OR1200_CASE_DEFAULT
208	141	marcus.erl	`default: begin`
209	10	unneback	`else
210	141	marcus.erl	`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
211	10	unneback	`endif
212	141	marcus.erl	`result=result_and;`
213			`end`
214	10	unneback	`endcase`
215			`end`
216
217			`//`
218			`// l.cust5 custom instructions`
219			`//`
220			`// Examples for move byte, set bit and clear bit`
221			`//`
222			`always @(cust5_op or cust5_limm or a or b) begin`
223			`casex (cust5_op) // synopsys parallel_case`
224			`5'h1 : begin`
225			`casex (cust5_limm[1:0])`
226			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
227			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
228			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
229			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
230			`endcase`
231			`end`
232			`5'h2 :`
233			`result_cust5 = a \| (1 << cust5_limm);`
234			`5'h3 :`
235			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
236			`//`
237			`// * Put here new l.cust5 custom instructions *`
238			`//`
239			`default: begin`
240			`result_cust5 = a;`
241			`end`
242			`endcase`
243			`end`
244
245			`//`
246			`// Generate flag and flag write enable`
247			`//`
248	141	marcus.erl	`always @(alu_op or result_sum or result_and or flagcomp`
249			`ifdef OR1200_IMPL_ADDC
250			`or result_csum`
251			`endif
252			`) begin`
253	10	unneback	`casex (alu_op) // synopsys parallel_case`
254			`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
255			`OR1200_ALUOP_ADD : begin
256			`flagforw = (result_sum == 32'h0000_0000);`
257			`flag_we = 1'b1;`
258			`end`
259			`ifdef OR1200_IMPL_ADDC
260			`OR1200_ALUOP_ADDC : begin
261			`flagforw = (result_csum == 32'h0000_0000);`
262			`flag_we = 1'b1;`
263			`end`
264			`endif
265			`OR1200_ALUOP_AND: begin
266			`flagforw = (result_and == 32'h0000_0000);`
267			`flag_we = 1'b1;`
268			`end`
269			`endif
270			`OR1200_ALUOP_COMP: begin
271			`flagforw = flagcomp;`
272			`flag_we = 1'b1;`
273			`end`
274			`default: begin`
275	141	marcus.erl	`flagforw = flagcomp;`
276	10	unneback	`flag_we = 1'b0;`
277			`end`
278			`endcase`
279			`end`
280
281			`//`
282			`// Generate SR[CY] write enable`
283			`//`
284			`always @(alu_op or cy_sum`
285	141	marcus.erl	`ifdef OR1200_IMPL_CY
286	10	unneback	`ifdef OR1200_IMPL_ADDC
287			`or cy_csum`
288			`endif
289	141	marcus.erl	`ifdef OR1200_IMPL_SUB
290			`or cy_sub`
291			`endif
292			`endif
293			`) begin`
294	10	unneback	`casex (alu_op) // synopsys parallel_case`
295			`ifdef OR1200_IMPL_CY
296			`OR1200_ALUOP_ADD : begin
297			`cyforw = cy_sum;`
298			`cy_we = 1'b1;`
299			`end`
300			`ifdef OR1200_IMPL_ADDC
301			`OR1200_ALUOP_ADDC: begin
302			`cyforw = cy_csum;`
303			`cy_we = 1'b1;`
304			`end`
305			`endif
306	141	marcus.erl	`ifdef OR1200_IMPL_SUB
307			`OR1200_ALUOP_SUB: begin
308			`cyforw = cy_sub;`
309			`cy_we = 1'b1;`
310			`end`
311	10	unneback	`endif
312	141	marcus.erl	`endif
313	10	unneback	`default: begin`
314			`cyforw = 1'b0;`
315			`cy_we = 1'b0;`
316			`end`
317			`endcase`
318			`end`
319
320			`//`
321			`// Shifts and rotation`
322			`//`
323			`always @(shrot_op or a or b) begin`
324			`case (shrot_op) // synopsys parallel_case`
325			`OR1200_SHROTOP_SLL :
326			`shifted_rotated = (a << b[4:0]);`
327			`OR1200_SHROTOP_SRL :
328			`shifted_rotated = (a >> b[4:0]);`
329
330			`ifdef OR1200_IMPL_ALU_ROTATE
331			`OR1200_SHROTOP_ROR :
332			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
333			`endif
334			`default:`
335			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
336			`endcase`
337			`end`
338
339			`//`
340			`// First type of compare implementation`
341			`//`
342			`ifdef OR1200_IMPL_ALU_COMP1
343			`always @(comp_op or a_eq_b or a_lt_b) begin`
344			`case(comp_op[2:0]) // synopsys parallel_case`
345			`OR1200_COP_SFEQ:
346			`flagcomp = a_eq_b;`
347			`OR1200_COP_SFNE:
348			`flagcomp = ~a_eq_b;`
349			`OR1200_COP_SFGT:
350			`flagcomp = ~(a_eq_b \| a_lt_b);`
351			`OR1200_COP_SFGE:
352			`flagcomp = ~a_lt_b;`
353			`OR1200_COP_SFLT:
354			`flagcomp = a_lt_b;`
355			`OR1200_COP_SFLE:
356			`flagcomp = a_eq_b \| a_lt_b;`
357			`default:`
358			`flagcomp = 1'b0;`
359			`endcase`
360			`end`
361			`endif
362
363			`//`
364			`// Second type of compare implementation`
365			`//`
366			`ifdef OR1200_IMPL_ALU_COMP2
367			`always @(comp_op or comp_a or comp_b) begin`
368			`case(comp_op[2:0]) // synopsys parallel_case`
369			`OR1200_COP_SFEQ:
370			`flagcomp = (comp_a == comp_b);`
371			`OR1200_COP_SFNE:
372			`flagcomp = (comp_a != comp_b);`
373			`OR1200_COP_SFGT:
374			`flagcomp = (comp_a > comp_b);`
375			`OR1200_COP_SFGE:
376			`flagcomp = (comp_a >= comp_b);`
377			`OR1200_COP_SFLT:
378			`flagcomp = (comp_a < comp_b);`
379			`OR1200_COP_SFLE:
380			`flagcomp = (comp_a <= comp_b);`
381			`default:`
382			`flagcomp = 1'b0;`
383			`endcase`
384			`end`
385			`endif
386
387			`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 185