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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's ALU                                                ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/project,or1k                       ////
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////                                                              ////
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////  Description                                                 ////
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////  ALU                                                         ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44 141 marcus.erl
// $Log: or1200_alu.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, flags are corrected. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
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`include "or1200_defines.v"
53
 
54
module or1200_alu(
55
        a, b, mult_mac_result, macrc_op,
56 401 julius
        alu_op, alu_op2, shrot_op, comp_op,
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        cust5_op, cust5_limm,
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        result, flagforw, flag_we,
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        cyforw, cy_we, carry, flag
60
);
61
 
62
parameter width = `OR1200_OPERAND_WIDTH;
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64
//
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// I/O
66
//
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input   [width-1:0]              a;
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input   [width-1:0]              b;
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input   [width-1:0]              mult_mac_result;
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input                           macrc_op;
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input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
72 401 julius
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
73 10 unneback
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
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input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
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input   [4:0]                    cust5_op;
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input   [5:0]                    cust5_limm;
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output  [width-1:0]              result;
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output                          flagforw;
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output                          flag_we;
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output                          cyforw;
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output                          cy_we;
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input                           carry;
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input         flag;
84
 
85
//
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// Internal wires and regs
87
//
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reg     [width-1:0]              result;
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reg     [width-1:0]              shifted_rotated;
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reg     [width-1:0]              result_cust5;
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reg                             flagforw;
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reg                             flagcomp;
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reg                             flag_we;
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reg                             cy_we;
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wire    [width-1:0]              comp_a;
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wire    [width-1:0]              comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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wire                            a_eq_b;
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wire                            a_lt_b;
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`endif
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wire    [width-1:0]              result_sum;
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`ifdef OR1200_IMPL_ADDC
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wire    [width-1:0]              result_csum;
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wire                            cy_csum;
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`endif
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wire    [width-1:0]              result_and;
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wire                            cy_sum;
108 141 marcus.erl
`ifdef OR1200_IMPL_SUB
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wire                            cy_sub;
110
`endif
111 10 unneback
reg                             cyforw;
112
 
113
//
114
// Combinatorial logic
115
//
116
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
118
`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
120
assign a_lt_b = (comp_a < comp_b);
121
`endif
122 141 marcus.erl
`ifdef OR1200_IMPL_SUB
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assign cy_sub = a < b;
124
`endif
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assign {cy_sum, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
127 141 marcus.erl
assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
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`endif
129
assign result_and = a & b;
130
 
131
//
132
// Simulation check for bad ALU behavior
133
//
134
`ifdef OR1200_WARNINGS
135
// synopsys translate_off
136
always @(result) begin
137
        if (result === 32'bx)
138
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
139
end
140
// synopsys translate_on
141
`endif
142
 
143
//
144
// Central part of the ALU
145
//
146 401 julius
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
147
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
148 141 marcus.erl
`ifdef OR1200_IMPL_ADDC
149
         or result_csum
150
`endif
151
) begin
152 10 unneback
`ifdef OR1200_CASE_DEFAULT
153 364 julius
        casez (alu_op)          // synopsys parallel_case
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`else
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        casez (alu_op)          // synopsys full_case parallel_case
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`endif
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`ifdef OR1200_IMPL_ALU_FFL1
158
                `OR1200_ALUOP_FFL1: begin
159
`ifdef OR1200_CASE_DEFAULT
160
                   casez (alu_op2) // synopsys parallel_case
161
`else
162
                   casez (alu_op2) // synopsys full_case parallel_case
163
`endif
164
                     0: begin // FF1
165 141 marcus.erl
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
166 401 julius
                     end
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                     default: begin // FL1
168
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
169
                     end
170
                   endcase // casez (alu_op2)
171
                end // case: `OR1200_ALUOP_FFL1
172
`endif
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                `OR1200_ALUOP_CUST5 : begin
174
                                result = result_cust5;
175
                end
176
                `OR1200_ALUOP_SHROT : begin
177
                                result = shifted_rotated;
178
                end
179
                `OR1200_ALUOP_ADD : begin
180
                                result = result_sum;
181
                end
182
`ifdef OR1200_IMPL_ADDC
183
                `OR1200_ALUOP_ADDC : begin
184
                                result = result_csum;
185
                end
186
`endif
187 141 marcus.erl
`ifdef OR1200_IMPL_SUB
188 10 unneback
                `OR1200_ALUOP_SUB : begin
189
                                result = a - b;
190
                end
191 141 marcus.erl
`endif
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                `OR1200_ALUOP_XOR : begin
193
                                result = a ^ b;
194
                end
195
                `OR1200_ALUOP_OR  : begin
196
                                result = a | b;
197
                end
198
                `OR1200_ALUOP_IMM : begin
199
                                result = b;
200
                end
201
                `OR1200_ALUOP_MOVHI : begin
202
                                if (macrc_op) begin
203
                                        result = mult_mac_result;
204
                                end
205
                                else begin
206
                                        result = b << 16;
207
                                end
208
                end
209
`ifdef OR1200_MULT_IMPLEMENTED
210 258 julius
`ifdef OR1200_DIV_IMPLEMENTED
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                `OR1200_ALUOP_DIV,
212
                `OR1200_ALUOP_DIVU,
213
`endif
214
                `OR1200_ALUOP_MUL : begin
215
                                result = mult_mac_result;
216
                end
217
`endif
218 141 marcus.erl
                `OR1200_ALUOP_CMOV: begin
219
                        result = flag ? a : b;
220
                end
221 10 unneback
 
222
`ifdef OR1200_CASE_DEFAULT
223 141 marcus.erl
                default: begin
224 10 unneback
`else
225 141 marcus.erl
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
226 10 unneback
`endif
227 141 marcus.erl
                        result=result_and;
228
                end
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        endcase
230
end
231
 
232
//
233
// l.cust5 custom instructions
234
//
235
// Examples for move byte, set bit and clear bit
236
//
237
always @(cust5_op or cust5_limm or a or b) begin
238 364 julius
        casez (cust5_op)                // synopsys parallel_case
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                5'h1 : begin
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                        casez (cust5_limm[1:0])
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                                2'h0: result_cust5 = {a[31:8], b[7:0]};
242
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
243
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
244
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
245
                        endcase
246
                end
247
                5'h2 :
248
                        result_cust5 = a | (1 << cust5_limm);
249
                5'h3 :
250
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
251
//
252
// *** Put here new l.cust5 custom instructions ***
253
//
254
                default: begin
255
                        result_cust5 = a;
256
                end
257
        endcase
258
end
259
 
260
//
261
// Generate flag and flag write enable
262
//
263 141 marcus.erl
always @(alu_op or result_sum or result_and or flagcomp
264
`ifdef OR1200_IMPL_ADDC
265
         or result_csum
266
`endif
267
) begin
268 364 julius
        casez (alu_op)          // synopsys parallel_case
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`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
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                `OR1200_ALUOP_ADD : begin
271
                        flagforw = (result_sum == 32'h0000_0000);
272
                        flag_we = 1'b1;
273
                end
274
`ifdef OR1200_IMPL_ADDC
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                `OR1200_ALUOP_ADDC : begin
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                        flagforw = (result_csum == 32'h0000_0000);
277
                        flag_we = 1'b1;
278
                end
279
`endif
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                `OR1200_ALUOP_AND: begin
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                        flagforw = (result_and == 32'h0000_0000);
282
                        flag_we = 1'b1;
283
                end
284
`endif
285
                `OR1200_ALUOP_COMP: begin
286
                        flagforw = flagcomp;
287
                        flag_we = 1'b1;
288
                end
289
                default: begin
290 141 marcus.erl
                        flagforw = flagcomp;
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                        flag_we = 1'b0;
292
                end
293
        endcase
294
end
295
 
296
//
297
// Generate SR[CY] write enable
298
//
299
always @(alu_op or cy_sum
300 141 marcus.erl
`ifdef OR1200_IMPL_CY
301 10 unneback
`ifdef OR1200_IMPL_ADDC
302
        or cy_csum
303
`endif
304 141 marcus.erl
`ifdef OR1200_IMPL_SUB
305
        or cy_sub
306
`endif
307
`endif
308
) begin
309 364 julius
        casez (alu_op)          // synopsys parallel_case
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`ifdef OR1200_IMPL_CY
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                `OR1200_ALUOP_ADD : begin
312
                        cyforw = cy_sum;
313
                        cy_we = 1'b1;
314
                end
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`ifdef OR1200_IMPL_ADDC
316
                `OR1200_ALUOP_ADDC: begin
317
                        cyforw = cy_csum;
318
                        cy_we = 1'b1;
319
                end
320
`endif
321 141 marcus.erl
`ifdef OR1200_IMPL_SUB
322
                `OR1200_ALUOP_SUB: begin
323
                        cyforw = cy_sub;
324
                        cy_we = 1'b1;
325
                end
326 10 unneback
`endif
327 141 marcus.erl
`endif
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                default: begin
329
                        cyforw = 1'b0;
330
                        cy_we = 1'b0;
331
                end
332
        endcase
333
end
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335
//
336
// Shifts and rotation
337
//
338
always @(shrot_op or a or b) begin
339
        case (shrot_op)         // synopsys parallel_case
340
        `OR1200_SHROTOP_SLL :
341
                                shifted_rotated = (a << b[4:0]);
342
                `OR1200_SHROTOP_SRL :
343
                                shifted_rotated = (a >> b[4:0]);
344
 
345
`ifdef OR1200_IMPL_ALU_ROTATE
346
                `OR1200_SHROTOP_ROR :
347
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
348
`endif
349
                default:
350
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
351
        endcase
352
end
353
 
354
//
355
// First type of compare implementation
356
//
357
`ifdef OR1200_IMPL_ALU_COMP1
358
always @(comp_op or a_eq_b or a_lt_b) begin
359
        case(comp_op[2:0])       // synopsys parallel_case
360
                `OR1200_COP_SFEQ:
361
                        flagcomp = a_eq_b;
362
                `OR1200_COP_SFNE:
363
                        flagcomp = ~a_eq_b;
364
                `OR1200_COP_SFGT:
365
                        flagcomp = ~(a_eq_b | a_lt_b);
366
                `OR1200_COP_SFGE:
367
                        flagcomp = ~a_lt_b;
368
                `OR1200_COP_SFLT:
369
                        flagcomp = a_lt_b;
370
                `OR1200_COP_SFLE:
371
                        flagcomp = a_eq_b | a_lt_b;
372
                default:
373
                        flagcomp = 1'b0;
374
        endcase
375
end
376
`endif
377
 
378
//
379
// Second type of compare implementation
380
//
381
`ifdef OR1200_IMPL_ALU_COMP2
382
always @(comp_op or comp_a or comp_b) begin
383
        case(comp_op[2:0])       // synopsys parallel_case
384
                `OR1200_COP_SFEQ:
385
                        flagcomp = (comp_a == comp_b);
386
                `OR1200_COP_SFNE:
387
                        flagcomp = (comp_a != comp_b);
388
                `OR1200_COP_SFGT:
389
                        flagcomp = (comp_a > comp_b);
390
                `OR1200_COP_SFGE:
391
                        flagcomp = (comp_a >= comp_b);
392
                `OR1200_COP_SFLT:
393
                        flagcomp = (comp_a < comp_b);
394
                `OR1200_COP_SFLE:
395
                        flagcomp = (comp_a <= comp_b);
396
                default:
397
                        flagcomp = 1'b0;
398
        endcase
399
end
400
`endif
401
 
402
endmodule

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