URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 609

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, flags are corrected. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, alu_op2, shrot_op, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cy_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
`ifdef OR1200_IMPL_ADDC
wire    [width-1:0]              result_csum;
wire                            cy_csum;
`endif
wire    [width-1:0]              result_and;
wire                            cy_sum;
`ifdef OR1200_IMPL_SUB
wire                            cy_sub;
`endif
reg                             cyforw;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_SUB
assign cy_sub = a < b;
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
`endif
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
        casez (alu_op)          // synopsys parallel_case
`else
        casez (alu_op)          // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
                `OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
                   casez (alu_op2) // synopsys parallel_case
`else
                   casez (alu_op2) // synopsys full_case parallel_case
`endif
                     0: begin // FF1
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                     end
                     default: begin // FL1
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                     end
                   endcase // casez (alu_op2)
                end // case: `OR1200_ALUOP_FFL1
`endif
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                                result = result_csum;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
`endif
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL,
                `OR1200_ALUOP_MULU : begin
                                result = mult_mac_result;
                end
`endif
                `OR1200_ALUOP_CMOV: begin
                        result = flag ? a : b;
                end
 
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
                        result=result_and;
                end
        endcase
end
 
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casez (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casez (cust5_limm[1:0])
                                2'h0: result_cust5 = {a[31:8], b[7:0]};
                                2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                                2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                                2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
`ifdef OR1200_IMPL_ADDC
         or result_csum
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC : begin
                        flagforw = (result_csum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
        or cy_csum
`endif
`ifdef OR1200_IMPL_SUB
        or cy_sub
`endif
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC: begin
                        cyforw = cy_csum;
                        cy_we = 1'b1;
                end
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB: begin
                        cyforw = cy_sub;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	141	marcus.erl	`// $Log: or1200_alu.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Defines added, flags are corrected.`
48	10	unneback
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_alu(`
55			`a, b, mult_mac_result, macrc_op,`
56	401	julius	`alu_op, alu_op2, shrot_op, comp_op,`
57	10	unneback	`cust5_op, cust5_limm,`
58			`result, flagforw, flag_we,`
59			`cyforw, cy_we, carry, flag`
60			`);`
61
62			parameter width = `OR1200_OPERAND_WIDTH;
63
64			`//`
65			`// I/O`
66			`//`
67			`input [width-1:0] a;`
68			`input [width-1:0] b;`
69			`input [width-1:0] mult_mac_result;`
70			`input macrc_op;`
71			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
72	401	julius	input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
73	10	unneback	input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
74			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
75			`input [4:0] cust5_op;`
76			`input [5:0] cust5_limm;`
77			`output [width-1:0] result;`
78			`output flagforw;`
79			`output flag_we;`
80			`output cyforw;`
81			`output cy_we;`
82			`input carry;`
83			`input flag;`
84
85			`//`
86			`// Internal wires and regs`
87			`//`
88			`reg [width-1:0] result;`
89			`reg [width-1:0] shifted_rotated;`
90			`reg [width-1:0] result_cust5;`
91			`reg flagforw;`
92			`reg flagcomp;`
93			`reg flag_we;`
94			`reg cy_we;`
95			`wire [width-1:0] comp_a;`
96			`wire [width-1:0] comp_b;`
97			`ifdef OR1200_IMPL_ALU_COMP1
98			`wire a_eq_b;`
99			`wire a_lt_b;`
100			`endif
101			`wire [width-1:0] result_sum;`
102			`ifdef OR1200_IMPL_ADDC
103			`wire [width-1:0] result_csum;`
104			`wire cy_csum;`
105			`endif
106			`wire [width-1:0] result_and;`
107			`wire cy_sum;`
108	141	marcus.erl	`ifdef OR1200_IMPL_SUB
109			`wire cy_sub;`
110			`endif
111	10	unneback	`reg cyforw;`
112
113			`//`
114			`// Combinatorial logic`
115			`//`
116			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
117			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
118			`ifdef OR1200_IMPL_ALU_COMP1
119			`assign a_eq_b = (comp_a == comp_b);`
120			`assign a_lt_b = (comp_a < comp_b);`
121			`endif
122	141	marcus.erl	`ifdef OR1200_IMPL_SUB
123			`assign cy_sub = a < b;`
124			`endif
125	10	unneback	`assign {cy_sum, result_sum} = a + b;`
126			`ifdef OR1200_IMPL_ADDC
127	141	marcus.erl	assign {cy_csum, result_csum} = a + b + {`OR1200_OPERAND_WIDTH'd0, carry};
128	10	unneback	`endif
129			`assign result_and = a & b;`
130
131			`//`
132			`// Simulation check for bad ALU behavior`
133			`//`
134			`ifdef OR1200_WARNINGS
135			`// synopsys translate_off`
136			`always @(result) begin`
137			`if (result === 32'bx)`
138			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
139			`end`
140			`// synopsys translate_on`
141			`endif
142
143			`//`
144			`// Central part of the ALU`
145			`//`
146	401	julius	`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`
147			`or shifted_rotated or mult_mac_result or flag or result_cust5 or carry`
148	141	marcus.erl	`ifdef OR1200_IMPL_ADDC
149			`or result_csum`
150			`endif
151			`) begin`
152	10	unneback	`ifdef OR1200_CASE_DEFAULT
153	364	julius	`casez (alu_op) // synopsys parallel_case`
154	10	unneback	`else
155	364	julius	`casez (alu_op) // synopsys full_case parallel_case`
156	10	unneback	`endif
157	401	julius	`ifdef OR1200_IMPL_ALU_FFL1
158			`OR1200_ALUOP_FFL1: begin
159			`ifdef OR1200_CASE_DEFAULT
160			`casez (alu_op2) // synopsys parallel_case`
161			`else
162			`casez (alu_op2) // synopsys full_case parallel_case`
163			`endif
164			`0: begin // FF1`
165	141	marcus.erl	`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
166	401	julius	`end`
167			`default: begin // FL1`
168			`result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;`
169			`end`
170			`endcase // casez (alu_op2)`
171			end // case: `OR1200_ALUOP_FFL1
172			`endif
173	10	unneback	`OR1200_ALUOP_CUST5 : begin
174			`result = result_cust5;`
175			`end`
176			`OR1200_ALUOP_SHROT : begin
177			`result = shifted_rotated;`
178			`end`
179			`OR1200_ALUOP_ADD : begin
180			`result = result_sum;`
181			`end`
182			`ifdef OR1200_IMPL_ADDC
183			`OR1200_ALUOP_ADDC : begin
184			`result = result_csum;`
185			`end`
186			`endif
187	141	marcus.erl	`ifdef OR1200_IMPL_SUB
188	10	unneback	`OR1200_ALUOP_SUB : begin
189			`result = a - b;`
190			`end`
191	141	marcus.erl	`endif
192	10	unneback	`OR1200_ALUOP_XOR : begin
193			`result = a ^ b;`
194			`end`
195			`OR1200_ALUOP_OR : begin
196			`result = a \| b;`
197			`end`
198			`OR1200_ALUOP_MOVHI : begin
199			`if (macrc_op) begin`
200			`result = mult_mac_result;`
201			`end`
202			`else begin`
203			`result = b << 16;`
204			`end`
205			`end`
206			`ifdef OR1200_MULT_IMPLEMENTED
207	258	julius	`ifdef OR1200_DIV_IMPLEMENTED
208	10	unneback	`OR1200_ALUOP_DIV,
209			`OR1200_ALUOP_DIVU,
210			`endif
211	481	julius	`OR1200_ALUOP_MUL,
212			`OR1200_ALUOP_MULU : begin
213	10	unneback	`result = mult_mac_result;`
214			`end`
215			`endif
216	141	marcus.erl	`OR1200_ALUOP_CMOV: begin
217			`result = flag ? a : b;`
218			`end`
219	10	unneback
220			`ifdef OR1200_CASE_DEFAULT
221	141	marcus.erl	`default: begin`
222	10	unneback	`else
223	141	marcus.erl	`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
224	10	unneback	`endif
225	141	marcus.erl	`result=result_and;`
226			`end`
227	10	unneback	`endcase`
228			`end`
229
230			`//`
231			`// l.cust5 custom instructions`
232			`//`
233			`// Examples for move byte, set bit and clear bit`
234			`//`
235			`always @(cust5_op or cust5_limm or a or b) begin`
236	364	julius	`casez (cust5_op) // synopsys parallel_case`
237	10	unneback	`5'h1 : begin`
238	364	julius	`casez (cust5_limm[1:0])`
239	10	unneback	`2'h0: result_cust5 = {a[31:8], b[7:0]};`
240			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
241			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
242			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
243			`endcase`
244			`end`
245			`5'h2 :`
246			`result_cust5 = a \| (1 << cust5_limm);`
247			`5'h3 :`
248			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
249			`//`
250			`// * Put here new l.cust5 custom instructions *`
251			`//`
252			`default: begin`
253			`result_cust5 = a;`
254			`end`
255			`endcase`
256			`end`
257
258			`//`
259			`// Generate flag and flag write enable`
260			`//`
261	141	marcus.erl	`always @(alu_op or result_sum or result_and or flagcomp`
262			`ifdef OR1200_IMPL_ADDC
263			`or result_csum`
264			`endif
265			`) begin`
266	364	julius	`casez (alu_op) // synopsys parallel_case`
267	10	unneback	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
268			`OR1200_ALUOP_ADD : begin
269			`flagforw = (result_sum == 32'h0000_0000);`
270			`flag_we = 1'b1;`
271			`end`
272			`ifdef OR1200_IMPL_ADDC
273			`OR1200_ALUOP_ADDC : begin
274			`flagforw = (result_csum == 32'h0000_0000);`
275			`flag_we = 1'b1;`
276			`end`
277			`endif
278			`OR1200_ALUOP_AND: begin
279			`flagforw = (result_and == 32'h0000_0000);`
280			`flag_we = 1'b1;`
281			`end`
282			`endif
283			`OR1200_ALUOP_COMP: begin
284			`flagforw = flagcomp;`
285			`flag_we = 1'b1;`
286			`end`
287			`default: begin`
288	141	marcus.erl	`flagforw = flagcomp;`
289	10	unneback	`flag_we = 1'b0;`
290			`end`
291			`endcase`
292			`end`
293
294			`//`
295			`// Generate SR[CY] write enable`
296			`//`
297			`always @(alu_op or cy_sum`
298	141	marcus.erl	`ifdef OR1200_IMPL_CY
299	10	unneback	`ifdef OR1200_IMPL_ADDC
300			`or cy_csum`
301			`endif
302	141	marcus.erl	`ifdef OR1200_IMPL_SUB
303			`or cy_sub`
304			`endif
305			`endif
306			`) begin`
307	364	julius	`casez (alu_op) // synopsys parallel_case`
308	10	unneback	`ifdef OR1200_IMPL_CY
309			`OR1200_ALUOP_ADD : begin
310			`cyforw = cy_sum;`
311			`cy_we = 1'b1;`
312			`end`
313			`ifdef OR1200_IMPL_ADDC
314			`OR1200_ALUOP_ADDC: begin
315			`cyforw = cy_csum;`
316			`cy_we = 1'b1;`
317			`end`
318			`endif
319	141	marcus.erl	`ifdef OR1200_IMPL_SUB
320			`OR1200_ALUOP_SUB: begin
321			`cyforw = cy_sub;`
322			`cy_we = 1'b1;`
323			`end`
324	10	unneback	`endif
325	141	marcus.erl	`endif
326	10	unneback	`default: begin`
327			`cyforw = 1'b0;`
328			`cy_we = 1'b0;`
329			`end`
330			`endcase`
331			`end`
332
333			`//`
334			`// Shifts and rotation`
335			`//`
336			`always @(shrot_op or a or b) begin`
337			`case (shrot_op) // synopsys parallel_case`
338			`OR1200_SHROTOP_SLL :
339			`shifted_rotated = (a << b[4:0]);`
340			`OR1200_SHROTOP_SRL :
341			`shifted_rotated = (a >> b[4:0]);`
342
343			`ifdef OR1200_IMPL_ALU_ROTATE
344			`OR1200_SHROTOP_ROR :
345			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
346			`endif
347			`default:`
348			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
349			`endcase`
350			`end`
351
352			`//`
353			`// First type of compare implementation`
354			`//`
355			`ifdef OR1200_IMPL_ALU_COMP1
356			`always @(comp_op or a_eq_b or a_lt_b) begin`
357			`case(comp_op[2:0]) // synopsys parallel_case`
358			`OR1200_COP_SFEQ:
359			`flagcomp = a_eq_b;`
360			`OR1200_COP_SFNE:
361			`flagcomp = ~a_eq_b;`
362			`OR1200_COP_SFGT:
363			`flagcomp = ~(a_eq_b \| a_lt_b);`
364			`OR1200_COP_SFGE:
365			`flagcomp = ~a_lt_b;`
366			`OR1200_COP_SFLT:
367			`flagcomp = a_lt_b;`
368			`OR1200_COP_SFLE:
369			`flagcomp = a_eq_b \| a_lt_b;`
370			`default:`
371			`flagcomp = 1'b0;`
372			`endcase`
373			`end`
374			`endif
375
376			`//`
377			`// Second type of compare implementation`
378			`//`
379			`ifdef OR1200_IMPL_ALU_COMP2
380			`always @(comp_op or comp_a or comp_b) begin`
381			`case(comp_op[2:0]) // synopsys parallel_case`
382			`OR1200_COP_SFEQ:
383			`flagcomp = (comp_a == comp_b);`
384			`OR1200_COP_SFNE:
385			`flagcomp = (comp_a != comp_b);`
386			`OR1200_COP_SFGT:
387			`flagcomp = (comp_a > comp_b);`
388			`OR1200_COP_SFGE:
389			`flagcomp = (comp_a >= comp_b);`
390			`OR1200_COP_SFLT:
391			`flagcomp = (comp_a < comp_b);`
392			`OR1200_COP_SFLE:
393			`flagcomp = (comp_a <= comp_b);`
394			`default:`
395			`flagcomp = 1'b0;`
396			`endcase`
397			`end`
398			`endif
399
400			`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 609