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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Blame information for rev 588

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66 141 marcus.erl
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69 258 julius
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
70
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
71
        du_lsu_store_dat, du_lsu_load_dat,
72 141 marcus.erl
        abort_mvspr, abort_ex,
73 10 unneback
 
74
        // Data interface
75
        dc_en,
76 258 julius
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
77
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
78
        sb_en, dmmu_en, dc_no_writethrough,
79 10 unneback
 
80 141 marcus.erl
        // SR Interface
81
        boot_adr_sel_i,
82
 
83 10 unneback
        // Interrupt & tick exceptions
84
        sig_int, sig_tick,
85
 
86
        // SPR interface
87
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
88 258 julius
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
89 10 unneback
);
90
 
91
parameter dw = `OR1200_OPERAND_WIDTH;
92
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
93
 
94
//
95
// I/O ports
96
//
97
 
98
//
99
// Clk & Rst
100
//
101
input                           clk;
102
input                           rst;
103
 
104
//
105
// Insn (IC) interface
106
//
107
output                          ic_en;
108
output  [31:0]                   icpu_adr_o;
109
output                          icpu_cycstb_o;
110
output  [3:0]                    icpu_sel_o;
111
output  [3:0]                    icpu_tag_o;
112
input   [31:0]                   icpu_dat_i;
113
input                           icpu_ack_i;
114
input                           icpu_rty_i;
115
input                           icpu_err_i;
116
input   [31:0]                   icpu_adr_i;
117
input   [3:0]                    icpu_tag_i;
118
 
119
//
120
// Insn (IMMU) interface
121
//
122
output                          immu_en;
123
 
124
//
125
// Debug interface
126
//
127 141 marcus.erl
output                          id_void;
128
output  [31:0]                   id_insn;
129
output                          ex_void;
130 10 unneback
output  [31:0]                   ex_insn;
131
output                          ex_freeze;
132 141 marcus.erl
output  [31:0]                   wb_insn;
133
output                          wb_freeze;
134 10 unneback
output  [31:0]                   id_pc;
135 141 marcus.erl
output  [31:0]                   ex_pc;
136
output  [31:0]                   wb_pc;
137
output                          ex_flushpipe;
138 10 unneback
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
139
 
140
input                           du_stall;
141
input   [dw-1:0]         du_addr;
142
input   [dw-1:0]         du_dat_du;
143
input                           du_read;
144
input                           du_write;
145
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
146 141 marcus.erl
input   [24:0]                   du_dmr1;
147 10 unneback
input                           du_hwbkpt;
148 141 marcus.erl
input                           du_hwbkpt_ls_r;
149 185 julius
output  [13:0]                   du_except_trig;
150
output  [13:0]                   du_except_stop;
151 10 unneback
output  [dw-1:0]         du_dat_cpu;
152
output  [dw-1:0]         rf_dataw;
153 141 marcus.erl
output  [dw-1:0]         du_lsu_store_dat;
154
output  [dw-1:0]         du_lsu_load_dat;
155 10 unneback
 
156
//
157
// Data (DC) interface
158
//
159
output  [31:0]                   dcpu_adr_o;
160
output                          dcpu_cycstb_o;
161
output                          dcpu_we_o;
162
output  [3:0]                    dcpu_sel_o;
163
output  [3:0]                    dcpu_tag_o;
164
output  [31:0]                   dcpu_dat_o;
165
input   [31:0]                   dcpu_dat_i;
166
input                           dcpu_ack_i;
167
input                           dcpu_rty_i;
168
input                           dcpu_err_i;
169
input   [3:0]                    dcpu_tag_i;
170
output                          dc_en;
171 258 julius
output                          dc_no_writethrough;
172
 
173 10 unneback
//
174
// Data (DMMU) interface
175
//
176 141 marcus.erl
output                          sb_en;
177 10 unneback
output                          dmmu_en;
178 141 marcus.erl
output                          abort_ex;
179
output                          abort_mvspr;
180 10 unneback
 
181
//
182 141 marcus.erl
// SR Interface 
183
//
184
input                           boot_adr_sel_i;
185
 
186
//
187 10 unneback
// SPR interface
188
//
189
output                          supv;
190
input   [dw-1:0]         spr_dat_pic;
191
input   [dw-1:0]         spr_dat_tt;
192
input   [dw-1:0]         spr_dat_pm;
193
input   [dw-1:0]         spr_dat_dmmu;
194
input   [dw-1:0]         spr_dat_immu;
195
input   [dw-1:0]         spr_dat_du;
196
output  [dw-1:0]         spr_addr;
197
output  [dw-1:0]         spr_dat_cpu;
198
output  [dw-1:0]         spr_dat_npc;
199
output  [31:0]                   spr_cs;
200
output                          spr_we;
201 258 julius
input                           mtspr_dc_done;
202
 
203 10 unneback
//
204
// Interrupt exceptions
205
//
206
input                           sig_int;
207
input                           sig_tick;
208
 
209
//
210
// Internal wires
211
//
212
wire    [31:0]                   if_insn;
213 141 marcus.erl
wire                            saving_if_insn;
214 10 unneback
wire    [31:0]                   if_pc;
215
wire    [aw-1:0]         rf_addrw;
216
wire    [aw-1:0]                 rf_addra;
217
wire    [aw-1:0]                 rf_addrb;
218
wire                            rf_rda;
219
wire                            rf_rdb;
220 141 marcus.erl
wire    [dw-1:0]         id_simm;
221
wire    [dw-1:2]                id_branch_addrtarget;
222
wire    [dw-1:2]                ex_branch_addrtarget;
223 10 unneback
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
224 401 julius
wire    [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
225 10 unneback
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
226
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
227 141 marcus.erl
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
228 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
229 141 marcus.erl
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
230 10 unneback
wire                            genpc_freeze;
231
wire                            if_freeze;
232
wire                            id_freeze;
233
wire                            ex_freeze;
234
wire                            wb_freeze;
235
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
236
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
237
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
238 185 julius
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
239 10 unneback
wire    [dw-1:0]         rf_dataw;
240
wire    [dw-1:0]         rf_dataa;
241
wire    [dw-1:0]         rf_datab;
242 141 marcus.erl
wire    [dw-1:0]         muxed_a;
243 10 unneback
wire    [dw-1:0]         muxed_b;
244
wire    [dw-1:0]         wb_forw;
245
wire                            wbforw_valid;
246
wire    [dw-1:0]         operand_a;
247
wire    [dw-1:0]         operand_b;
248
wire    [dw-1:0]         alu_dataout;
249
wire    [dw-1:0]         lsu_dataout;
250
wire    [dw-1:0]         sprs_dataout;
251 185 julius
wire    [dw-1:0]         fpu_dataout;
252 258 julius
wire                            fpu_done;
253 141 marcus.erl
wire    [31:0]                   ex_simm;
254 10 unneback
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
255 258 julius
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
256 10 unneback
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
257
wire    [4:0]                    cust5_op;
258
wire    [5:0]                    cust5_limm;
259 141 marcus.erl
wire                            if_flushpipe;
260
wire                            id_flushpipe;
261
wire                            ex_flushpipe;
262
wire                            wb_flushpipe;
263 10 unneback
wire                            extend_flush;
264 141 marcus.erl
wire                            ex_branch_taken;
265 10 unneback
wire                            flag;
266
wire                            flagforw;
267
wire                            flag_we;
268 185 julius
wire                            flagforw_alu;
269 141 marcus.erl
wire                            flag_we_alu;
270 185 julius
wire                            flagforw_fpu;
271
wire                            flag_we_fpu;
272 10 unneback
wire                            carry;
273
wire                            cyforw;
274 141 marcus.erl
wire                            cy_we_alu;
275
wire                            cy_we_rf;
276 10 unneback
wire                            lsu_stall;
277
wire                            epcr_we;
278
wire                            eear_we;
279
wire                            esr_we;
280
wire                            pc_we;
281
wire    [31:0]                   epcr;
282
wire    [31:0]                   eear;
283
wire    [`OR1200_SR_WIDTH-1:0]   esr;
284 185 julius
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
285 258 julius
wire                            fpcsr_we;
286 10 unneback
wire                            sr_we;
287
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
288
wire    [`OR1200_SR_WIDTH-1:0]   sr;
289 141 marcus.erl
wire                            except_flushpipe;
290 10 unneback
wire                            except_start;
291
wire                            except_started;
292 185 julius
wire                            fpu_except_started;
293 10 unneback
wire    [31:0]                   wb_insn;
294
wire                            sig_syscall;
295
wire                            sig_trap;
296 185 julius
wire                            sig_fp;
297 10 unneback
wire    [31:0]                   spr_dat_cfgr;
298
wire    [31:0]                   spr_dat_rf;
299
wire    [31:0]                  spr_dat_npc;
300
wire    [31:0]                   spr_dat_ppc;
301
wire    [31:0]                   spr_dat_mac;
302 258 julius
wire [31:0]                      spr_dat_fpu;
303
wire                            mtspr_done;
304 10 unneback
wire                            force_dslot_fetch;
305
wire                            no_more_dslot;
306
wire                            ex_void;
307 141 marcus.erl
wire                            ex_spr_read;
308
wire                            ex_spr_write;
309 10 unneback
wire                            if_stall;
310
wire                            id_macrc_op;
311
wire                            ex_macrc_op;
312 141 marcus.erl
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
313 10 unneback
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
314
wire    [31:0]                   mult_mac_result;
315 481 julius
wire                            mult_mac_stall;
316 185 julius
wire    [13:0]                   except_trig;
317
wire    [13:0]                   except_stop;
318 10 unneback
wire                            genpc_refetch;
319
wire                            rfe;
320
wire                            lsu_unstall;
321
wire                            except_align;
322
wire                            except_dtlbmiss;
323
wire                            except_dmmufault;
324
wire                            except_illegal;
325
wire                            except_itlbmiss;
326
wire                            except_immufault;
327
wire                            except_ibuserr;
328
wire                            except_dbuserr;
329
wire                            abort_ex;
330 141 marcus.erl
wire                            abort_mvspr;
331 10 unneback
 
332
//
333
// Send exceptions to Debug Unit
334
//
335 141 marcus.erl
assign du_except_trig = except_trig;
336
assign du_except_stop = except_stop;
337
assign du_lsu_store_dat = operand_b;
338
assign du_lsu_load_dat  = lsu_dataout;
339 10 unneback
 
340
//
341
// Data cache enable
342
//
343 141 marcus.erl
`ifdef OR1200_NO_DC
344
assign dc_en = 1'b0;
345
`else
346 258 julius
   assign dc_en = sr[`OR1200_SR_DCE];
347 141 marcus.erl
`endif
348 10 unneback
 
349
//
350
// Instruction cache enable
351
//
352 141 marcus.erl
`ifdef OR1200_NO_IC
353
assign ic_en = 1'b0;
354
`else
355 10 unneback
assign ic_en = sr[`OR1200_SR_ICE];
356 141 marcus.erl
`endif
357 10 unneback
 
358
//
359 141 marcus.erl
// SB enable
360
//
361
`ifdef OR1200_SB_IMPLEMENTED
362
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
363
`else
364
assign sb_en = 1'b0;
365
`endif
366
 
367
//
368 10 unneback
// DMMU enable
369
//
370 141 marcus.erl
`ifdef OR1200_NO_DMMU
371
assign dmmu_en = 1'b0;
372
`else
373 10 unneback
assign dmmu_en = sr[`OR1200_SR_DME];
374 141 marcus.erl
`endif
375 10 unneback
 
376
//
377
// IMMU enable
378
//
379 141 marcus.erl
`ifdef OR1200_NO_IMMU
380
assign immu_en = 1'b0;
381
`else
382
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
383
`endif
384 10 unneback
 
385
//
386
// SUPV bit
387
//
388
assign supv = sr[`OR1200_SR_SM];
389
 
390
//
391 141 marcus.erl
// FLAG write enable
392
//
393 185 julius
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
394
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
395 141 marcus.erl
 
396
//
397 258 julius
//  Flag for any MTSPR instructions, that must block execution, to indicate done
398
//
399
assign mtspr_done = mtspr_dc_done;
400
 
401
 
402
//
403 10 unneback
// Instantiation of instruction fetch block
404
//
405
or1200_genpc or1200_genpc(
406
        .clk(clk),
407
        .rst(rst),
408
        .icpu_adr_o(icpu_adr_o),
409
        .icpu_cycstb_o(icpu_cycstb_o),
410
        .icpu_sel_o(icpu_sel_o),
411
        .icpu_tag_o(icpu_tag_o),
412
        .icpu_rty_i(icpu_rty_i),
413
        .icpu_adr_i(icpu_adr_i),
414
 
415 141 marcus.erl
        .pre_branch_op(pre_branch_op),
416 10 unneback
        .branch_op(branch_op),
417
        .except_type(except_type),
418
        .except_start(except_start),
419
        .except_prefix(sr[`OR1200_SR_EPH]),
420 141 marcus.erl
        .id_branch_addrtarget(id_branch_addrtarget),
421
        .ex_branch_addrtarget(ex_branch_addrtarget),
422
        .muxed_b(muxed_b),
423
        .operand_b(operand_b),
424 10 unneback
        .flag(flag),
425 141 marcus.erl
        .flagforw(flagforw),
426
        .ex_branch_taken(ex_branch_taken),
427 10 unneback
        .epcr(epcr),
428
        .spr_dat_i(spr_dat_cpu),
429
        .spr_pc_we(pc_we),
430
        .genpc_refetch(genpc_refetch),
431
        .genpc_freeze(genpc_freeze),
432
        .no_more_dslot(no_more_dslot)
433
);
434
 
435
//
436
// Instantiation of instruction fetch block
437
//
438
or1200_if or1200_if(
439
        .clk(clk),
440
        .rst(rst),
441
        .icpu_dat_i(icpu_dat_i),
442
        .icpu_ack_i(icpu_ack_i),
443
        .icpu_err_i(icpu_err_i),
444
        .icpu_adr_i(icpu_adr_i),
445
        .icpu_tag_i(icpu_tag_i),
446
 
447
        .if_freeze(if_freeze),
448
        .if_insn(if_insn),
449
        .if_pc(if_pc),
450 141 marcus.erl
        .saving_if_insn(saving_if_insn),
451
        .if_flushpipe(if_flushpipe),
452 10 unneback
        .if_stall(if_stall),
453
        .no_more_dslot(no_more_dslot),
454
        .genpc_refetch(genpc_refetch),
455
        .rfe(rfe),
456
        .except_itlbmiss(except_itlbmiss),
457
        .except_immufault(except_immufault),
458
        .except_ibuserr(except_ibuserr)
459
);
460
 
461
//
462
// Instantiation of instruction decode/control logic
463
//
464
or1200_ctrl or1200_ctrl(
465
        .clk(clk),
466
        .rst(rst),
467
        .id_freeze(id_freeze),
468
        .ex_freeze(ex_freeze),
469
        .wb_freeze(wb_freeze),
470 141 marcus.erl
        .if_flushpipe(if_flushpipe),
471
        .id_flushpipe(id_flushpipe),
472
        .ex_flushpipe(ex_flushpipe),
473
        .wb_flushpipe(wb_flushpipe),
474
        .extend_flush(extend_flush),
475
        .except_flushpipe(except_flushpipe),
476
        .abort_mvspr(abort_mvspr),
477 10 unneback
        .if_insn(if_insn),
478 141 marcus.erl
        .id_insn(id_insn),
479 10 unneback
        .ex_insn(ex_insn),
480 141 marcus.erl
        .id_branch_op(pre_branch_op),
481
        .ex_branch_op(branch_op),
482
        .ex_branch_taken(ex_branch_taken),
483 10 unneback
        .rf_addra(rf_addra),
484
        .rf_addrb(rf_addrb),
485
        .rf_rda(rf_rda),
486
        .rf_rdb(rf_rdb),
487
        .alu_op(alu_op),
488 401 julius
        .alu_op2(alu_op2),
489 10 unneback
        .mac_op(mac_op),
490
        .shrot_op(shrot_op),
491
        .comp_op(comp_op),
492
        .rf_addrw(rf_addrw),
493
        .rfwb_op(rfwb_op),
494 185 julius
        .fpu_op(fpu_op),
495 141 marcus.erl
        .pc_we(pc_we),
496 10 unneback
        .wb_insn(wb_insn),
497 141 marcus.erl
        .id_simm(id_simm),
498
        .id_branch_addrtarget(id_branch_addrtarget),
499
        .ex_branch_addrtarget(ex_branch_addrtarget),
500
        .ex_simm(ex_simm),
501 10 unneback
        .sel_a(sel_a),
502
        .sel_b(sel_b),
503 141 marcus.erl
        .id_lsu_op(id_lsu_op),
504 10 unneback
        .cust5_op(cust5_op),
505
        .cust5_limm(cust5_limm),
506 141 marcus.erl
        .id_pc(id_pc),
507
        .ex_pc(ex_pc),
508 10 unneback
        .multicycle(multicycle),
509 258 julius
        .wait_on(wait_on),
510 10 unneback
        .wbforw_valid(wbforw_valid),
511
        .sig_syscall(sig_syscall),
512
        .sig_trap(sig_trap),
513
        .force_dslot_fetch(force_dslot_fetch),
514
        .no_more_dslot(no_more_dslot),
515 141 marcus.erl
        .id_void(id_void),
516 10 unneback
        .ex_void(ex_void),
517 141 marcus.erl
        .ex_spr_read(ex_spr_read),
518
        .ex_spr_write(ex_spr_write),
519
        .id_mac_op(id_mac_op),
520 10 unneback
        .id_macrc_op(id_macrc_op),
521
        .ex_macrc_op(ex_macrc_op),
522
        .rfe(rfe),
523
        .du_hwbkpt(du_hwbkpt),
524 258 julius
        .except_illegal(except_illegal),
525
        .dc_no_writethrough(dc_no_writethrough)
526 10 unneback
);
527
 
528
//
529
// Instantiation of register file
530
//
531
or1200_rf or1200_rf(
532
        .clk(clk),
533
        .rst(rst),
534 141 marcus.erl
        .cy_we_i(cy_we_alu),
535
        .cy_we_o(cy_we_rf),
536 10 unneback
        .supv(sr[`OR1200_SR_SM]),
537
        .wb_freeze(wb_freeze),
538
        .addrw(rf_addrw),
539
        .dataw(rf_dataw),
540
        .id_freeze(id_freeze),
541
        .we(rfwb_op[0]),
542 141 marcus.erl
        .flushpipe(wb_flushpipe),
543 10 unneback
        .addra(rf_addra),
544
        .rda(rf_rda),
545
        .dataa(rf_dataa),
546
        .addrb(rf_addrb),
547
        .rdb(rf_rdb),
548
        .datab(rf_datab),
549
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
550
        .spr_write(spr_we),
551
        .spr_addr(spr_addr),
552
        .spr_dat_i(spr_dat_cpu),
553 258 julius
        .spr_dat_o(spr_dat_rf),
554
        .du_read(du_read)
555 10 unneback
);
556
 
557
//
558
// Instantiation of operand muxes
559
//
560
or1200_operandmuxes or1200_operandmuxes(
561
        .clk(clk),
562
        .rst(rst),
563
        .id_freeze(id_freeze),
564
        .ex_freeze(ex_freeze),
565
        .rf_dataa(rf_dataa),
566
        .rf_datab(rf_datab),
567
        .ex_forw(rf_dataw),
568
        .wb_forw(wb_forw),
569 141 marcus.erl
        .simm(id_simm),
570 10 unneback
        .sel_a(sel_a),
571
        .sel_b(sel_b),
572
        .operand_a(operand_a),
573
        .operand_b(operand_b),
574 141 marcus.erl
        .muxed_a(muxed_a),
575 10 unneback
        .muxed_b(muxed_b)
576
);
577
 
578
//
579
// Instantiation of CPU's ALU
580
//
581
or1200_alu or1200_alu(
582
        .a(operand_a),
583
        .b(operand_b),
584
        .mult_mac_result(mult_mac_result),
585
        .macrc_op(ex_macrc_op),
586
        .alu_op(alu_op),
587 401 julius
        .alu_op2(alu_op2),
588 10 unneback
        .shrot_op(shrot_op),
589
        .comp_op(comp_op),
590
        .cust5_op(cust5_op),
591
        .cust5_limm(cust5_limm),
592
        .result(alu_dataout),
593 185 julius
        .flagforw(flagforw_alu),
594 141 marcus.erl
        .flag_we(flag_we_alu),
595 10 unneback
        .cyforw(cyforw),
596 141 marcus.erl
        .cy_we(cy_we_alu),
597
        .flag(flag),
598 10 unneback
        .carry(carry)
599
);
600
 
601 185 julius
 
602 10 unneback
//
603 185 julius
// FPU's exception is being dealt with
604
//    
605
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
606
 
607 10 unneback
//
608 185 julius
// Instantiation of FPU
609
//
610
or1200_fpu or1200_fpu(
611
        .clk(clk),
612
        .rst(rst),
613
        .ex_freeze(ex_freeze),
614
        .a(operand_a),
615
        .b(operand_b),
616
        .fpu_op(fpu_op),
617
        .result(fpu_dataout),
618 258 julius
        .done(fpu_done),
619 185 julius
        .flagforw(flagforw_fpu),
620
        .flag_we(flag_we_fpu),
621
        .sig_fp(sig_fp),
622 258 julius
        .except_started(fpu_except_started),
623 185 julius
        .fpcsr_we(fpcsr_we),
624 258 julius
        .fpcsr(fpcsr),
625 185 julius
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
626
        .spr_write(spr_we),
627
        .spr_addr(spr_addr),
628
        .spr_dat_i(spr_dat_cpu),
629
        .spr_dat_o(spr_dat_fpu)
630
);
631
 
632
 
633
//
634
// Instantiation of CPU's multiply unit
635
//
636 10 unneback
or1200_mult_mac or1200_mult_mac(
637
        .clk(clk),
638
        .rst(rst),
639
        .ex_freeze(ex_freeze),
640
        .id_macrc_op(id_macrc_op),
641
        .macrc_op(ex_macrc_op),
642
        .a(operand_a),
643
        .b(operand_b),
644
        .mac_op(mac_op),
645
        .alu_op(alu_op),
646
        .result(mult_mac_result),
647 481 julius
        .mult_mac_stall(mult_mac_stall),
648 10 unneback
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
649
        .spr_write(spr_we),
650
        .spr_addr(spr_addr),
651
        .spr_dat_i(spr_dat_cpu),
652
        .spr_dat_o(spr_dat_mac)
653
);
654
 
655
//
656
// Instantiation of CPU's SPRS block
657
//
658
or1200_sprs or1200_sprs(
659
        .clk(clk),
660
        .rst(rst),
661
        .addrbase(operand_a),
662 141 marcus.erl
        .addrofs(ex_simm[15:0]),
663 10 unneback
        .dat_i(operand_b),
664 141 marcus.erl
        .ex_spr_read(ex_spr_read),
665
        .ex_spr_write(ex_spr_write),
666 10 unneback
        .flagforw(flagforw),
667
        .flag_we(flag_we),
668
        .flag(flag),
669
        .cyforw(cyforw),
670 141 marcus.erl
        .cy_we(cy_we_rf),
671 10 unneback
        .carry(carry),
672
        .to_wbmux(sprs_dataout),
673
 
674
        .du_addr(du_addr),
675
        .du_dat_du(du_dat_du),
676
        .du_read(du_read),
677
        .du_write(du_write),
678
        .du_dat_cpu(du_dat_cpu),
679 141 marcus.erl
        .boot_adr_sel_i(boot_adr_sel_i),
680 10 unneback
        .spr_addr(spr_addr),
681
        .spr_dat_pic(spr_dat_pic),
682
        .spr_dat_tt(spr_dat_tt),
683
        .spr_dat_pm(spr_dat_pm),
684
        .spr_dat_cfgr(spr_dat_cfgr),
685
        .spr_dat_rf(spr_dat_rf),
686
        .spr_dat_npc(spr_dat_npc),
687
        .spr_dat_ppc(spr_dat_ppc),
688
        .spr_dat_mac(spr_dat_mac),
689
        .spr_dat_dmmu(spr_dat_dmmu),
690
        .spr_dat_immu(spr_dat_immu),
691
        .spr_dat_du(spr_dat_du),
692
        .spr_dat_o(spr_dat_cpu),
693
        .spr_cs(spr_cs),
694
        .spr_we(spr_we),
695
 
696
        .epcr_we(epcr_we),
697
        .eear_we(eear_we),
698
        .esr_we(esr_we),
699
        .pc_we(pc_we),
700
        .epcr(epcr),
701
        .eear(eear),
702
        .esr(esr),
703
        .except_started(except_started),
704
 
705 185 julius
        .fpcsr(fpcsr),
706 258 julius
        .fpcsr_we(fpcsr_we),
707 185 julius
        .spr_dat_fpu(spr_dat_fpu),
708
 
709 10 unneback
        .sr_we(sr_we),
710
        .to_sr(to_sr),
711
        .sr(sr),
712
        .branch_op(branch_op)
713
);
714
 
715
//
716
// Instantiation of load/store unit
717
//
718
or1200_lsu or1200_lsu(
719 141 marcus.erl
        .clk(clk),
720
        .rst(rst),
721
        .id_addrbase(muxed_a),
722
        .id_addrofs(id_simm),
723
        .ex_addrbase(operand_a),
724
        .ex_addrofs(ex_simm),
725
        .id_lsu_op(id_lsu_op),
726 10 unneback
        .lsu_datain(operand_b),
727
        .lsu_dataout(lsu_dataout),
728
        .lsu_stall(lsu_stall),
729
        .lsu_unstall(lsu_unstall),
730 141 marcus.erl
        .du_stall(du_stall),
731 10 unneback
        .except_align(except_align),
732
        .except_dtlbmiss(except_dtlbmiss),
733
        .except_dmmufault(except_dmmufault),
734
        .except_dbuserr(except_dbuserr),
735 141 marcus.erl
        .id_freeze(id_freeze),
736
        .ex_freeze(ex_freeze),
737
        .flushpipe(ex_flushpipe),
738 10 unneback
 
739
        .dcpu_adr_o(dcpu_adr_o),
740
        .dcpu_cycstb_o(dcpu_cycstb_o),
741
        .dcpu_we_o(dcpu_we_o),
742
        .dcpu_sel_o(dcpu_sel_o),
743
        .dcpu_tag_o(dcpu_tag_o),
744
        .dcpu_dat_o(dcpu_dat_o),
745
        .dcpu_dat_i(dcpu_dat_i),
746
        .dcpu_ack_i(dcpu_ack_i),
747
        .dcpu_rty_i(dcpu_rty_i),
748
        .dcpu_err_i(dcpu_err_i),
749
        .dcpu_tag_i(dcpu_tag_i)
750
);
751
 
752
//
753
// Instantiation of write-back muxes
754
//
755
or1200_wbmux or1200_wbmux(
756
        .clk(clk),
757
        .rst(rst),
758
        .wb_freeze(wb_freeze),
759
        .rfwb_op(rfwb_op),
760
        .muxin_a(alu_dataout),
761
        .muxin_b(lsu_dataout),
762
        .muxin_c(sprs_dataout),
763 141 marcus.erl
        .muxin_d(ex_pc),
764 185 julius
        .muxin_e(fpu_dataout),
765 10 unneback
        .muxout(rf_dataw),
766
        .muxreg(wb_forw),
767
        .muxreg_valid(wbforw_valid)
768
);
769
 
770
//
771
// Instantiation of freeze logic
772
//
773
or1200_freeze or1200_freeze(
774
        .clk(clk),
775
        .rst(rst),
776
        .multicycle(multicycle),
777 258 julius
        .wait_on(wait_on),
778
        .fpu_done(fpu_done),
779
        .mtspr_done(mtspr_done),
780 141 marcus.erl
        .flushpipe(wb_flushpipe),
781 10 unneback
        .extend_flush(extend_flush),
782
        .lsu_stall(lsu_stall),
783
        .if_stall(if_stall),
784
        .lsu_unstall(lsu_unstall),
785
        .force_dslot_fetch(force_dslot_fetch),
786
        .abort_ex(abort_ex),
787
        .du_stall(du_stall),
788 481 julius
        .mac_stall(mult_mac_stall),
789 141 marcus.erl
        .saving_if_insn(saving_if_insn),
790 10 unneback
        .genpc_freeze(genpc_freeze),
791
        .if_freeze(if_freeze),
792
        .id_freeze(id_freeze),
793
        .ex_freeze(ex_freeze),
794
        .wb_freeze(wb_freeze),
795
        .icpu_ack_i(icpu_ack_i),
796
        .icpu_err_i(icpu_err_i)
797
);
798
 
799
//
800
// Instantiation of exception block
801
//
802
or1200_except or1200_except(
803
        .clk(clk),
804
        .rst(rst),
805
        .sig_ibuserr(except_ibuserr),
806
        .sig_dbuserr(except_dbuserr),
807
        .sig_illegal(except_illegal),
808
        .sig_align(except_align),
809
        .sig_range(1'b0),
810
        .sig_dtlbmiss(except_dtlbmiss),
811
        .sig_dmmufault(except_dmmufault),
812
        .sig_int(sig_int),
813
        .sig_syscall(sig_syscall),
814
        .sig_trap(sig_trap),
815
        .sig_itlbmiss(except_itlbmiss),
816
        .sig_immufault(except_immufault),
817
        .sig_tick(sig_tick),
818 185 julius
        .sig_fp(sig_fp),
819 258 julius
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
820 141 marcus.erl
        .ex_branch_taken(ex_branch_taken),
821 10 unneback
        .icpu_ack_i(icpu_ack_i),
822
        .icpu_err_i(icpu_err_i),
823
        .dcpu_ack_i(dcpu_ack_i),
824
        .dcpu_err_i(dcpu_err_i),
825
        .genpc_freeze(genpc_freeze),
826
        .id_freeze(id_freeze),
827
        .ex_freeze(ex_freeze),
828
        .wb_freeze(wb_freeze),
829
        .if_stall(if_stall),
830
        .if_pc(if_pc),
831
        .id_pc(id_pc),
832 141 marcus.erl
        .ex_pc(ex_pc),
833
        .wb_pc(wb_pc),
834
        .id_flushpipe(id_flushpipe),
835
        .ex_flushpipe(ex_flushpipe),
836 10 unneback
        .extend_flush(extend_flush),
837 141 marcus.erl
        .except_flushpipe(except_flushpipe),
838
        .abort_mvspr(abort_mvspr),
839 10 unneback
        .except_type(except_type),
840
        .except_start(except_start),
841
        .except_started(except_started),
842
        .except_stop(except_stop),
843 141 marcus.erl
        .except_trig(except_trig),
844 10 unneback
        .ex_void(ex_void),
845
        .spr_dat_ppc(spr_dat_ppc),
846
        .spr_dat_npc(spr_dat_npc),
847
 
848 141 marcus.erl
        .datain(spr_dat_cpu),
849
        .branch_op(branch_op),
850 10 unneback
        .du_dsr(du_dsr),
851 141 marcus.erl
        .du_dmr1(du_dmr1),
852
        .du_hwbkpt(du_hwbkpt),
853
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
854 10 unneback
        .epcr_we(epcr_we),
855
        .eear_we(eear_we),
856
        .esr_we(esr_we),
857
        .pc_we(pc_we),
858
        .epcr(epcr),
859
        .eear(eear),
860
        .esr(esr),
861
 
862
        .lsu_addr(dcpu_adr_o),
863
        .sr_we(sr_we),
864
        .to_sr(to_sr),
865
        .sr(sr),
866
        .abort_ex(abort_ex)
867
);
868
 
869
//
870
// Instantiation of configuration registers
871
//
872
or1200_cfgr or1200_cfgr(
873
        .spr_addr(spr_addr),
874
        .spr_dat_o(spr_dat_cfgr)
875
);
876
 
877
endmodule

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