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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Blame information for rev 808

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66 141 marcus.erl
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69 258 julius
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
70
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
71
        du_lsu_store_dat, du_lsu_load_dat,
72 141 marcus.erl
        abort_mvspr, abort_ex,
73 10 unneback
 
74
        // Data interface
75
        dc_en,
76 258 julius
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
77
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
78
        sb_en, dmmu_en, dc_no_writethrough,
79 10 unneback
 
80 141 marcus.erl
        // SR Interface
81
        boot_adr_sel_i,
82
 
83 10 unneback
        // Interrupt & tick exceptions
84
        sig_int, sig_tick,
85
 
86
        // SPR interface
87
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
88 258 julius
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
89 10 unneback
);
90
 
91
parameter dw = `OR1200_OPERAND_WIDTH;
92
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
93
 
94
//
95
// I/O ports
96
//
97
 
98
//
99
// Clk & Rst
100
//
101
input                           clk;
102
input                           rst;
103
 
104
//
105
// Insn (IC) interface
106
//
107
output                          ic_en;
108
output  [31:0]                   icpu_adr_o;
109
output                          icpu_cycstb_o;
110
output  [3:0]                    icpu_sel_o;
111
output  [3:0]                    icpu_tag_o;
112
input   [31:0]                   icpu_dat_i;
113
input                           icpu_ack_i;
114
input                           icpu_rty_i;
115
input                           icpu_err_i;
116
input   [31:0]                   icpu_adr_i;
117
input   [3:0]                    icpu_tag_i;
118
 
119
//
120
// Insn (IMMU) interface
121
//
122
output                          immu_en;
123
 
124
//
125
// Debug interface
126
//
127 141 marcus.erl
output                          id_void;
128
output  [31:0]                   id_insn;
129
output                          ex_void;
130 10 unneback
output  [31:0]                   ex_insn;
131
output                          ex_freeze;
132 141 marcus.erl
output  [31:0]                   wb_insn;
133
output                          wb_freeze;
134 10 unneback
output  [31:0]                   id_pc;
135 141 marcus.erl
output  [31:0]                   ex_pc;
136
output  [31:0]                   wb_pc;
137
output                          ex_flushpipe;
138 10 unneback
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
139
 
140
input                           du_stall;
141
input   [dw-1:0]         du_addr;
142
input   [dw-1:0]         du_dat_du;
143
input                           du_read;
144
input                           du_write;
145
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
146 141 marcus.erl
input   [24:0]                   du_dmr1;
147 10 unneback
input                           du_hwbkpt;
148 141 marcus.erl
input                           du_hwbkpt_ls_r;
149 185 julius
output  [13:0]                   du_except_trig;
150
output  [13:0]                   du_except_stop;
151 10 unneback
output  [dw-1:0]         du_dat_cpu;
152
output  [dw-1:0]         rf_dataw;
153 141 marcus.erl
output  [dw-1:0]         du_lsu_store_dat;
154
output  [dw-1:0]         du_lsu_load_dat;
155 10 unneback
 
156
//
157
// Data (DC) interface
158
//
159
output  [31:0]                   dcpu_adr_o;
160
output                          dcpu_cycstb_o;
161
output                          dcpu_we_o;
162
output  [3:0]                    dcpu_sel_o;
163
output  [3:0]                    dcpu_tag_o;
164
output  [31:0]                   dcpu_dat_o;
165
input   [31:0]                   dcpu_dat_i;
166
input                           dcpu_ack_i;
167
input                           dcpu_rty_i;
168
input                           dcpu_err_i;
169
input   [3:0]                    dcpu_tag_i;
170
output                          dc_en;
171 258 julius
output                          dc_no_writethrough;
172
 
173 10 unneback
//
174
// Data (DMMU) interface
175
//
176 141 marcus.erl
output                          sb_en;
177 10 unneback
output                          dmmu_en;
178 141 marcus.erl
output                          abort_ex;
179
output                          abort_mvspr;
180 10 unneback
 
181
//
182 141 marcus.erl
// SR Interface 
183
//
184
input                           boot_adr_sel_i;
185
 
186
//
187 10 unneback
// SPR interface
188
//
189
output                          supv;
190
input   [dw-1:0]         spr_dat_pic;
191
input   [dw-1:0]         spr_dat_tt;
192
input   [dw-1:0]         spr_dat_pm;
193
input   [dw-1:0]         spr_dat_dmmu;
194
input   [dw-1:0]         spr_dat_immu;
195
input   [dw-1:0]         spr_dat_du;
196
output  [dw-1:0]         spr_addr;
197
output  [dw-1:0]         spr_dat_cpu;
198
output  [dw-1:0]         spr_dat_npc;
199
output  [31:0]                   spr_cs;
200
output                          spr_we;
201 258 julius
input                           mtspr_dc_done;
202
 
203 10 unneback
//
204
// Interrupt exceptions
205
//
206
input                           sig_int;
207
input                           sig_tick;
208
 
209
//
210
// Internal wires
211
//
212
wire    [31:0]                   if_insn;
213 141 marcus.erl
wire                            saving_if_insn;
214 10 unneback
wire    [31:0]                   if_pc;
215
wire    [aw-1:0]         rf_addrw;
216
wire    [aw-1:0]                 rf_addra;
217
wire    [aw-1:0]                 rf_addrb;
218
wire                            rf_rda;
219
wire                            rf_rdb;
220 141 marcus.erl
wire    [dw-1:0]         id_simm;
221
wire    [dw-1:2]                id_branch_addrtarget;
222
wire    [dw-1:2]                ex_branch_addrtarget;
223 10 unneback
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
224 401 julius
wire    [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
225 10 unneback
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
226 141 marcus.erl
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
227 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
228 141 marcus.erl
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
229 10 unneback
wire                            genpc_freeze;
230
wire                            if_freeze;
231
wire                            id_freeze;
232
wire                            ex_freeze;
233
wire                            wb_freeze;
234
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
235
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
236
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
237 185 julius
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
238 10 unneback
wire    [dw-1:0]         rf_dataw;
239
wire    [dw-1:0]         rf_dataa;
240
wire    [dw-1:0]         rf_datab;
241 141 marcus.erl
wire    [dw-1:0]         muxed_a;
242 10 unneback
wire    [dw-1:0]         muxed_b;
243
wire    [dw-1:0]         wb_forw;
244
wire                            wbforw_valid;
245
wire    [dw-1:0]         operand_a;
246
wire    [dw-1:0]         operand_b;
247
wire    [dw-1:0]         alu_dataout;
248
wire    [dw-1:0]         lsu_dataout;
249
wire    [dw-1:0]         sprs_dataout;
250 185 julius
wire    [dw-1:0]         fpu_dataout;
251 258 julius
wire                            fpu_done;
252 141 marcus.erl
wire    [31:0]                   ex_simm;
253 10 unneback
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
254 258 julius
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
255 10 unneback
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
256
wire    [4:0]                    cust5_op;
257
wire    [5:0]                    cust5_limm;
258 141 marcus.erl
wire                            if_flushpipe;
259
wire                            id_flushpipe;
260
wire                            ex_flushpipe;
261
wire                            wb_flushpipe;
262 10 unneback
wire                            extend_flush;
263 141 marcus.erl
wire                            ex_branch_taken;
264 10 unneback
wire                            flag;
265
wire                            flagforw;
266
wire                            flag_we;
267 185 julius
wire                            flagforw_alu;
268 141 marcus.erl
wire                            flag_we_alu;
269 185 julius
wire                            flagforw_fpu;
270
wire                            flag_we_fpu;
271 10 unneback
wire                            carry;
272
wire                            cyforw;
273 141 marcus.erl
wire                            cy_we_alu;
274 642 julius
wire                            ovforw;
275
wire                            ov_we_alu;
276
wire                            ovforw_mult_mac;
277
wire                            ov_we_mult_mac;
278 141 marcus.erl
wire                            cy_we_rf;
279 10 unneback
wire                            lsu_stall;
280
wire                            epcr_we;
281
wire                            eear_we;
282
wire                            esr_we;
283
wire                            pc_we;
284
wire    [31:0]                   epcr;
285
wire    [31:0]                   eear;
286
wire    [`OR1200_SR_WIDTH-1:0]   esr;
287 185 julius
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
288 258 julius
wire                            fpcsr_we;
289 10 unneback
wire                            sr_we;
290
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
291
wire    [`OR1200_SR_WIDTH-1:0]   sr;
292 808 julius
wire                            dsx;
293 141 marcus.erl
wire                            except_flushpipe;
294 10 unneback
wire                            except_start;
295
wire                            except_started;
296 185 julius
wire                            fpu_except_started;
297 10 unneback
wire    [31:0]                   wb_insn;
298
wire                            sig_syscall;
299
wire                            sig_trap;
300 642 julius
wire                            sig_range;
301 185 julius
wire                            sig_fp;
302 10 unneback
wire    [31:0]                   spr_dat_cfgr;
303
wire    [31:0]                   spr_dat_rf;
304
wire    [31:0]                  spr_dat_npc;
305
wire    [31:0]                   spr_dat_ppc;
306
wire    [31:0]                   spr_dat_mac;
307 258 julius
wire [31:0]                      spr_dat_fpu;
308
wire                            mtspr_done;
309 10 unneback
wire                            force_dslot_fetch;
310
wire                            no_more_dslot;
311
wire                            ex_void;
312 141 marcus.erl
wire                            ex_spr_read;
313
wire                            ex_spr_write;
314 10 unneback
wire                            if_stall;
315
wire                            id_macrc_op;
316
wire                            ex_macrc_op;
317 141 marcus.erl
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
318 10 unneback
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
319
wire    [31:0]                   mult_mac_result;
320 481 julius
wire                            mult_mac_stall;
321 185 julius
wire    [13:0]                   except_trig;
322
wire    [13:0]                   except_stop;
323 10 unneback
wire                            genpc_refetch;
324
wire                            rfe;
325
wire                            lsu_unstall;
326
wire                            except_align;
327
wire                            except_dtlbmiss;
328
wire                            except_dmmufault;
329
wire                            except_illegal;
330
wire                            except_itlbmiss;
331
wire                            except_immufault;
332
wire                            except_ibuserr;
333
wire                            except_dbuserr;
334
wire                            abort_ex;
335 141 marcus.erl
wire                            abort_mvspr;
336 10 unneback
 
337
//
338
// Send exceptions to Debug Unit
339
//
340 141 marcus.erl
assign du_except_trig = except_trig;
341
assign du_except_stop = except_stop;
342
assign du_lsu_store_dat = operand_b;
343
assign du_lsu_load_dat  = lsu_dataout;
344 10 unneback
 
345
//
346
// Data cache enable
347
//
348 141 marcus.erl
`ifdef OR1200_NO_DC
349
assign dc_en = 1'b0;
350
`else
351 258 julius
   assign dc_en = sr[`OR1200_SR_DCE];
352 141 marcus.erl
`endif
353 10 unneback
 
354
//
355
// Instruction cache enable
356
//
357 141 marcus.erl
`ifdef OR1200_NO_IC
358
assign ic_en = 1'b0;
359
`else
360 10 unneback
assign ic_en = sr[`OR1200_SR_ICE];
361 141 marcus.erl
`endif
362 10 unneback
 
363
//
364 141 marcus.erl
// SB enable
365
//
366
`ifdef OR1200_SB_IMPLEMENTED
367
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
368
`else
369
assign sb_en = 1'b0;
370
`endif
371
 
372
//
373 10 unneback
// DMMU enable
374
//
375 141 marcus.erl
`ifdef OR1200_NO_DMMU
376
assign dmmu_en = 1'b0;
377
`else
378 10 unneback
assign dmmu_en = sr[`OR1200_SR_DME];
379 141 marcus.erl
`endif
380 10 unneback
 
381
//
382
// IMMU enable
383
//
384 141 marcus.erl
`ifdef OR1200_NO_IMMU
385
assign immu_en = 1'b0;
386
`else
387
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
388
`endif
389 10 unneback
 
390
//
391
// SUPV bit
392
//
393
assign supv = sr[`OR1200_SR_SM];
394
 
395
//
396 141 marcus.erl
// FLAG write enable
397
//
398 185 julius
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
399
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
400 141 marcus.erl
 
401
//
402 642 julius
// Flag for any MTSPR instructions, that must block execution, to indicate done
403 258 julius
//
404
assign mtspr_done = mtspr_dc_done;
405 642 julius
 
406
//
407
// Range exception
408
//
409
assign sig_range = sr[`OR1200_SR_OV];
410 258 julius
 
411
 
412 642 julius
 
413 258 julius
//
414 10 unneback
// Instantiation of instruction fetch block
415
//
416
or1200_genpc or1200_genpc(
417
        .clk(clk),
418
        .rst(rst),
419
        .icpu_adr_o(icpu_adr_o),
420
        .icpu_cycstb_o(icpu_cycstb_o),
421
        .icpu_sel_o(icpu_sel_o),
422
        .icpu_tag_o(icpu_tag_o),
423
        .icpu_rty_i(icpu_rty_i),
424
        .icpu_adr_i(icpu_adr_i),
425
 
426 141 marcus.erl
        .pre_branch_op(pre_branch_op),
427 10 unneback
        .branch_op(branch_op),
428
        .except_type(except_type),
429
        .except_start(except_start),
430
        .except_prefix(sr[`OR1200_SR_EPH]),
431 141 marcus.erl
        .id_branch_addrtarget(id_branch_addrtarget),
432
        .ex_branch_addrtarget(ex_branch_addrtarget),
433
        .muxed_b(muxed_b),
434
        .operand_b(operand_b),
435 10 unneback
        .flag(flag),
436 141 marcus.erl
        .flagforw(flagforw),
437
        .ex_branch_taken(ex_branch_taken),
438 10 unneback
        .epcr(epcr),
439
        .spr_dat_i(spr_dat_cpu),
440
        .spr_pc_we(pc_we),
441
        .genpc_refetch(genpc_refetch),
442
        .genpc_freeze(genpc_freeze),
443
        .no_more_dslot(no_more_dslot)
444
);
445
 
446
//
447
// Instantiation of instruction fetch block
448
//
449
or1200_if or1200_if(
450
        .clk(clk),
451
        .rst(rst),
452
        .icpu_dat_i(icpu_dat_i),
453
        .icpu_ack_i(icpu_ack_i),
454
        .icpu_err_i(icpu_err_i),
455
        .icpu_adr_i(icpu_adr_i),
456
        .icpu_tag_i(icpu_tag_i),
457
 
458
        .if_freeze(if_freeze),
459
        .if_insn(if_insn),
460
        .if_pc(if_pc),
461 141 marcus.erl
        .saving_if_insn(saving_if_insn),
462
        .if_flushpipe(if_flushpipe),
463 10 unneback
        .if_stall(if_stall),
464
        .no_more_dslot(no_more_dslot),
465
        .genpc_refetch(genpc_refetch),
466
        .rfe(rfe),
467
        .except_itlbmiss(except_itlbmiss),
468
        .except_immufault(except_immufault),
469
        .except_ibuserr(except_ibuserr)
470
);
471
 
472
//
473
// Instantiation of instruction decode/control logic
474
//
475
or1200_ctrl or1200_ctrl(
476
        .clk(clk),
477
        .rst(rst),
478
        .id_freeze(id_freeze),
479
        .ex_freeze(ex_freeze),
480
        .wb_freeze(wb_freeze),
481 141 marcus.erl
        .if_flushpipe(if_flushpipe),
482
        .id_flushpipe(id_flushpipe),
483
        .ex_flushpipe(ex_flushpipe),
484
        .wb_flushpipe(wb_flushpipe),
485
        .extend_flush(extend_flush),
486
        .except_flushpipe(except_flushpipe),
487
        .abort_mvspr(abort_mvspr),
488 10 unneback
        .if_insn(if_insn),
489 141 marcus.erl
        .id_insn(id_insn),
490 10 unneback
        .ex_insn(ex_insn),
491 141 marcus.erl
        .id_branch_op(pre_branch_op),
492
        .ex_branch_op(branch_op),
493
        .ex_branch_taken(ex_branch_taken),
494 10 unneback
        .rf_addra(rf_addra),
495
        .rf_addrb(rf_addrb),
496
        .rf_rda(rf_rda),
497
        .rf_rdb(rf_rdb),
498
        .alu_op(alu_op),
499 401 julius
        .alu_op2(alu_op2),
500 10 unneback
        .mac_op(mac_op),
501
        .comp_op(comp_op),
502
        .rf_addrw(rf_addrw),
503
        .rfwb_op(rfwb_op),
504 185 julius
        .fpu_op(fpu_op),
505 141 marcus.erl
        .pc_we(pc_we),
506 10 unneback
        .wb_insn(wb_insn),
507 141 marcus.erl
        .id_simm(id_simm),
508
        .id_branch_addrtarget(id_branch_addrtarget),
509
        .ex_branch_addrtarget(ex_branch_addrtarget),
510
        .ex_simm(ex_simm),
511 10 unneback
        .sel_a(sel_a),
512
        .sel_b(sel_b),
513 141 marcus.erl
        .id_lsu_op(id_lsu_op),
514 10 unneback
        .cust5_op(cust5_op),
515
        .cust5_limm(cust5_limm),
516 141 marcus.erl
        .id_pc(id_pc),
517
        .ex_pc(ex_pc),
518 10 unneback
        .multicycle(multicycle),
519 258 julius
        .wait_on(wait_on),
520 10 unneback
        .wbforw_valid(wbforw_valid),
521
        .sig_syscall(sig_syscall),
522
        .sig_trap(sig_trap),
523
        .force_dslot_fetch(force_dslot_fetch),
524
        .no_more_dslot(no_more_dslot),
525 141 marcus.erl
        .id_void(id_void),
526 10 unneback
        .ex_void(ex_void),
527 141 marcus.erl
        .ex_spr_read(ex_spr_read),
528
        .ex_spr_write(ex_spr_write),
529
        .id_mac_op(id_mac_op),
530 10 unneback
        .id_macrc_op(id_macrc_op),
531
        .ex_macrc_op(ex_macrc_op),
532
        .rfe(rfe),
533
        .du_hwbkpt(du_hwbkpt),
534 258 julius
        .except_illegal(except_illegal),
535
        .dc_no_writethrough(dc_no_writethrough)
536 10 unneback
);
537
 
538
//
539
// Instantiation of register file
540
//
541
or1200_rf or1200_rf(
542
        .clk(clk),
543
        .rst(rst),
544 141 marcus.erl
        .cy_we_i(cy_we_alu),
545
        .cy_we_o(cy_we_rf),
546 10 unneback
        .supv(sr[`OR1200_SR_SM]),
547
        .wb_freeze(wb_freeze),
548
        .addrw(rf_addrw),
549
        .dataw(rf_dataw),
550
        .id_freeze(id_freeze),
551
        .we(rfwb_op[0]),
552 141 marcus.erl
        .flushpipe(wb_flushpipe),
553 10 unneback
        .addra(rf_addra),
554
        .rda(rf_rda),
555
        .dataa(rf_dataa),
556
        .addrb(rf_addrb),
557
        .rdb(rf_rdb),
558
        .datab(rf_datab),
559
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
560
        .spr_write(spr_we),
561
        .spr_addr(spr_addr),
562
        .spr_dat_i(spr_dat_cpu),
563 258 julius
        .spr_dat_o(spr_dat_rf),
564
        .du_read(du_read)
565 10 unneback
);
566
 
567
//
568
// Instantiation of operand muxes
569
//
570
or1200_operandmuxes or1200_operandmuxes(
571
        .clk(clk),
572
        .rst(rst),
573
        .id_freeze(id_freeze),
574
        .ex_freeze(ex_freeze),
575
        .rf_dataa(rf_dataa),
576
        .rf_datab(rf_datab),
577
        .ex_forw(rf_dataw),
578
        .wb_forw(wb_forw),
579 141 marcus.erl
        .simm(id_simm),
580 10 unneback
        .sel_a(sel_a),
581
        .sel_b(sel_b),
582
        .operand_a(operand_a),
583
        .operand_b(operand_b),
584 141 marcus.erl
        .muxed_a(muxed_a),
585 10 unneback
        .muxed_b(muxed_b)
586
);
587
 
588
//
589
// Instantiation of CPU's ALU
590
//
591
or1200_alu or1200_alu(
592
        .a(operand_a),
593
        .b(operand_b),
594
        .mult_mac_result(mult_mac_result),
595
        .macrc_op(ex_macrc_op),
596
        .alu_op(alu_op),
597 401 julius
        .alu_op2(alu_op2),
598 10 unneback
        .comp_op(comp_op),
599
        .cust5_op(cust5_op),
600
        .cust5_limm(cust5_limm),
601
        .result(alu_dataout),
602 185 julius
        .flagforw(flagforw_alu),
603 141 marcus.erl
        .flag_we(flag_we_alu),
604 10 unneback
        .cyforw(cyforw),
605 141 marcus.erl
        .cy_we(cy_we_alu),
606 642 julius
        .ovforw(ovforw),
607
        .ov_we(ov_we_alu),
608 141 marcus.erl
        .flag(flag),
609 10 unneback
        .carry(carry)
610
);
611
 
612 185 julius
 
613 10 unneback
//
614 185 julius
// FPU's exception is being dealt with
615
//    
616
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
617
 
618 10 unneback
//
619 185 julius
// Instantiation of FPU
620
//
621
or1200_fpu or1200_fpu(
622
        .clk(clk),
623
        .rst(rst),
624
        .ex_freeze(ex_freeze),
625
        .a(operand_a),
626
        .b(operand_b),
627
        .fpu_op(fpu_op),
628
        .result(fpu_dataout),
629 258 julius
        .done(fpu_done),
630 185 julius
        .flagforw(flagforw_fpu),
631
        .flag_we(flag_we_fpu),
632
        .sig_fp(sig_fp),
633 258 julius
        .except_started(fpu_except_started),
634 185 julius
        .fpcsr_we(fpcsr_we),
635 258 julius
        .fpcsr(fpcsr),
636 185 julius
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
637
        .spr_write(spr_we),
638
        .spr_addr(spr_addr),
639
        .spr_dat_i(spr_dat_cpu),
640
        .spr_dat_o(spr_dat_fpu)
641
);
642
 
643
 
644
//
645
// Instantiation of CPU's multiply unit
646
//
647 10 unneback
or1200_mult_mac or1200_mult_mac(
648
        .clk(clk),
649
        .rst(rst),
650
        .ex_freeze(ex_freeze),
651
        .id_macrc_op(id_macrc_op),
652
        .macrc_op(ex_macrc_op),
653
        .a(operand_a),
654
        .b(operand_b),
655
        .mac_op(mac_op),
656
        .alu_op(alu_op),
657
        .result(mult_mac_result),
658 642 julius
        .ovforw(ovforw_mult_mac),
659
        .ov_we(ov_we_mult_mac),
660 481 julius
        .mult_mac_stall(mult_mac_stall),
661 10 unneback
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
662
        .spr_write(spr_we),
663
        .spr_addr(spr_addr),
664
        .spr_dat_i(spr_dat_cpu),
665
        .spr_dat_o(spr_dat_mac)
666
);
667
 
668
//
669
// Instantiation of CPU's SPRS block
670
//
671
or1200_sprs or1200_sprs(
672
        .clk(clk),
673
        .rst(rst),
674
        .addrbase(operand_a),
675 141 marcus.erl
        .addrofs(ex_simm[15:0]),
676 10 unneback
        .dat_i(operand_b),
677 141 marcus.erl
        .ex_spr_read(ex_spr_read),
678
        .ex_spr_write(ex_spr_write),
679 10 unneback
        .flagforw(flagforw),
680
        .flag_we(flag_we),
681
        .flag(flag),
682
        .cyforw(cyforw),
683 141 marcus.erl
        .cy_we(cy_we_rf),
684 10 unneback
        .carry(carry),
685 642 julius
        .ovforw(ovforw | ovforw_mult_mac),
686
        .ov_we(ov_we_alu | ov_we_mult_mac),
687 10 unneback
        .to_wbmux(sprs_dataout),
688
 
689
        .du_addr(du_addr),
690
        .du_dat_du(du_dat_du),
691
        .du_read(du_read),
692
        .du_write(du_write),
693
        .du_dat_cpu(du_dat_cpu),
694 141 marcus.erl
        .boot_adr_sel_i(boot_adr_sel_i),
695 10 unneback
        .spr_addr(spr_addr),
696
        .spr_dat_pic(spr_dat_pic),
697
        .spr_dat_tt(spr_dat_tt),
698
        .spr_dat_pm(spr_dat_pm),
699
        .spr_dat_cfgr(spr_dat_cfgr),
700
        .spr_dat_rf(spr_dat_rf),
701
        .spr_dat_npc(spr_dat_npc),
702
        .spr_dat_ppc(spr_dat_ppc),
703
        .spr_dat_mac(spr_dat_mac),
704
        .spr_dat_dmmu(spr_dat_dmmu),
705
        .spr_dat_immu(spr_dat_immu),
706
        .spr_dat_du(spr_dat_du),
707
        .spr_dat_o(spr_dat_cpu),
708
        .spr_cs(spr_cs),
709
        .spr_we(spr_we),
710
 
711
        .epcr_we(epcr_we),
712
        .eear_we(eear_we),
713
        .esr_we(esr_we),
714
        .pc_we(pc_we),
715
        .epcr(epcr),
716
        .eear(eear),
717
        .esr(esr),
718
        .except_started(except_started),
719
 
720 185 julius
        .fpcsr(fpcsr),
721 258 julius
        .fpcsr_we(fpcsr_we),
722 185 julius
        .spr_dat_fpu(spr_dat_fpu),
723
 
724 10 unneback
        .sr_we(sr_we),
725
        .to_sr(to_sr),
726
        .sr(sr),
727 808 julius
        .branch_op(branch_op),
728
        .dsx(dsx)
729 10 unneback
);
730
 
731
//
732
// Instantiation of load/store unit
733
//
734
or1200_lsu or1200_lsu(
735 141 marcus.erl
        .clk(clk),
736
        .rst(rst),
737
        .id_addrbase(muxed_a),
738
        .id_addrofs(id_simm),
739
        .ex_addrbase(operand_a),
740
        .ex_addrofs(ex_simm),
741
        .id_lsu_op(id_lsu_op),
742 10 unneback
        .lsu_datain(operand_b),
743
        .lsu_dataout(lsu_dataout),
744
        .lsu_stall(lsu_stall),
745
        .lsu_unstall(lsu_unstall),
746 141 marcus.erl
        .du_stall(du_stall),
747 10 unneback
        .except_align(except_align),
748
        .except_dtlbmiss(except_dtlbmiss),
749
        .except_dmmufault(except_dmmufault),
750
        .except_dbuserr(except_dbuserr),
751 141 marcus.erl
        .id_freeze(id_freeze),
752
        .ex_freeze(ex_freeze),
753
        .flushpipe(ex_flushpipe),
754 10 unneback
 
755
        .dcpu_adr_o(dcpu_adr_o),
756
        .dcpu_cycstb_o(dcpu_cycstb_o),
757
        .dcpu_we_o(dcpu_we_o),
758
        .dcpu_sel_o(dcpu_sel_o),
759
        .dcpu_tag_o(dcpu_tag_o),
760
        .dcpu_dat_o(dcpu_dat_o),
761
        .dcpu_dat_i(dcpu_dat_i),
762
        .dcpu_ack_i(dcpu_ack_i),
763
        .dcpu_rty_i(dcpu_rty_i),
764
        .dcpu_err_i(dcpu_err_i),
765
        .dcpu_tag_i(dcpu_tag_i)
766
);
767
 
768
//
769
// Instantiation of write-back muxes
770
//
771
or1200_wbmux or1200_wbmux(
772
        .clk(clk),
773
        .rst(rst),
774
        .wb_freeze(wb_freeze),
775
        .rfwb_op(rfwb_op),
776
        .muxin_a(alu_dataout),
777
        .muxin_b(lsu_dataout),
778
        .muxin_c(sprs_dataout),
779 141 marcus.erl
        .muxin_d(ex_pc),
780 185 julius
        .muxin_e(fpu_dataout),
781 10 unneback
        .muxout(rf_dataw),
782
        .muxreg(wb_forw),
783
        .muxreg_valid(wbforw_valid)
784
);
785
 
786
//
787
// Instantiation of freeze logic
788
//
789
or1200_freeze or1200_freeze(
790
        .clk(clk),
791
        .rst(rst),
792
        .multicycle(multicycle),
793 258 julius
        .wait_on(wait_on),
794
        .fpu_done(fpu_done),
795
        .mtspr_done(mtspr_done),
796 141 marcus.erl
        .flushpipe(wb_flushpipe),
797 10 unneback
        .extend_flush(extend_flush),
798
        .lsu_stall(lsu_stall),
799
        .if_stall(if_stall),
800
        .lsu_unstall(lsu_unstall),
801
        .force_dslot_fetch(force_dslot_fetch),
802
        .abort_ex(abort_ex),
803
        .du_stall(du_stall),
804 481 julius
        .mac_stall(mult_mac_stall),
805 141 marcus.erl
        .saving_if_insn(saving_if_insn),
806 10 unneback
        .genpc_freeze(genpc_freeze),
807
        .if_freeze(if_freeze),
808
        .id_freeze(id_freeze),
809
        .ex_freeze(ex_freeze),
810
        .wb_freeze(wb_freeze),
811
        .icpu_ack_i(icpu_ack_i),
812
        .icpu_err_i(icpu_err_i)
813
);
814
 
815
//
816
// Instantiation of exception block
817
//
818
or1200_except or1200_except(
819
        .clk(clk),
820
        .rst(rst),
821
        .sig_ibuserr(except_ibuserr),
822
        .sig_dbuserr(except_dbuserr),
823
        .sig_illegal(except_illegal),
824
        .sig_align(except_align),
825 642 julius
        .sig_range(sig_range),
826 10 unneback
        .sig_dtlbmiss(except_dtlbmiss),
827
        .sig_dmmufault(except_dmmufault),
828
        .sig_int(sig_int),
829
        .sig_syscall(sig_syscall),
830
        .sig_trap(sig_trap),
831
        .sig_itlbmiss(except_itlbmiss),
832
        .sig_immufault(except_immufault),
833
        .sig_tick(sig_tick),
834 185 julius
        .sig_fp(sig_fp),
835 258 julius
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
836 141 marcus.erl
        .ex_branch_taken(ex_branch_taken),
837 10 unneback
        .icpu_ack_i(icpu_ack_i),
838
        .icpu_err_i(icpu_err_i),
839
        .dcpu_ack_i(dcpu_ack_i),
840
        .dcpu_err_i(dcpu_err_i),
841
        .genpc_freeze(genpc_freeze),
842
        .id_freeze(id_freeze),
843
        .ex_freeze(ex_freeze),
844
        .wb_freeze(wb_freeze),
845
        .if_stall(if_stall),
846
        .if_pc(if_pc),
847
        .id_pc(id_pc),
848 141 marcus.erl
        .ex_pc(ex_pc),
849
        .wb_pc(wb_pc),
850
        .id_flushpipe(id_flushpipe),
851
        .ex_flushpipe(ex_flushpipe),
852 10 unneback
        .extend_flush(extend_flush),
853 141 marcus.erl
        .except_flushpipe(except_flushpipe),
854
        .abort_mvspr(abort_mvspr),
855 10 unneback
        .except_type(except_type),
856
        .except_start(except_start),
857
        .except_started(except_started),
858
        .except_stop(except_stop),
859 141 marcus.erl
        .except_trig(except_trig),
860 10 unneback
        .ex_void(ex_void),
861
        .spr_dat_ppc(spr_dat_ppc),
862
        .spr_dat_npc(spr_dat_npc),
863
 
864 141 marcus.erl
        .datain(spr_dat_cpu),
865
        .branch_op(branch_op),
866 10 unneback
        .du_dsr(du_dsr),
867 141 marcus.erl
        .du_dmr1(du_dmr1),
868
        .du_hwbkpt(du_hwbkpt),
869
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
870 10 unneback
        .epcr_we(epcr_we),
871
        .eear_we(eear_we),
872
        .esr_we(esr_we),
873
        .pc_we(pc_we),
874
        .epcr(epcr),
875
        .eear(eear),
876
        .esr(esr),
877
 
878
        .lsu_addr(dcpu_adr_o),
879
        .sr_we(sr_we),
880
        .to_sr(to_sr),
881
        .sr(sr),
882 808 julius
        .abort_ex(abort_ex),
883
        .dsx(dsx)
884 10 unneback
);
885
 
886
//
887
// Instantiation of configuration registers
888
//
889
or1200_cfgr or1200_cfgr(
890
        .spr_addr(spr_addr),
891
        .spr_dat_o(spr_dat_cfgr)
892
);
893
 
894
endmodule

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