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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Blame information for rev 815

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66 141 marcus.erl
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69 258 julius
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
70
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
71
        du_lsu_store_dat, du_lsu_load_dat,
72 141 marcus.erl
        abort_mvspr, abort_ex,
73 10 unneback
 
74
        // Data interface
75
        dc_en,
76 258 julius
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
77
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
78
        sb_en, dmmu_en, dc_no_writethrough,
79 10 unneback
 
80 141 marcus.erl
        // SR Interface
81
        boot_adr_sel_i,
82
 
83 10 unneback
        // Interrupt & tick exceptions
84
        sig_int, sig_tick,
85
 
86
        // SPR interface
87
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
88 258 julius
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
89 10 unneback
);
90
 
91
parameter dw = `OR1200_OPERAND_WIDTH;
92
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
93 813 olof
parameter boot_adr = `OR1200_BOOT_ADR;
94 10 unneback
 
95
//
96
// I/O ports
97
//
98
 
99
//
100
// Clk & Rst
101
//
102
input                           clk;
103
input                           rst;
104
 
105
//
106
// Insn (IC) interface
107
//
108
output                          ic_en;
109
output  [31:0]                   icpu_adr_o;
110
output                          icpu_cycstb_o;
111
output  [3:0]                    icpu_sel_o;
112
output  [3:0]                    icpu_tag_o;
113
input   [31:0]                   icpu_dat_i;
114
input                           icpu_ack_i;
115
input                           icpu_rty_i;
116
input                           icpu_err_i;
117
input   [31:0]                   icpu_adr_i;
118
input   [3:0]                    icpu_tag_i;
119
 
120
//
121
// Insn (IMMU) interface
122
//
123
output                          immu_en;
124
 
125
//
126
// Debug interface
127
//
128 141 marcus.erl
output                          id_void;
129
output  [31:0]                   id_insn;
130
output                          ex_void;
131 10 unneback
output  [31:0]                   ex_insn;
132
output                          ex_freeze;
133 141 marcus.erl
output  [31:0]                   wb_insn;
134
output                          wb_freeze;
135 10 unneback
output  [31:0]                   id_pc;
136 141 marcus.erl
output  [31:0]                   ex_pc;
137
output  [31:0]                   wb_pc;
138
output                          ex_flushpipe;
139 10 unneback
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
140
 
141
input                           du_stall;
142
input   [dw-1:0]         du_addr;
143
input   [dw-1:0]         du_dat_du;
144
input                           du_read;
145
input                           du_write;
146
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
147 141 marcus.erl
input   [24:0]                   du_dmr1;
148 10 unneback
input                           du_hwbkpt;
149 141 marcus.erl
input                           du_hwbkpt_ls_r;
150 185 julius
output  [13:0]                   du_except_trig;
151
output  [13:0]                   du_except_stop;
152 10 unneback
output  [dw-1:0]         du_dat_cpu;
153
output  [dw-1:0]         rf_dataw;
154 141 marcus.erl
output  [dw-1:0]         du_lsu_store_dat;
155
output  [dw-1:0]         du_lsu_load_dat;
156 10 unneback
 
157
//
158
// Data (DC) interface
159
//
160
output  [31:0]                   dcpu_adr_o;
161
output                          dcpu_cycstb_o;
162
output                          dcpu_we_o;
163
output  [3:0]                    dcpu_sel_o;
164
output  [3:0]                    dcpu_tag_o;
165
output  [31:0]                   dcpu_dat_o;
166
input   [31:0]                   dcpu_dat_i;
167
input                           dcpu_ack_i;
168
input                           dcpu_rty_i;
169
input                           dcpu_err_i;
170
input   [3:0]                    dcpu_tag_i;
171
output                          dc_en;
172 258 julius
output                          dc_no_writethrough;
173
 
174 10 unneback
//
175
// Data (DMMU) interface
176
//
177 141 marcus.erl
output                          sb_en;
178 10 unneback
output                          dmmu_en;
179 141 marcus.erl
output                          abort_ex;
180
output                          abort_mvspr;
181 10 unneback
 
182
//
183 141 marcus.erl
// SR Interface 
184
//
185
input                           boot_adr_sel_i;
186
 
187
//
188 10 unneback
// SPR interface
189
//
190
output                          supv;
191
input   [dw-1:0]         spr_dat_pic;
192
input   [dw-1:0]         spr_dat_tt;
193
input   [dw-1:0]         spr_dat_pm;
194
input   [dw-1:0]         spr_dat_dmmu;
195
input   [dw-1:0]         spr_dat_immu;
196
input   [dw-1:0]         spr_dat_du;
197
output  [dw-1:0]         spr_addr;
198
output  [dw-1:0]         spr_dat_cpu;
199
output  [dw-1:0]         spr_dat_npc;
200
output  [31:0]                   spr_cs;
201
output                          spr_we;
202 258 julius
input                           mtspr_dc_done;
203
 
204 10 unneback
//
205
// Interrupt exceptions
206
//
207
input                           sig_int;
208
input                           sig_tick;
209
 
210
//
211
// Internal wires
212
//
213
wire    [31:0]                   if_insn;
214 141 marcus.erl
wire                            saving_if_insn;
215 10 unneback
wire    [31:0]                   if_pc;
216
wire    [aw-1:0]         rf_addrw;
217
wire    [aw-1:0]                 rf_addra;
218
wire    [aw-1:0]                 rf_addrb;
219
wire                            rf_rda;
220
wire                            rf_rdb;
221 141 marcus.erl
wire    [dw-1:0]         id_simm;
222
wire    [dw-1:2]                id_branch_addrtarget;
223
wire    [dw-1:2]                ex_branch_addrtarget;
224 10 unneback
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
225 401 julius
wire    [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
226 10 unneback
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
227 141 marcus.erl
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
228 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
229 141 marcus.erl
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
230 10 unneback
wire                            genpc_freeze;
231
wire                            if_freeze;
232
wire                            id_freeze;
233
wire                            ex_freeze;
234
wire                            wb_freeze;
235
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
236
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
237
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
238 185 julius
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
239 10 unneback
wire    [dw-1:0]         rf_dataw;
240
wire    [dw-1:0]         rf_dataa;
241
wire    [dw-1:0]         rf_datab;
242 141 marcus.erl
wire    [dw-1:0]         muxed_a;
243 10 unneback
wire    [dw-1:0]         muxed_b;
244
wire    [dw-1:0]         wb_forw;
245
wire                            wbforw_valid;
246
wire    [dw-1:0]         operand_a;
247
wire    [dw-1:0]         operand_b;
248
wire    [dw-1:0]         alu_dataout;
249
wire    [dw-1:0]         lsu_dataout;
250
wire    [dw-1:0]         sprs_dataout;
251 185 julius
wire    [dw-1:0]         fpu_dataout;
252 258 julius
wire                            fpu_done;
253 141 marcus.erl
wire    [31:0]                   ex_simm;
254 10 unneback
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
255 258 julius
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
256 10 unneback
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
257
wire    [4:0]                    cust5_op;
258
wire    [5:0]                    cust5_limm;
259 141 marcus.erl
wire                            if_flushpipe;
260
wire                            id_flushpipe;
261
wire                            ex_flushpipe;
262
wire                            wb_flushpipe;
263 10 unneback
wire                            extend_flush;
264 141 marcus.erl
wire                            ex_branch_taken;
265 10 unneback
wire                            flag;
266
wire                            flagforw;
267
wire                            flag_we;
268 185 julius
wire                            flagforw_alu;
269 141 marcus.erl
wire                            flag_we_alu;
270 185 julius
wire                            flagforw_fpu;
271
wire                            flag_we_fpu;
272 10 unneback
wire                            carry;
273
wire                            cyforw;
274 141 marcus.erl
wire                            cy_we_alu;
275 642 julius
wire                            ovforw;
276
wire                            ov_we_alu;
277
wire                            ovforw_mult_mac;
278
wire                            ov_we_mult_mac;
279 141 marcus.erl
wire                            cy_we_rf;
280 10 unneback
wire                            lsu_stall;
281
wire                            epcr_we;
282
wire                            eear_we;
283
wire                            esr_we;
284
wire                            pc_we;
285
wire    [31:0]                   epcr;
286
wire    [31:0]                   eear;
287
wire    [`OR1200_SR_WIDTH-1:0]   esr;
288 185 julius
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
289 258 julius
wire                            fpcsr_we;
290 10 unneback
wire                            sr_we;
291
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
292
wire    [`OR1200_SR_WIDTH-1:0]   sr;
293 808 julius
wire                            dsx;
294 141 marcus.erl
wire                            except_flushpipe;
295 10 unneback
wire                            except_start;
296
wire                            except_started;
297 185 julius
wire                            fpu_except_started;
298 10 unneback
wire    [31:0]                   wb_insn;
299
wire                            sig_syscall;
300
wire                            sig_trap;
301 642 julius
wire                            sig_range;
302 185 julius
wire                            sig_fp;
303 10 unneback
wire    [31:0]                   spr_dat_cfgr;
304
wire    [31:0]                   spr_dat_rf;
305
wire    [31:0]                  spr_dat_npc;
306
wire    [31:0]                   spr_dat_ppc;
307
wire    [31:0]                   spr_dat_mac;
308 258 julius
wire [31:0]                      spr_dat_fpu;
309
wire                            mtspr_done;
310 10 unneback
wire                            force_dslot_fetch;
311
wire                            no_more_dslot;
312
wire                            ex_void;
313 141 marcus.erl
wire                            ex_spr_read;
314
wire                            ex_spr_write;
315 10 unneback
wire                            if_stall;
316
wire                            id_macrc_op;
317
wire                            ex_macrc_op;
318 141 marcus.erl
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
319 10 unneback
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
320
wire    [31:0]                   mult_mac_result;
321 481 julius
wire                            mult_mac_stall;
322 185 julius
wire    [13:0]                   except_trig;
323
wire    [13:0]                   except_stop;
324 10 unneback
wire                            genpc_refetch;
325
wire                            rfe;
326
wire                            lsu_unstall;
327
wire                            except_align;
328
wire                            except_dtlbmiss;
329
wire                            except_dmmufault;
330
wire                            except_illegal;
331
wire                            except_itlbmiss;
332
wire                            except_immufault;
333
wire                            except_ibuserr;
334
wire                            except_dbuserr;
335
wire                            abort_ex;
336 141 marcus.erl
wire                            abort_mvspr;
337 10 unneback
 
338
//
339
// Send exceptions to Debug Unit
340
//
341 141 marcus.erl
assign du_except_trig = except_trig;
342
assign du_except_stop = except_stop;
343
assign du_lsu_store_dat = operand_b;
344
assign du_lsu_load_dat  = lsu_dataout;
345 10 unneback
 
346
//
347
// Data cache enable
348
//
349 141 marcus.erl
`ifdef OR1200_NO_DC
350
assign dc_en = 1'b0;
351
`else
352 258 julius
   assign dc_en = sr[`OR1200_SR_DCE];
353 141 marcus.erl
`endif
354 10 unneback
 
355
//
356
// Instruction cache enable
357
//
358 141 marcus.erl
`ifdef OR1200_NO_IC
359
assign ic_en = 1'b0;
360
`else
361 10 unneback
assign ic_en = sr[`OR1200_SR_ICE];
362 141 marcus.erl
`endif
363 10 unneback
 
364
//
365 141 marcus.erl
// SB enable
366
//
367
`ifdef OR1200_SB_IMPLEMENTED
368
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
369
`else
370
assign sb_en = 1'b0;
371
`endif
372
 
373
//
374 10 unneback
// DMMU enable
375
//
376 141 marcus.erl
`ifdef OR1200_NO_DMMU
377
assign dmmu_en = 1'b0;
378
`else
379 10 unneback
assign dmmu_en = sr[`OR1200_SR_DME];
380 141 marcus.erl
`endif
381 10 unneback
 
382
//
383
// IMMU enable
384
//
385 141 marcus.erl
`ifdef OR1200_NO_IMMU
386
assign immu_en = 1'b0;
387
`else
388
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
389
`endif
390 10 unneback
 
391
//
392
// SUPV bit
393
//
394
assign supv = sr[`OR1200_SR_SM];
395
 
396
//
397 141 marcus.erl
// FLAG write enable
398
//
399 185 julius
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
400
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
401 141 marcus.erl
 
402
//
403 642 julius
// Flag for any MTSPR instructions, that must block execution, to indicate done
404 258 julius
//
405
assign mtspr_done = mtspr_dc_done;
406 642 julius
 
407
//
408
// Range exception
409
//
410
assign sig_range = sr[`OR1200_SR_OV];
411 258 julius
 
412
 
413 642 julius
 
414 258 julius
//
415 10 unneback
// Instantiation of instruction fetch block
416
//
417 813 olof
or1200_genpc #(.boot_adr(boot_adr)) or1200_genpc(
418 10 unneback
        .clk(clk),
419
        .rst(rst),
420
        .icpu_adr_o(icpu_adr_o),
421
        .icpu_cycstb_o(icpu_cycstb_o),
422
        .icpu_sel_o(icpu_sel_o),
423
        .icpu_tag_o(icpu_tag_o),
424
        .icpu_rty_i(icpu_rty_i),
425
        .icpu_adr_i(icpu_adr_i),
426
 
427 141 marcus.erl
        .pre_branch_op(pre_branch_op),
428 10 unneback
        .branch_op(branch_op),
429
        .except_type(except_type),
430
        .except_start(except_start),
431
        .except_prefix(sr[`OR1200_SR_EPH]),
432 141 marcus.erl
        .id_branch_addrtarget(id_branch_addrtarget),
433
        .ex_branch_addrtarget(ex_branch_addrtarget),
434
        .muxed_b(muxed_b),
435
        .operand_b(operand_b),
436 10 unneback
        .flag(flag),
437 141 marcus.erl
        .flagforw(flagforw),
438
        .ex_branch_taken(ex_branch_taken),
439 10 unneback
        .epcr(epcr),
440
        .spr_dat_i(spr_dat_cpu),
441
        .spr_pc_we(pc_we),
442
        .genpc_refetch(genpc_refetch),
443
        .genpc_freeze(genpc_freeze),
444
        .no_more_dslot(no_more_dslot)
445
);
446
 
447
//
448
// Instantiation of instruction fetch block
449
//
450
or1200_if or1200_if(
451
        .clk(clk),
452
        .rst(rst),
453
        .icpu_dat_i(icpu_dat_i),
454
        .icpu_ack_i(icpu_ack_i),
455
        .icpu_err_i(icpu_err_i),
456
        .icpu_adr_i(icpu_adr_i),
457
        .icpu_tag_i(icpu_tag_i),
458
 
459
        .if_freeze(if_freeze),
460
        .if_insn(if_insn),
461
        .if_pc(if_pc),
462 141 marcus.erl
        .saving_if_insn(saving_if_insn),
463
        .if_flushpipe(if_flushpipe),
464 10 unneback
        .if_stall(if_stall),
465
        .no_more_dslot(no_more_dslot),
466
        .genpc_refetch(genpc_refetch),
467
        .rfe(rfe),
468
        .except_itlbmiss(except_itlbmiss),
469
        .except_immufault(except_immufault),
470
        .except_ibuserr(except_ibuserr)
471
);
472
 
473
//
474
// Instantiation of instruction decode/control logic
475
//
476
or1200_ctrl or1200_ctrl(
477
        .clk(clk),
478
        .rst(rst),
479
        .id_freeze(id_freeze),
480
        .ex_freeze(ex_freeze),
481
        .wb_freeze(wb_freeze),
482 141 marcus.erl
        .if_flushpipe(if_flushpipe),
483
        .id_flushpipe(id_flushpipe),
484
        .ex_flushpipe(ex_flushpipe),
485
        .wb_flushpipe(wb_flushpipe),
486
        .extend_flush(extend_flush),
487
        .except_flushpipe(except_flushpipe),
488
        .abort_mvspr(abort_mvspr),
489 10 unneback
        .if_insn(if_insn),
490 141 marcus.erl
        .id_insn(id_insn),
491 10 unneback
        .ex_insn(ex_insn),
492 141 marcus.erl
        .id_branch_op(pre_branch_op),
493
        .ex_branch_op(branch_op),
494
        .ex_branch_taken(ex_branch_taken),
495 10 unneback
        .rf_addra(rf_addra),
496
        .rf_addrb(rf_addrb),
497
        .rf_rda(rf_rda),
498
        .rf_rdb(rf_rdb),
499
        .alu_op(alu_op),
500 401 julius
        .alu_op2(alu_op2),
501 10 unneback
        .mac_op(mac_op),
502
        .comp_op(comp_op),
503
        .rf_addrw(rf_addrw),
504
        .rfwb_op(rfwb_op),
505 185 julius
        .fpu_op(fpu_op),
506 141 marcus.erl
        .pc_we(pc_we),
507 10 unneback
        .wb_insn(wb_insn),
508 141 marcus.erl
        .id_simm(id_simm),
509
        .id_branch_addrtarget(id_branch_addrtarget),
510
        .ex_branch_addrtarget(ex_branch_addrtarget),
511
        .ex_simm(ex_simm),
512 10 unneback
        .sel_a(sel_a),
513
        .sel_b(sel_b),
514 141 marcus.erl
        .id_lsu_op(id_lsu_op),
515 10 unneback
        .cust5_op(cust5_op),
516
        .cust5_limm(cust5_limm),
517 141 marcus.erl
        .id_pc(id_pc),
518
        .ex_pc(ex_pc),
519 10 unneback
        .multicycle(multicycle),
520 258 julius
        .wait_on(wait_on),
521 10 unneback
        .wbforw_valid(wbforw_valid),
522
        .sig_syscall(sig_syscall),
523
        .sig_trap(sig_trap),
524
        .force_dslot_fetch(force_dslot_fetch),
525
        .no_more_dslot(no_more_dslot),
526 141 marcus.erl
        .id_void(id_void),
527 10 unneback
        .ex_void(ex_void),
528 141 marcus.erl
        .ex_spr_read(ex_spr_read),
529
        .ex_spr_write(ex_spr_write),
530
        .id_mac_op(id_mac_op),
531 10 unneback
        .id_macrc_op(id_macrc_op),
532
        .ex_macrc_op(ex_macrc_op),
533
        .rfe(rfe),
534
        .du_hwbkpt(du_hwbkpt),
535 258 julius
        .except_illegal(except_illegal),
536
        .dc_no_writethrough(dc_no_writethrough)
537 10 unneback
);
538
 
539
//
540
// Instantiation of register file
541
//
542
or1200_rf or1200_rf(
543
        .clk(clk),
544
        .rst(rst),
545 141 marcus.erl
        .cy_we_i(cy_we_alu),
546
        .cy_we_o(cy_we_rf),
547 10 unneback
        .supv(sr[`OR1200_SR_SM]),
548
        .wb_freeze(wb_freeze),
549
        .addrw(rf_addrw),
550
        .dataw(rf_dataw),
551
        .id_freeze(id_freeze),
552
        .we(rfwb_op[0]),
553 141 marcus.erl
        .flushpipe(wb_flushpipe),
554 10 unneback
        .addra(rf_addra),
555
        .rda(rf_rda),
556
        .dataa(rf_dataa),
557
        .addrb(rf_addrb),
558
        .rdb(rf_rdb),
559
        .datab(rf_datab),
560
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
561
        .spr_write(spr_we),
562
        .spr_addr(spr_addr),
563
        .spr_dat_i(spr_dat_cpu),
564 258 julius
        .spr_dat_o(spr_dat_rf),
565
        .du_read(du_read)
566 10 unneback
);
567
 
568
//
569
// Instantiation of operand muxes
570
//
571
or1200_operandmuxes or1200_operandmuxes(
572
        .clk(clk),
573
        .rst(rst),
574
        .id_freeze(id_freeze),
575
        .ex_freeze(ex_freeze),
576
        .rf_dataa(rf_dataa),
577
        .rf_datab(rf_datab),
578
        .ex_forw(rf_dataw),
579
        .wb_forw(wb_forw),
580 141 marcus.erl
        .simm(id_simm),
581 10 unneback
        .sel_a(sel_a),
582
        .sel_b(sel_b),
583
        .operand_a(operand_a),
584
        .operand_b(operand_b),
585 141 marcus.erl
        .muxed_a(muxed_a),
586 10 unneback
        .muxed_b(muxed_b)
587
);
588
 
589
//
590
// Instantiation of CPU's ALU
591
//
592
or1200_alu or1200_alu(
593
        .a(operand_a),
594
        .b(operand_b),
595
        .mult_mac_result(mult_mac_result),
596
        .macrc_op(ex_macrc_op),
597
        .alu_op(alu_op),
598 401 julius
        .alu_op2(alu_op2),
599 10 unneback
        .comp_op(comp_op),
600
        .cust5_op(cust5_op),
601
        .cust5_limm(cust5_limm),
602
        .result(alu_dataout),
603 185 julius
        .flagforw(flagforw_alu),
604 141 marcus.erl
        .flag_we(flag_we_alu),
605 10 unneback
        .cyforw(cyforw),
606 141 marcus.erl
        .cy_we(cy_we_alu),
607 642 julius
        .ovforw(ovforw),
608
        .ov_we(ov_we_alu),
609 141 marcus.erl
        .flag(flag),
610 10 unneback
        .carry(carry)
611
);
612
 
613 185 julius
 
614 10 unneback
//
615 185 julius
// FPU's exception is being dealt with
616
//    
617
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
618
 
619 10 unneback
//
620 185 julius
// Instantiation of FPU
621
//
622
or1200_fpu or1200_fpu(
623
        .clk(clk),
624
        .rst(rst),
625
        .ex_freeze(ex_freeze),
626
        .a(operand_a),
627
        .b(operand_b),
628
        .fpu_op(fpu_op),
629
        .result(fpu_dataout),
630 258 julius
        .done(fpu_done),
631 185 julius
        .flagforw(flagforw_fpu),
632
        .flag_we(flag_we_fpu),
633
        .sig_fp(sig_fp),
634 258 julius
        .except_started(fpu_except_started),
635 185 julius
        .fpcsr_we(fpcsr_we),
636 258 julius
        .fpcsr(fpcsr),
637 185 julius
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
638
        .spr_write(spr_we),
639
        .spr_addr(spr_addr),
640
        .spr_dat_i(spr_dat_cpu),
641
        .spr_dat_o(spr_dat_fpu)
642
);
643
 
644
 
645
//
646
// Instantiation of CPU's multiply unit
647
//
648 10 unneback
or1200_mult_mac or1200_mult_mac(
649
        .clk(clk),
650
        .rst(rst),
651
        .ex_freeze(ex_freeze),
652
        .id_macrc_op(id_macrc_op),
653
        .macrc_op(ex_macrc_op),
654
        .a(operand_a),
655
        .b(operand_b),
656
        .mac_op(mac_op),
657
        .alu_op(alu_op),
658
        .result(mult_mac_result),
659 642 julius
        .ovforw(ovforw_mult_mac),
660
        .ov_we(ov_we_mult_mac),
661 481 julius
        .mult_mac_stall(mult_mac_stall),
662 10 unneback
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
663
        .spr_write(spr_we),
664
        .spr_addr(spr_addr),
665
        .spr_dat_i(spr_dat_cpu),
666
        .spr_dat_o(spr_dat_mac)
667
);
668
 
669
//
670
// Instantiation of CPU's SPRS block
671
//
672
or1200_sprs or1200_sprs(
673
        .clk(clk),
674
        .rst(rst),
675
        .addrbase(operand_a),
676 141 marcus.erl
        .addrofs(ex_simm[15:0]),
677 10 unneback
        .dat_i(operand_b),
678 141 marcus.erl
        .ex_spr_read(ex_spr_read),
679
        .ex_spr_write(ex_spr_write),
680 10 unneback
        .flagforw(flagforw),
681
        .flag_we(flag_we),
682
        .flag(flag),
683
        .cyforw(cyforw),
684 141 marcus.erl
        .cy_we(cy_we_rf),
685 10 unneback
        .carry(carry),
686 642 julius
        .ovforw(ovforw | ovforw_mult_mac),
687
        .ov_we(ov_we_alu | ov_we_mult_mac),
688 10 unneback
        .to_wbmux(sprs_dataout),
689
 
690
        .du_addr(du_addr),
691
        .du_dat_du(du_dat_du),
692
        .du_read(du_read),
693
        .du_write(du_write),
694
        .du_dat_cpu(du_dat_cpu),
695 141 marcus.erl
        .boot_adr_sel_i(boot_adr_sel_i),
696 10 unneback
        .spr_addr(spr_addr),
697
        .spr_dat_pic(spr_dat_pic),
698
        .spr_dat_tt(spr_dat_tt),
699
        .spr_dat_pm(spr_dat_pm),
700
        .spr_dat_cfgr(spr_dat_cfgr),
701
        .spr_dat_rf(spr_dat_rf),
702
        .spr_dat_npc(spr_dat_npc),
703
        .spr_dat_ppc(spr_dat_ppc),
704
        .spr_dat_mac(spr_dat_mac),
705
        .spr_dat_dmmu(spr_dat_dmmu),
706
        .spr_dat_immu(spr_dat_immu),
707
        .spr_dat_du(spr_dat_du),
708
        .spr_dat_o(spr_dat_cpu),
709
        .spr_cs(spr_cs),
710
        .spr_we(spr_we),
711
 
712
        .epcr_we(epcr_we),
713
        .eear_we(eear_we),
714
        .esr_we(esr_we),
715
        .pc_we(pc_we),
716
        .epcr(epcr),
717
        .eear(eear),
718
        .esr(esr),
719
        .except_started(except_started),
720
 
721 185 julius
        .fpcsr(fpcsr),
722 258 julius
        .fpcsr_we(fpcsr_we),
723 185 julius
        .spr_dat_fpu(spr_dat_fpu),
724
 
725 10 unneback
        .sr_we(sr_we),
726
        .to_sr(to_sr),
727
        .sr(sr),
728 808 julius
        .branch_op(branch_op),
729
        .dsx(dsx)
730 10 unneback
);
731
 
732
//
733
// Instantiation of load/store unit
734
//
735
or1200_lsu or1200_lsu(
736 141 marcus.erl
        .clk(clk),
737
        .rst(rst),
738
        .id_addrbase(muxed_a),
739
        .id_addrofs(id_simm),
740
        .ex_addrbase(operand_a),
741
        .ex_addrofs(ex_simm),
742
        .id_lsu_op(id_lsu_op),
743 10 unneback
        .lsu_datain(operand_b),
744
        .lsu_dataout(lsu_dataout),
745
        .lsu_stall(lsu_stall),
746
        .lsu_unstall(lsu_unstall),
747 141 marcus.erl
        .du_stall(du_stall),
748 10 unneback
        .except_align(except_align),
749
        .except_dtlbmiss(except_dtlbmiss),
750
        .except_dmmufault(except_dmmufault),
751
        .except_dbuserr(except_dbuserr),
752 141 marcus.erl
        .id_freeze(id_freeze),
753
        .ex_freeze(ex_freeze),
754
        .flushpipe(ex_flushpipe),
755 10 unneback
 
756
        .dcpu_adr_o(dcpu_adr_o),
757
        .dcpu_cycstb_o(dcpu_cycstb_o),
758
        .dcpu_we_o(dcpu_we_o),
759
        .dcpu_sel_o(dcpu_sel_o),
760
        .dcpu_tag_o(dcpu_tag_o),
761
        .dcpu_dat_o(dcpu_dat_o),
762
        .dcpu_dat_i(dcpu_dat_i),
763
        .dcpu_ack_i(dcpu_ack_i),
764
        .dcpu_rty_i(dcpu_rty_i),
765
        .dcpu_err_i(dcpu_err_i),
766
        .dcpu_tag_i(dcpu_tag_i)
767
);
768
 
769
//
770
// Instantiation of write-back muxes
771
//
772
or1200_wbmux or1200_wbmux(
773
        .clk(clk),
774
        .rst(rst),
775
        .wb_freeze(wb_freeze),
776
        .rfwb_op(rfwb_op),
777
        .muxin_a(alu_dataout),
778
        .muxin_b(lsu_dataout),
779
        .muxin_c(sprs_dataout),
780 141 marcus.erl
        .muxin_d(ex_pc),
781 185 julius
        .muxin_e(fpu_dataout),
782 10 unneback
        .muxout(rf_dataw),
783
        .muxreg(wb_forw),
784
        .muxreg_valid(wbforw_valid)
785
);
786
 
787
//
788
// Instantiation of freeze logic
789
//
790
or1200_freeze or1200_freeze(
791
        .clk(clk),
792
        .rst(rst),
793
        .multicycle(multicycle),
794 258 julius
        .wait_on(wait_on),
795
        .fpu_done(fpu_done),
796
        .mtspr_done(mtspr_done),
797 141 marcus.erl
        .flushpipe(wb_flushpipe),
798 10 unneback
        .extend_flush(extend_flush),
799
        .lsu_stall(lsu_stall),
800
        .if_stall(if_stall),
801
        .lsu_unstall(lsu_unstall),
802
        .force_dslot_fetch(force_dslot_fetch),
803
        .abort_ex(abort_ex),
804
        .du_stall(du_stall),
805 481 julius
        .mac_stall(mult_mac_stall),
806 141 marcus.erl
        .saving_if_insn(saving_if_insn),
807 10 unneback
        .genpc_freeze(genpc_freeze),
808
        .if_freeze(if_freeze),
809
        .id_freeze(id_freeze),
810
        .ex_freeze(ex_freeze),
811
        .wb_freeze(wb_freeze),
812
        .icpu_ack_i(icpu_ack_i),
813
        .icpu_err_i(icpu_err_i)
814
);
815
 
816
//
817
// Instantiation of exception block
818
//
819
or1200_except or1200_except(
820
        .clk(clk),
821
        .rst(rst),
822
        .sig_ibuserr(except_ibuserr),
823
        .sig_dbuserr(except_dbuserr),
824
        .sig_illegal(except_illegal),
825
        .sig_align(except_align),
826 642 julius
        .sig_range(sig_range),
827 10 unneback
        .sig_dtlbmiss(except_dtlbmiss),
828
        .sig_dmmufault(except_dmmufault),
829
        .sig_int(sig_int),
830
        .sig_syscall(sig_syscall),
831
        .sig_trap(sig_trap),
832
        .sig_itlbmiss(except_itlbmiss),
833
        .sig_immufault(except_immufault),
834
        .sig_tick(sig_tick),
835 185 julius
        .sig_fp(sig_fp),
836 258 julius
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
837 141 marcus.erl
        .ex_branch_taken(ex_branch_taken),
838 10 unneback
        .icpu_ack_i(icpu_ack_i),
839
        .icpu_err_i(icpu_err_i),
840
        .dcpu_ack_i(dcpu_ack_i),
841
        .dcpu_err_i(dcpu_err_i),
842
        .genpc_freeze(genpc_freeze),
843
        .id_freeze(id_freeze),
844
        .ex_freeze(ex_freeze),
845
        .wb_freeze(wb_freeze),
846
        .if_stall(if_stall),
847
        .if_pc(if_pc),
848
        .id_pc(id_pc),
849 141 marcus.erl
        .ex_pc(ex_pc),
850
        .wb_pc(wb_pc),
851
        .id_flushpipe(id_flushpipe),
852
        .ex_flushpipe(ex_flushpipe),
853 10 unneback
        .extend_flush(extend_flush),
854 141 marcus.erl
        .except_flushpipe(except_flushpipe),
855
        .abort_mvspr(abort_mvspr),
856 10 unneback
        .except_type(except_type),
857
        .except_start(except_start),
858
        .except_started(except_started),
859
        .except_stop(except_stop),
860 141 marcus.erl
        .except_trig(except_trig),
861 10 unneback
        .ex_void(ex_void),
862
        .spr_dat_ppc(spr_dat_ppc),
863
        .spr_dat_npc(spr_dat_npc),
864
 
865 141 marcus.erl
        .datain(spr_dat_cpu),
866
        .branch_op(branch_op),
867 10 unneback
        .du_dsr(du_dsr),
868 141 marcus.erl
        .du_dmr1(du_dmr1),
869
        .du_hwbkpt(du_hwbkpt),
870
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
871 10 unneback
        .epcr_we(epcr_we),
872
        .eear_we(eear_we),
873
        .esr_we(esr_we),
874
        .pc_we(pc_we),
875
        .epcr(epcr),
876
        .eear(eear),
877
        .esr(esr),
878
 
879
        .lsu_addr(dcpu_adr_o),
880
        .sr_we(sr_we),
881
        .to_sr(to_sr),
882
        .sr(sr),
883 808 julius
        .abort_ex(abort_ex),
884
        .dsx(dsx)
885 10 unneback
);
886
 
887
//
888
// Instantiation of configuration registers
889
//
890
or1200_cfgr or1200_cfgr(
891
        .spr_addr(spr_addr),
892
        .spr_dat_o(spr_dat_cfgr)
893
);
894
 
895
endmodule

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