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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Blame information for rev 868

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66 141 marcus.erl
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69 859 olof
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop, du_flush_pipe,
70 258 julius
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
71
        du_lsu_store_dat, du_lsu_load_dat,
72 141 marcus.erl
        abort_mvspr, abort_ex,
73 10 unneback
 
74
        // Data interface
75
        dc_en,
76 258 julius
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
77
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
78
        sb_en, dmmu_en, dc_no_writethrough,
79 10 unneback
 
80 141 marcus.erl
        // SR Interface
81
        boot_adr_sel_i,
82
 
83 10 unneback
        // Interrupt & tick exceptions
84
        sig_int, sig_tick,
85
 
86
        // SPR interface
87
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
88 258 julius
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
89 10 unneback
);
90
 
91
parameter dw = `OR1200_OPERAND_WIDTH;
92
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
93 813 olof
parameter boot_adr = `OR1200_BOOT_ADR;
94 10 unneback
 
95
//
96
// I/O ports
97
//
98
 
99
//
100
// Clk & Rst
101
//
102
input                           clk;
103
input                           rst;
104
 
105
//
106
// Insn (IC) interface
107
//
108
output                          ic_en;
109
output  [31:0]                   icpu_adr_o;
110
output                          icpu_cycstb_o;
111
output  [3:0]                    icpu_sel_o;
112
output  [3:0]                    icpu_tag_o;
113
input   [31:0]                   icpu_dat_i;
114
input                           icpu_ack_i;
115
input                           icpu_rty_i;
116
input                           icpu_err_i;
117
input   [31:0]                   icpu_adr_i;
118
input   [3:0]                    icpu_tag_i;
119
 
120
//
121
// Insn (IMMU) interface
122
//
123
output                          immu_en;
124
 
125
//
126
// Debug interface
127
//
128 141 marcus.erl
output                          id_void;
129
output  [31:0]                   id_insn;
130
output                          ex_void;
131 10 unneback
output  [31:0]                   ex_insn;
132
output                          ex_freeze;
133 141 marcus.erl
output  [31:0]                   wb_insn;
134
output                          wb_freeze;
135 10 unneback
output  [31:0]                   id_pc;
136 141 marcus.erl
output  [31:0]                   ex_pc;
137
output  [31:0]                   wb_pc;
138
output                          ex_flushpipe;
139 10 unneback
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
140
 
141
input                           du_stall;
142
input   [dw-1:0]         du_addr;
143
input   [dw-1:0]         du_dat_du;
144
input                           du_read;
145
input                           du_write;
146
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
147 141 marcus.erl
input   [24:0]                   du_dmr1;
148 10 unneback
input                           du_hwbkpt;
149 141 marcus.erl
input                           du_hwbkpt_ls_r;
150 185 julius
output  [13:0]                   du_except_trig;
151
output  [13:0]                   du_except_stop;
152 10 unneback
output  [dw-1:0]         du_dat_cpu;
153
output  [dw-1:0]         rf_dataw;
154 141 marcus.erl
output  [dw-1:0]         du_lsu_store_dat;
155
output  [dw-1:0]         du_lsu_load_dat;
156 859 olof
input                           du_flush_pipe;
157 10 unneback
 
158
//
159
// Data (DC) interface
160
//
161
output  [31:0]                   dcpu_adr_o;
162
output                          dcpu_cycstb_o;
163
output                          dcpu_we_o;
164
output  [3:0]                    dcpu_sel_o;
165
output  [3:0]                    dcpu_tag_o;
166
output  [31:0]                   dcpu_dat_o;
167
input   [31:0]                   dcpu_dat_i;
168
input                           dcpu_ack_i;
169
input                           dcpu_rty_i;
170
input                           dcpu_err_i;
171
input   [3:0]                    dcpu_tag_i;
172
output                          dc_en;
173 258 julius
output                          dc_no_writethrough;
174
 
175 10 unneback
//
176
// Data (DMMU) interface
177
//
178 141 marcus.erl
output                          sb_en;
179 10 unneback
output                          dmmu_en;
180 141 marcus.erl
output                          abort_ex;
181
output                          abort_mvspr;
182 10 unneback
 
183
//
184 141 marcus.erl
// SR Interface 
185
//
186
input                           boot_adr_sel_i;
187
 
188
//
189 10 unneback
// SPR interface
190
//
191
output                          supv;
192
input   [dw-1:0]         spr_dat_pic;
193
input   [dw-1:0]         spr_dat_tt;
194
input   [dw-1:0]         spr_dat_pm;
195
input   [dw-1:0]         spr_dat_dmmu;
196
input   [dw-1:0]         spr_dat_immu;
197
input   [dw-1:0]         spr_dat_du;
198
output  [dw-1:0]         spr_addr;
199
output  [dw-1:0]         spr_dat_cpu;
200
output  [dw-1:0]         spr_dat_npc;
201
output  [31:0]                   spr_cs;
202
output                          spr_we;
203 258 julius
input                           mtspr_dc_done;
204
 
205 10 unneback
//
206
// Interrupt exceptions
207
//
208
input                           sig_int;
209
input                           sig_tick;
210
 
211
//
212
// Internal wires
213
//
214
wire    [31:0]                   if_insn;
215 141 marcus.erl
wire                            saving_if_insn;
216 10 unneback
wire    [31:0]                   if_pc;
217
wire    [aw-1:0]         rf_addrw;
218
wire    [aw-1:0]                 rf_addra;
219
wire    [aw-1:0]                 rf_addrb;
220
wire                            rf_rda;
221
wire                            rf_rdb;
222 141 marcus.erl
wire    [dw-1:0]         id_simm;
223
wire    [dw-1:2]                id_branch_addrtarget;
224
wire    [dw-1:2]                ex_branch_addrtarget;
225 10 unneback
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
226 401 julius
wire    [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
227 10 unneback
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
228 141 marcus.erl
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
229 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
230 141 marcus.erl
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
231 10 unneback
wire                            genpc_freeze;
232
wire                            if_freeze;
233
wire                            id_freeze;
234
wire                            ex_freeze;
235
wire                            wb_freeze;
236
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
237
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
238
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
239 185 julius
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
240 10 unneback
wire    [dw-1:0]         rf_dataw;
241
wire    [dw-1:0]         rf_dataa;
242
wire    [dw-1:0]         rf_datab;
243 141 marcus.erl
wire    [dw-1:0]         muxed_a;
244 10 unneback
wire    [dw-1:0]         muxed_b;
245
wire    [dw-1:0]         wb_forw;
246
wire                            wbforw_valid;
247
wire    [dw-1:0]         operand_a;
248
wire    [dw-1:0]         operand_b;
249
wire    [dw-1:0]         alu_dataout;
250
wire    [dw-1:0]         lsu_dataout;
251
wire    [dw-1:0]         sprs_dataout;
252 185 julius
wire    [dw-1:0]         fpu_dataout;
253 258 julius
wire                            fpu_done;
254 141 marcus.erl
wire    [31:0]                   ex_simm;
255 10 unneback
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
256 258 julius
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
257 10 unneback
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
258
wire    [4:0]                    cust5_op;
259
wire    [5:0]                    cust5_limm;
260 141 marcus.erl
wire                            if_flushpipe;
261
wire                            id_flushpipe;
262
wire                            ex_flushpipe;
263
wire                            wb_flushpipe;
264 10 unneback
wire                            extend_flush;
265 141 marcus.erl
wire                            ex_branch_taken;
266 10 unneback
wire                            flag;
267
wire                            flagforw;
268
wire                            flag_we;
269 185 julius
wire                            flagforw_alu;
270 141 marcus.erl
wire                            flag_we_alu;
271 185 julius
wire                            flagforw_fpu;
272
wire                            flag_we_fpu;
273 10 unneback
wire                            carry;
274
wire                            cyforw;
275 141 marcus.erl
wire                            cy_we_alu;
276 642 julius
wire                            ovforw;
277
wire                            ov_we_alu;
278
wire                            ovforw_mult_mac;
279
wire                            ov_we_mult_mac;
280 141 marcus.erl
wire                            cy_we_rf;
281 10 unneback
wire                            lsu_stall;
282
wire                            epcr_we;
283
wire                            eear_we;
284
wire                            esr_we;
285
wire                            pc_we;
286
wire    [31:0]                   epcr;
287
wire    [31:0]                   eear;
288
wire    [`OR1200_SR_WIDTH-1:0]   esr;
289 185 julius
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
290 258 julius
wire                            fpcsr_we;
291 10 unneback
wire                            sr_we;
292
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
293
wire    [`OR1200_SR_WIDTH-1:0]   sr;
294 808 julius
wire                            dsx;
295 141 marcus.erl
wire                            except_flushpipe;
296 10 unneback
wire                            except_start;
297
wire                            except_started;
298 185 julius
wire                            fpu_except_started;
299 10 unneback
wire    [31:0]                   wb_insn;
300
wire                            sig_syscall;
301
wire                            sig_trap;
302 642 julius
wire                            sig_range;
303 185 julius
wire                            sig_fp;
304 10 unneback
wire    [31:0]                   spr_dat_cfgr;
305
wire    [31:0]                   spr_dat_rf;
306
wire    [31:0]                  spr_dat_npc;
307
wire    [31:0]                   spr_dat_ppc;
308
wire    [31:0]                   spr_dat_mac;
309 258 julius
wire [31:0]                      spr_dat_fpu;
310
wire                            mtspr_done;
311 10 unneback
wire                            force_dslot_fetch;
312
wire                            no_more_dslot;
313
wire                            ex_void;
314 141 marcus.erl
wire                            ex_spr_read;
315
wire                            ex_spr_write;
316 10 unneback
wire                            if_stall;
317
wire                            id_macrc_op;
318
wire                            ex_macrc_op;
319 141 marcus.erl
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
320 10 unneback
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
321
wire    [31:0]                   mult_mac_result;
322 481 julius
wire                            mult_mac_stall;
323 185 julius
wire    [13:0]                   except_trig;
324
wire    [13:0]                   except_stop;
325 10 unneback
wire                            genpc_refetch;
326
wire                            rfe;
327
wire                            lsu_unstall;
328
wire                            except_align;
329
wire                            except_dtlbmiss;
330
wire                            except_dmmufault;
331
wire                            except_illegal;
332
wire                            except_itlbmiss;
333
wire                            except_immufault;
334
wire                            except_ibuserr;
335
wire                            except_dbuserr;
336
wire                            abort_ex;
337 141 marcus.erl
wire                            abort_mvspr;
338 10 unneback
 
339
//
340
// Send exceptions to Debug Unit
341
//
342 141 marcus.erl
assign du_except_trig = except_trig;
343
assign du_except_stop = except_stop;
344
assign du_lsu_store_dat = operand_b;
345
assign du_lsu_load_dat  = lsu_dataout;
346 10 unneback
 
347
//
348
// Data cache enable
349
//
350 141 marcus.erl
`ifdef OR1200_NO_DC
351
assign dc_en = 1'b0;
352
`else
353 258 julius
   assign dc_en = sr[`OR1200_SR_DCE];
354 141 marcus.erl
`endif
355 10 unneback
 
356
//
357
// Instruction cache enable
358
//
359 141 marcus.erl
`ifdef OR1200_NO_IC
360
assign ic_en = 1'b0;
361
`else
362 10 unneback
assign ic_en = sr[`OR1200_SR_ICE];
363 141 marcus.erl
`endif
364 10 unneback
 
365
//
366 141 marcus.erl
// SB enable
367
//
368
`ifdef OR1200_SB_IMPLEMENTED
369
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
370
`else
371
assign sb_en = 1'b0;
372
`endif
373
 
374
//
375 10 unneback
// DMMU enable
376
//
377 141 marcus.erl
`ifdef OR1200_NO_DMMU
378
assign dmmu_en = 1'b0;
379
`else
380 10 unneback
assign dmmu_en = sr[`OR1200_SR_DME];
381 141 marcus.erl
`endif
382 10 unneback
 
383
//
384
// IMMU enable
385
//
386 141 marcus.erl
`ifdef OR1200_NO_IMMU
387
assign immu_en = 1'b0;
388
`else
389
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
390
`endif
391 10 unneback
 
392
//
393
// SUPV bit
394
//
395
assign supv = sr[`OR1200_SR_SM];
396
 
397
//
398 141 marcus.erl
// FLAG write enable
399
//
400 185 julius
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
401
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
402 141 marcus.erl
 
403
//
404 642 julius
// Flag for any MTSPR instructions, that must block execution, to indicate done
405 258 julius
//
406
assign mtspr_done = mtspr_dc_done;
407 642 julius
 
408
//
409
// Range exception
410
//
411
assign sig_range = sr[`OR1200_SR_OV];
412 258 julius
 
413
 
414 642 julius
 
415 258 julius
//
416 10 unneback
// Instantiation of instruction fetch block
417
//
418 813 olof
or1200_genpc #(.boot_adr(boot_adr)) or1200_genpc(
419 10 unneback
        .clk(clk),
420
        .rst(rst),
421
        .icpu_adr_o(icpu_adr_o),
422
        .icpu_cycstb_o(icpu_cycstb_o),
423
        .icpu_sel_o(icpu_sel_o),
424
        .icpu_tag_o(icpu_tag_o),
425
        .icpu_rty_i(icpu_rty_i),
426
        .icpu_adr_i(icpu_adr_i),
427
 
428 141 marcus.erl
        .pre_branch_op(pre_branch_op),
429 10 unneback
        .branch_op(branch_op),
430
        .except_type(except_type),
431
        .except_start(except_start),
432
        .except_prefix(sr[`OR1200_SR_EPH]),
433 141 marcus.erl
        .id_branch_addrtarget(id_branch_addrtarget),
434
        .ex_branch_addrtarget(ex_branch_addrtarget),
435
        .muxed_b(muxed_b),
436
        .operand_b(operand_b),
437 10 unneback
        .flag(flag),
438 141 marcus.erl
        .flagforw(flagforw),
439
        .ex_branch_taken(ex_branch_taken),
440 10 unneback
        .epcr(epcr),
441
        .spr_dat_i(spr_dat_cpu),
442
        .spr_pc_we(pc_we),
443
        .genpc_refetch(genpc_refetch),
444
        .genpc_freeze(genpc_freeze),
445 847 stekern
        .no_more_dslot(no_more_dslot),
446 859 olof
        .lsu_stall(lsu_stall),
447
        .du_flush_pipe(du_flush_pipe),
448
        .spr_dat_npc(spr_dat_npc)
449 10 unneback
);
450
 
451
//
452
// Instantiation of instruction fetch block
453
//
454
or1200_if or1200_if(
455
        .clk(clk),
456
        .rst(rst),
457
        .icpu_dat_i(icpu_dat_i),
458
        .icpu_ack_i(icpu_ack_i),
459
        .icpu_err_i(icpu_err_i),
460
        .icpu_adr_i(icpu_adr_i),
461
        .icpu_tag_i(icpu_tag_i),
462
 
463
        .if_freeze(if_freeze),
464
        .if_insn(if_insn),
465
        .if_pc(if_pc),
466 141 marcus.erl
        .saving_if_insn(saving_if_insn),
467
        .if_flushpipe(if_flushpipe),
468 10 unneback
        .if_stall(if_stall),
469
        .no_more_dslot(no_more_dslot),
470
        .genpc_refetch(genpc_refetch),
471
        .rfe(rfe),
472
        .except_itlbmiss(except_itlbmiss),
473
        .except_immufault(except_immufault),
474
        .except_ibuserr(except_ibuserr)
475
);
476
 
477
//
478
// Instantiation of instruction decode/control logic
479
//
480
or1200_ctrl or1200_ctrl(
481
        .clk(clk),
482
        .rst(rst),
483
        .id_freeze(id_freeze),
484
        .ex_freeze(ex_freeze),
485
        .wb_freeze(wb_freeze),
486 141 marcus.erl
        .if_flushpipe(if_flushpipe),
487
        .id_flushpipe(id_flushpipe),
488
        .ex_flushpipe(ex_flushpipe),
489
        .wb_flushpipe(wb_flushpipe),
490
        .extend_flush(extend_flush),
491
        .except_flushpipe(except_flushpipe),
492
        .abort_mvspr(abort_mvspr),
493 10 unneback
        .if_insn(if_insn),
494 141 marcus.erl
        .id_insn(id_insn),
495 10 unneback
        .ex_insn(ex_insn),
496 141 marcus.erl
        .id_branch_op(pre_branch_op),
497
        .ex_branch_op(branch_op),
498
        .ex_branch_taken(ex_branch_taken),
499 10 unneback
        .rf_addra(rf_addra),
500
        .rf_addrb(rf_addrb),
501
        .rf_rda(rf_rda),
502
        .rf_rdb(rf_rdb),
503
        .alu_op(alu_op),
504 401 julius
        .alu_op2(alu_op2),
505 10 unneback
        .mac_op(mac_op),
506
        .comp_op(comp_op),
507
        .rf_addrw(rf_addrw),
508
        .rfwb_op(rfwb_op),
509 185 julius
        .fpu_op(fpu_op),
510 141 marcus.erl
        .pc_we(pc_we),
511 10 unneback
        .wb_insn(wb_insn),
512 141 marcus.erl
        .id_simm(id_simm),
513
        .id_branch_addrtarget(id_branch_addrtarget),
514
        .ex_branch_addrtarget(ex_branch_addrtarget),
515
        .ex_simm(ex_simm),
516 10 unneback
        .sel_a(sel_a),
517
        .sel_b(sel_b),
518 141 marcus.erl
        .id_lsu_op(id_lsu_op),
519 10 unneback
        .cust5_op(cust5_op),
520
        .cust5_limm(cust5_limm),
521 141 marcus.erl
        .id_pc(id_pc),
522
        .ex_pc(ex_pc),
523 10 unneback
        .multicycle(multicycle),
524 258 julius
        .wait_on(wait_on),
525 10 unneback
        .wbforw_valid(wbforw_valid),
526
        .sig_syscall(sig_syscall),
527
        .sig_trap(sig_trap),
528
        .force_dslot_fetch(force_dslot_fetch),
529
        .no_more_dslot(no_more_dslot),
530 141 marcus.erl
        .id_void(id_void),
531 10 unneback
        .ex_void(ex_void),
532 141 marcus.erl
        .ex_spr_read(ex_spr_read),
533
        .ex_spr_write(ex_spr_write),
534
        .id_mac_op(id_mac_op),
535 10 unneback
        .id_macrc_op(id_macrc_op),
536
        .ex_macrc_op(ex_macrc_op),
537
        .rfe(rfe),
538
        .du_hwbkpt(du_hwbkpt),
539 258 julius
        .except_illegal(except_illegal),
540 859 olof
        .dc_no_writethrough(dc_no_writethrough),
541
        .du_flush_pipe(du_flush_pipe)
542 10 unneback
);
543
 
544
//
545
// Instantiation of register file
546
//
547
or1200_rf or1200_rf(
548
        .clk(clk),
549
        .rst(rst),
550 141 marcus.erl
        .cy_we_i(cy_we_alu),
551
        .cy_we_o(cy_we_rf),
552 10 unneback
        .supv(sr[`OR1200_SR_SM]),
553
        .wb_freeze(wb_freeze),
554
        .addrw(rf_addrw),
555
        .dataw(rf_dataw),
556
        .id_freeze(id_freeze),
557
        .we(rfwb_op[0]),
558 141 marcus.erl
        .flushpipe(wb_flushpipe),
559 10 unneback
        .addra(rf_addra),
560
        .rda(rf_rda),
561
        .dataa(rf_dataa),
562
        .addrb(rf_addrb),
563
        .rdb(rf_rdb),
564
        .datab(rf_datab),
565
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
566
        .spr_write(spr_we),
567
        .spr_addr(spr_addr),
568
        .spr_dat_i(spr_dat_cpu),
569 258 julius
        .spr_dat_o(spr_dat_rf),
570
        .du_read(du_read)
571 10 unneback
);
572
 
573
//
574
// Instantiation of operand muxes
575
//
576
or1200_operandmuxes or1200_operandmuxes(
577
        .clk(clk),
578
        .rst(rst),
579
        .id_freeze(id_freeze),
580
        .ex_freeze(ex_freeze),
581
        .rf_dataa(rf_dataa),
582
        .rf_datab(rf_datab),
583
        .ex_forw(rf_dataw),
584
        .wb_forw(wb_forw),
585 141 marcus.erl
        .simm(id_simm),
586 10 unneback
        .sel_a(sel_a),
587
        .sel_b(sel_b),
588
        .operand_a(operand_a),
589
        .operand_b(operand_b),
590 141 marcus.erl
        .muxed_a(muxed_a),
591 10 unneback
        .muxed_b(muxed_b)
592
);
593
 
594
//
595
// Instantiation of CPU's ALU
596
//
597
or1200_alu or1200_alu(
598
        .a(operand_a),
599
        .b(operand_b),
600
        .mult_mac_result(mult_mac_result),
601
        .macrc_op(ex_macrc_op),
602
        .alu_op(alu_op),
603 401 julius
        .alu_op2(alu_op2),
604 10 unneback
        .comp_op(comp_op),
605
        .cust5_op(cust5_op),
606
        .cust5_limm(cust5_limm),
607
        .result(alu_dataout),
608 185 julius
        .flagforw(flagforw_alu),
609 141 marcus.erl
        .flag_we(flag_we_alu),
610 10 unneback
        .cyforw(cyforw),
611 141 marcus.erl
        .cy_we(cy_we_alu),
612 642 julius
        .ovforw(ovforw),
613
        .ov_we(ov_we_alu),
614 141 marcus.erl
        .flag(flag),
615 10 unneback
        .carry(carry)
616
);
617
 
618 185 julius
 
619 10 unneback
//
620 185 julius
// FPU's exception is being dealt with
621
//    
622
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
623
 
624 10 unneback
//
625 185 julius
// Instantiation of FPU
626
//
627
or1200_fpu or1200_fpu(
628
        .clk(clk),
629
        .rst(rst),
630
        .ex_freeze(ex_freeze),
631
        .a(operand_a),
632
        .b(operand_b),
633
        .fpu_op(fpu_op),
634
        .result(fpu_dataout),
635 258 julius
        .done(fpu_done),
636 185 julius
        .flagforw(flagforw_fpu),
637
        .flag_we(flag_we_fpu),
638
        .sig_fp(sig_fp),
639 258 julius
        .except_started(fpu_except_started),
640 185 julius
        .fpcsr_we(fpcsr_we),
641 258 julius
        .fpcsr(fpcsr),
642 185 julius
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
643
        .spr_write(spr_we),
644
        .spr_addr(spr_addr),
645
        .spr_dat_i(spr_dat_cpu),
646
        .spr_dat_o(spr_dat_fpu)
647
);
648
 
649
 
650
//
651
// Instantiation of CPU's multiply unit
652
//
653 10 unneback
or1200_mult_mac or1200_mult_mac(
654
        .clk(clk),
655
        .rst(rst),
656
        .ex_freeze(ex_freeze),
657
        .id_macrc_op(id_macrc_op),
658
        .macrc_op(ex_macrc_op),
659
        .a(operand_a),
660
        .b(operand_b),
661
        .mac_op(mac_op),
662
        .alu_op(alu_op),
663
        .result(mult_mac_result),
664 642 julius
        .ovforw(ovforw_mult_mac),
665
        .ov_we(ov_we_mult_mac),
666 481 julius
        .mult_mac_stall(mult_mac_stall),
667 10 unneback
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
668
        .spr_write(spr_we),
669
        .spr_addr(spr_addr),
670
        .spr_dat_i(spr_dat_cpu),
671
        .spr_dat_o(spr_dat_mac)
672
);
673
 
674
//
675
// Instantiation of CPU's SPRS block
676
//
677
or1200_sprs or1200_sprs(
678
        .clk(clk),
679
        .rst(rst),
680
        .addrbase(operand_a),
681 141 marcus.erl
        .addrofs(ex_simm[15:0]),
682 10 unneback
        .dat_i(operand_b),
683 141 marcus.erl
        .ex_spr_read(ex_spr_read),
684
        .ex_spr_write(ex_spr_write),
685 10 unneback
        .flagforw(flagforw),
686
        .flag_we(flag_we),
687
        .flag(flag),
688
        .cyforw(cyforw),
689 141 marcus.erl
        .cy_we(cy_we_rf),
690 10 unneback
        .carry(carry),
691 642 julius
        .ovforw(ovforw | ovforw_mult_mac),
692
        .ov_we(ov_we_alu | ov_we_mult_mac),
693 10 unneback
        .to_wbmux(sprs_dataout),
694
 
695
        .du_addr(du_addr),
696
        .du_dat_du(du_dat_du),
697
        .du_read(du_read),
698
        .du_write(du_write),
699
        .du_dat_cpu(du_dat_cpu),
700 141 marcus.erl
        .boot_adr_sel_i(boot_adr_sel_i),
701 10 unneback
        .spr_addr(spr_addr),
702
        .spr_dat_pic(spr_dat_pic),
703
        .spr_dat_tt(spr_dat_tt),
704
        .spr_dat_pm(spr_dat_pm),
705
        .spr_dat_cfgr(spr_dat_cfgr),
706
        .spr_dat_rf(spr_dat_rf),
707
        .spr_dat_npc(spr_dat_npc),
708
        .spr_dat_ppc(spr_dat_ppc),
709
        .spr_dat_mac(spr_dat_mac),
710
        .spr_dat_dmmu(spr_dat_dmmu),
711
        .spr_dat_immu(spr_dat_immu),
712
        .spr_dat_du(spr_dat_du),
713
        .spr_dat_o(spr_dat_cpu),
714
        .spr_cs(spr_cs),
715
        .spr_we(spr_we),
716
 
717
        .epcr_we(epcr_we),
718
        .eear_we(eear_we),
719
        .esr_we(esr_we),
720
        .pc_we(pc_we),
721
        .epcr(epcr),
722
        .eear(eear),
723
        .esr(esr),
724
        .except_started(except_started),
725
 
726 185 julius
        .fpcsr(fpcsr),
727 258 julius
        .fpcsr_we(fpcsr_we),
728 185 julius
        .spr_dat_fpu(spr_dat_fpu),
729
 
730 10 unneback
        .sr_we(sr_we),
731
        .to_sr(to_sr),
732
        .sr(sr),
733 808 julius
        .branch_op(branch_op),
734
        .dsx(dsx)
735 10 unneback
);
736
 
737
//
738
// Instantiation of load/store unit
739
//
740
or1200_lsu or1200_lsu(
741 141 marcus.erl
        .clk(clk),
742
        .rst(rst),
743
        .id_addrbase(muxed_a),
744
        .id_addrofs(id_simm),
745
        .ex_addrbase(operand_a),
746
        .ex_addrofs(ex_simm),
747
        .id_lsu_op(id_lsu_op),
748 10 unneback
        .lsu_datain(operand_b),
749
        .lsu_dataout(lsu_dataout),
750
        .lsu_stall(lsu_stall),
751
        .lsu_unstall(lsu_unstall),
752 141 marcus.erl
        .du_stall(du_stall),
753 10 unneback
        .except_align(except_align),
754
        .except_dtlbmiss(except_dtlbmiss),
755
        .except_dmmufault(except_dmmufault),
756
        .except_dbuserr(except_dbuserr),
757 141 marcus.erl
        .id_freeze(id_freeze),
758
        .ex_freeze(ex_freeze),
759
        .flushpipe(ex_flushpipe),
760 10 unneback
 
761
        .dcpu_adr_o(dcpu_adr_o),
762
        .dcpu_cycstb_o(dcpu_cycstb_o),
763
        .dcpu_we_o(dcpu_we_o),
764
        .dcpu_sel_o(dcpu_sel_o),
765
        .dcpu_tag_o(dcpu_tag_o),
766
        .dcpu_dat_o(dcpu_dat_o),
767
        .dcpu_dat_i(dcpu_dat_i),
768
        .dcpu_ack_i(dcpu_ack_i),
769
        .dcpu_rty_i(dcpu_rty_i),
770
        .dcpu_err_i(dcpu_err_i),
771
        .dcpu_tag_i(dcpu_tag_i)
772
);
773
 
774
//
775
// Instantiation of write-back muxes
776
//
777
or1200_wbmux or1200_wbmux(
778
        .clk(clk),
779
        .rst(rst),
780
        .wb_freeze(wb_freeze),
781
        .rfwb_op(rfwb_op),
782
        .muxin_a(alu_dataout),
783
        .muxin_b(lsu_dataout),
784
        .muxin_c(sprs_dataout),
785 141 marcus.erl
        .muxin_d(ex_pc),
786 185 julius
        .muxin_e(fpu_dataout),
787 10 unneback
        .muxout(rf_dataw),
788
        .muxreg(wb_forw),
789
        .muxreg_valid(wbforw_valid)
790
);
791
 
792
//
793
// Instantiation of freeze logic
794
//
795
or1200_freeze or1200_freeze(
796
        .clk(clk),
797
        .rst(rst),
798
        .multicycle(multicycle),
799 258 julius
        .wait_on(wait_on),
800
        .fpu_done(fpu_done),
801
        .mtspr_done(mtspr_done),
802 141 marcus.erl
        .flushpipe(wb_flushpipe),
803 10 unneback
        .extend_flush(extend_flush),
804
        .lsu_stall(lsu_stall),
805
        .if_stall(if_stall),
806
        .lsu_unstall(lsu_unstall),
807
        .force_dslot_fetch(force_dslot_fetch),
808
        .abort_ex(abort_ex),
809
        .du_stall(du_stall),
810 481 julius
        .mac_stall(mult_mac_stall),
811 141 marcus.erl
        .saving_if_insn(saving_if_insn),
812 10 unneback
        .genpc_freeze(genpc_freeze),
813
        .if_freeze(if_freeze),
814
        .id_freeze(id_freeze),
815
        .ex_freeze(ex_freeze),
816
        .wb_freeze(wb_freeze),
817
        .icpu_ack_i(icpu_ack_i),
818
        .icpu_err_i(icpu_err_i)
819
);
820
 
821
//
822
// Instantiation of exception block
823
//
824
or1200_except or1200_except(
825
        .clk(clk),
826
        .rst(rst),
827
        .sig_ibuserr(except_ibuserr),
828
        .sig_dbuserr(except_dbuserr),
829
        .sig_illegal(except_illegal),
830
        .sig_align(except_align),
831 642 julius
        .sig_range(sig_range),
832 10 unneback
        .sig_dtlbmiss(except_dtlbmiss),
833
        .sig_dmmufault(except_dmmufault),
834
        .sig_int(sig_int),
835
        .sig_syscall(sig_syscall),
836
        .sig_trap(sig_trap),
837
        .sig_itlbmiss(except_itlbmiss),
838
        .sig_immufault(except_immufault),
839
        .sig_tick(sig_tick),
840 185 julius
        .sig_fp(sig_fp),
841 258 julius
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
842 141 marcus.erl
        .ex_branch_taken(ex_branch_taken),
843 10 unneback
        .icpu_ack_i(icpu_ack_i),
844
        .icpu_err_i(icpu_err_i),
845
        .dcpu_ack_i(dcpu_ack_i),
846
        .dcpu_err_i(dcpu_err_i),
847
        .genpc_freeze(genpc_freeze),
848
        .id_freeze(id_freeze),
849
        .ex_freeze(ex_freeze),
850
        .wb_freeze(wb_freeze),
851
        .if_stall(if_stall),
852
        .if_pc(if_pc),
853
        .id_pc(id_pc),
854 141 marcus.erl
        .ex_pc(ex_pc),
855
        .wb_pc(wb_pc),
856
        .id_flushpipe(id_flushpipe),
857
        .ex_flushpipe(ex_flushpipe),
858 10 unneback
        .extend_flush(extend_flush),
859 141 marcus.erl
        .except_flushpipe(except_flushpipe),
860
        .abort_mvspr(abort_mvspr),
861 10 unneback
        .except_type(except_type),
862
        .except_start(except_start),
863
        .except_started(except_started),
864
        .except_stop(except_stop),
865 141 marcus.erl
        .except_trig(except_trig),
866 10 unneback
        .ex_void(ex_void),
867
        .spr_dat_ppc(spr_dat_ppc),
868
        .spr_dat_npc(spr_dat_npc),
869
 
870 141 marcus.erl
        .datain(spr_dat_cpu),
871
        .branch_op(branch_op),
872 10 unneback
        .du_dsr(du_dsr),
873 141 marcus.erl
        .du_dmr1(du_dmr1),
874
        .du_hwbkpt(du_hwbkpt),
875
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
876 10 unneback
        .epcr_we(epcr_we),
877
        .eear_we(eear_we),
878
        .esr_we(esr_we),
879
        .pc_we(pc_we),
880
        .epcr(epcr),
881
        .eear(eear),
882
        .esr(esr),
883
 
884
        .lsu_addr(dcpu_adr_o),
885
        .sr_we(sr_we),
886
        .to_sr(to_sr),
887
        .sr(sr),
888 808 julius
        .abort_ex(abort_ex),
889
        .dsx(dsx)
890 10 unneback
);
891
 
892
//
893
// Instantiation of configuration registers
894
//
895
or1200_cfgr or1200_cfgr(
896
        .spr_addr(spr_addr),
897
        .spr_dat_o(spr_dat_cfgr)
898
);
899
 
900
endmodule

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