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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Blame information for rev 185

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66 141 marcus.erl
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop, du_except_trig,
70
        du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu, du_lsu_store_dat, du_lsu_load_dat,
71
        abort_mvspr, abort_ex,
72 10 unneback
 
73
        // Data interface
74
        dc_en,
75
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
76
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
77 141 marcus.erl
        sb_en, dmmu_en,
78 10 unneback
 
79 141 marcus.erl
        // SR Interface
80
        boot_adr_sel_i,
81
 
82 10 unneback
        // Interrupt & tick exceptions
83
        sig_int, sig_tick,
84
 
85
        // SPR interface
86
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
87
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
88
);
89
 
90
parameter dw = `OR1200_OPERAND_WIDTH;
91
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
92
 
93
//
94
// I/O ports
95
//
96
 
97
//
98
// Clk & Rst
99
//
100
input                           clk;
101
input                           rst;
102
 
103
//
104
// Insn (IC) interface
105
//
106
output                          ic_en;
107
output  [31:0]                   icpu_adr_o;
108
output                          icpu_cycstb_o;
109
output  [3:0]                    icpu_sel_o;
110
output  [3:0]                    icpu_tag_o;
111
input   [31:0]                   icpu_dat_i;
112
input                           icpu_ack_i;
113
input                           icpu_rty_i;
114
input                           icpu_err_i;
115
input   [31:0]                   icpu_adr_i;
116
input   [3:0]                    icpu_tag_i;
117
 
118
//
119
// Insn (IMMU) interface
120
//
121
output                          immu_en;
122
 
123
//
124
// Debug interface
125
//
126 141 marcus.erl
output                          id_void;
127
output  [31:0]                   id_insn;
128
output                          ex_void;
129 10 unneback
output  [31:0]                   ex_insn;
130
output                          ex_freeze;
131 141 marcus.erl
output  [31:0]                   wb_insn;
132
output                          wb_freeze;
133 10 unneback
output  [31:0]                   id_pc;
134 141 marcus.erl
output  [31:0]                   ex_pc;
135
output  [31:0]                   wb_pc;
136
output                          ex_flushpipe;
137 10 unneback
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
138
 
139
input                           du_stall;
140
input   [dw-1:0]         du_addr;
141
input   [dw-1:0]         du_dat_du;
142
input                           du_read;
143
input                           du_write;
144
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
145 141 marcus.erl
input   [24:0]                   du_dmr1;
146 10 unneback
input                           du_hwbkpt;
147 141 marcus.erl
input                           du_hwbkpt_ls_r;
148 185 julius
output  [13:0]                   du_except_trig;
149
output  [13:0]                   du_except_stop;
150 10 unneback
output  [dw-1:0]         du_dat_cpu;
151
output  [dw-1:0]         rf_dataw;
152 141 marcus.erl
output  [dw-1:0]         du_lsu_store_dat;
153
output  [dw-1:0]         du_lsu_load_dat;
154 10 unneback
 
155
//
156
// Data (DC) interface
157
//
158
output  [31:0]                   dcpu_adr_o;
159
output                          dcpu_cycstb_o;
160
output                          dcpu_we_o;
161
output  [3:0]                    dcpu_sel_o;
162
output  [3:0]                    dcpu_tag_o;
163
output  [31:0]                   dcpu_dat_o;
164
input   [31:0]                   dcpu_dat_i;
165
input                           dcpu_ack_i;
166
input                           dcpu_rty_i;
167
input                           dcpu_err_i;
168
input   [3:0]                    dcpu_tag_i;
169
output                          dc_en;
170
 
171
//
172
// Data (DMMU) interface
173
//
174 141 marcus.erl
output                          sb_en;
175 10 unneback
output                          dmmu_en;
176 141 marcus.erl
output                          abort_ex;
177
output                          abort_mvspr;
178 10 unneback
 
179
//
180 141 marcus.erl
// SR Interface 
181
//
182
input                           boot_adr_sel_i;
183
 
184
//
185 10 unneback
// SPR interface
186
//
187
output                          supv;
188
input   [dw-1:0]         spr_dat_pic;
189
input   [dw-1:0]         spr_dat_tt;
190
input   [dw-1:0]         spr_dat_pm;
191
input   [dw-1:0]         spr_dat_dmmu;
192
input   [dw-1:0]         spr_dat_immu;
193
input   [dw-1:0]         spr_dat_du;
194
output  [dw-1:0]         spr_addr;
195
output  [dw-1:0]         spr_dat_cpu;
196
output  [dw-1:0]         spr_dat_npc;
197
output  [31:0]                   spr_cs;
198
output                          spr_we;
199
 
200
//
201
// Interrupt exceptions
202
//
203
input                           sig_int;
204
input                           sig_tick;
205
 
206
//
207
// Internal wires
208
//
209
wire    [31:0]                   if_insn;
210 141 marcus.erl
wire                            saving_if_insn;
211 10 unneback
wire    [31:0]                   if_pc;
212
wire    [aw-1:0]         rf_addrw;
213
wire    [aw-1:0]                 rf_addra;
214
wire    [aw-1:0]                 rf_addrb;
215
wire                            rf_rda;
216
wire                            rf_rdb;
217 141 marcus.erl
wire    [dw-1:0]         id_simm;
218
wire    [dw-1:2]                id_branch_addrtarget;
219
wire    [dw-1:2]                ex_branch_addrtarget;
220 10 unneback
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
221
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
222
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
223 141 marcus.erl
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
224 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
225 141 marcus.erl
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
226 10 unneback
wire                            genpc_freeze;
227
wire                            if_freeze;
228
wire                            id_freeze;
229
wire                            ex_freeze;
230
wire                            wb_freeze;
231
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
232
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
233
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
234 185 julius
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
235 10 unneback
wire    [dw-1:0]         rf_dataw;
236
wire    [dw-1:0]         rf_dataa;
237
wire    [dw-1:0]         rf_datab;
238 141 marcus.erl
wire    [dw-1:0]         muxed_a;
239 10 unneback
wire    [dw-1:0]         muxed_b;
240
wire    [dw-1:0]         wb_forw;
241
wire                            wbforw_valid;
242
wire    [dw-1:0]         operand_a;
243
wire    [dw-1:0]         operand_b;
244
wire    [dw-1:0]         alu_dataout;
245
wire    [dw-1:0]         lsu_dataout;
246
wire    [dw-1:0]         sprs_dataout;
247 185 julius
wire    [dw-1:0]         fpu_dataout;
248 141 marcus.erl
wire    [31:0]                   ex_simm;
249 10 unneback
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
250
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
251
wire    [4:0]                    cust5_op;
252
wire    [5:0]                    cust5_limm;
253 141 marcus.erl
wire                            if_flushpipe;
254
wire                            id_flushpipe;
255
wire                            ex_flushpipe;
256
wire                            wb_flushpipe;
257 10 unneback
wire                            extend_flush;
258 141 marcus.erl
wire                            ex_branch_taken;
259 10 unneback
wire                            flag;
260
wire                            flagforw;
261
wire                            flag_we;
262 185 julius
wire                            flagforw_alu;
263 141 marcus.erl
wire                            flag_we_alu;
264 185 julius
wire                            flagforw_fpu;
265
wire                            flag_we_fpu;
266 10 unneback
wire                            carry;
267
wire                            cyforw;
268 141 marcus.erl
wire                            cy_we_alu;
269
wire                            cy_we_rf;
270 10 unneback
wire                            lsu_stall;
271
wire                            epcr_we;
272
wire                            eear_we;
273
wire                            esr_we;
274
wire                            pc_we;
275
wire    [31:0]                   epcr;
276
wire    [31:0]                   eear;
277
wire    [`OR1200_SR_WIDTH-1:0]   esr;
278 185 julius
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
279
wire                            fpcsr_we;
280 10 unneback
wire                            sr_we;
281
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
282
wire    [`OR1200_SR_WIDTH-1:0]   sr;
283 141 marcus.erl
wire                            except_flushpipe;
284 10 unneback
wire                            except_start;
285
wire                            except_started;
286 185 julius
wire                            fpu_except_started;
287 10 unneback
wire    [31:0]                   wb_insn;
288
wire                            sig_syscall;
289
wire                            sig_trap;
290 185 julius
wire                            sig_fp;
291 10 unneback
wire    [31:0]                   spr_dat_cfgr;
292
wire    [31:0]                   spr_dat_rf;
293
wire    [31:0]                  spr_dat_npc;
294
wire    [31:0]                   spr_dat_ppc;
295
wire    [31:0]                   spr_dat_mac;
296 185 julius
wire [31:0]                      spr_dat_fpu;
297 10 unneback
wire                            force_dslot_fetch;
298
wire                            no_more_dslot;
299
wire                            ex_void;
300 141 marcus.erl
wire                            ex_spr_read;
301
wire                            ex_spr_write;
302 10 unneback
wire                            if_stall;
303
wire                            id_macrc_op;
304
wire                            ex_macrc_op;
305 141 marcus.erl
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
306 10 unneback
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
307
wire    [31:0]                   mult_mac_result;
308
wire                            mac_stall;
309 185 julius
wire    [13:0]                   except_trig;
310
wire    [13:0]                   except_stop;
311 10 unneback
wire                            genpc_refetch;
312
wire                            rfe;
313
wire                            lsu_unstall;
314
wire                            except_align;
315
wire                            except_dtlbmiss;
316
wire                            except_dmmufault;
317
wire                            except_illegal;
318
wire                            except_itlbmiss;
319
wire                            except_immufault;
320
wire                            except_ibuserr;
321
wire                            except_dbuserr;
322
wire                            abort_ex;
323 141 marcus.erl
wire                            abort_mvspr;
324 10 unneback
 
325
//
326
// Send exceptions to Debug Unit
327
//
328 141 marcus.erl
assign du_except_trig = except_trig;
329
assign du_except_stop = except_stop;
330
assign du_lsu_store_dat = operand_b;
331
assign du_lsu_load_dat  = lsu_dataout;
332 10 unneback
 
333
//
334
// Data cache enable
335
//
336 141 marcus.erl
`ifdef OR1200_NO_DC
337
assign dc_en = 1'b0;
338
`else
339 10 unneback
assign dc_en = sr[`OR1200_SR_DCE];
340 141 marcus.erl
`endif
341 10 unneback
 
342
//
343
// Instruction cache enable
344
//
345 141 marcus.erl
`ifdef OR1200_NO_IC
346
assign ic_en = 1'b0;
347
`else
348 10 unneback
assign ic_en = sr[`OR1200_SR_ICE];
349 141 marcus.erl
`endif
350 10 unneback
 
351
//
352 141 marcus.erl
// SB enable
353
//
354
`ifdef OR1200_SB_IMPLEMENTED
355
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
356
`else
357
assign sb_en = 1'b0;
358
`endif
359
 
360
//
361 10 unneback
// DMMU enable
362
//
363 141 marcus.erl
`ifdef OR1200_NO_DMMU
364
assign dmmu_en = 1'b0;
365
`else
366 10 unneback
assign dmmu_en = sr[`OR1200_SR_DME];
367 141 marcus.erl
`endif
368 10 unneback
 
369
//
370
// IMMU enable
371
//
372 141 marcus.erl
`ifdef OR1200_NO_IMMU
373
assign immu_en = 1'b0;
374
`else
375
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
376
`endif
377 10 unneback
 
378
//
379
// SUPV bit
380
//
381
assign supv = sr[`OR1200_SR_SM];
382
 
383
//
384 141 marcus.erl
// FLAG write enable
385
//
386 185 julius
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
387
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
388 141 marcus.erl
 
389
//
390 10 unneback
// Instantiation of instruction fetch block
391
//
392
or1200_genpc or1200_genpc(
393
        .clk(clk),
394
        .rst(rst),
395
        .icpu_adr_o(icpu_adr_o),
396
        .icpu_cycstb_o(icpu_cycstb_o),
397
        .icpu_sel_o(icpu_sel_o),
398
        .icpu_tag_o(icpu_tag_o),
399
        .icpu_rty_i(icpu_rty_i),
400
        .icpu_adr_i(icpu_adr_i),
401
 
402 141 marcus.erl
        .pre_branch_op(pre_branch_op),
403 10 unneback
        .branch_op(branch_op),
404
        .except_type(except_type),
405
        .except_start(except_start),
406
        .except_prefix(sr[`OR1200_SR_EPH]),
407 141 marcus.erl
        .id_branch_addrtarget(id_branch_addrtarget),
408
        .ex_branch_addrtarget(ex_branch_addrtarget),
409
        .muxed_b(muxed_b),
410
        .operand_b(operand_b),
411 10 unneback
        .flag(flag),
412 141 marcus.erl
        .flagforw(flagforw),
413
        .ex_branch_taken(ex_branch_taken),
414 10 unneback
        .epcr(epcr),
415
        .spr_dat_i(spr_dat_cpu),
416
        .spr_pc_we(pc_we),
417
        .genpc_refetch(genpc_refetch),
418
        .genpc_freeze(genpc_freeze),
419
        .no_more_dslot(no_more_dslot)
420
);
421
 
422
//
423
// Instantiation of instruction fetch block
424
//
425
or1200_if or1200_if(
426
        .clk(clk),
427
        .rst(rst),
428
        .icpu_dat_i(icpu_dat_i),
429
        .icpu_ack_i(icpu_ack_i),
430
        .icpu_err_i(icpu_err_i),
431
        .icpu_adr_i(icpu_adr_i),
432
        .icpu_tag_i(icpu_tag_i),
433
 
434
        .if_freeze(if_freeze),
435
        .if_insn(if_insn),
436
        .if_pc(if_pc),
437 141 marcus.erl
        .saving_if_insn(saving_if_insn),
438
        .if_flushpipe(if_flushpipe),
439 10 unneback
        .if_stall(if_stall),
440
        .no_more_dslot(no_more_dslot),
441
        .genpc_refetch(genpc_refetch),
442
        .rfe(rfe),
443
        .except_itlbmiss(except_itlbmiss),
444
        .except_immufault(except_immufault),
445
        .except_ibuserr(except_ibuserr)
446
);
447
 
448
//
449
// Instantiation of instruction decode/control logic
450
//
451
or1200_ctrl or1200_ctrl(
452
        .clk(clk),
453
        .rst(rst),
454
        .id_freeze(id_freeze),
455
        .ex_freeze(ex_freeze),
456
        .wb_freeze(wb_freeze),
457 141 marcus.erl
        .if_flushpipe(if_flushpipe),
458
        .id_flushpipe(id_flushpipe),
459
        .ex_flushpipe(ex_flushpipe),
460
        .wb_flushpipe(wb_flushpipe),
461
        .extend_flush(extend_flush),
462
        .except_flushpipe(except_flushpipe),
463
        .abort_mvspr(abort_mvspr),
464 10 unneback
        .if_insn(if_insn),
465 141 marcus.erl
        .id_insn(id_insn),
466 10 unneback
        .ex_insn(ex_insn),
467 141 marcus.erl
        .id_branch_op(pre_branch_op),
468
        .ex_branch_op(branch_op),
469
        .ex_branch_taken(ex_branch_taken),
470 10 unneback
        .rf_addra(rf_addra),
471
        .rf_addrb(rf_addrb),
472
        .rf_rda(rf_rda),
473
        .rf_rdb(rf_rdb),
474
        .alu_op(alu_op),
475
        .mac_op(mac_op),
476
        .shrot_op(shrot_op),
477
        .comp_op(comp_op),
478
        .rf_addrw(rf_addrw),
479
        .rfwb_op(rfwb_op),
480 185 julius
        .fpu_op(fpu_op),
481 141 marcus.erl
        .pc_we(pc_we),
482 10 unneback
        .wb_insn(wb_insn),
483 141 marcus.erl
        .id_simm(id_simm),
484
        .id_branch_addrtarget(id_branch_addrtarget),
485
        .ex_branch_addrtarget(ex_branch_addrtarget),
486
        .ex_simm(ex_simm),
487 10 unneback
        .sel_a(sel_a),
488
        .sel_b(sel_b),
489 141 marcus.erl
        .id_lsu_op(id_lsu_op),
490 10 unneback
        .cust5_op(cust5_op),
491
        .cust5_limm(cust5_limm),
492 141 marcus.erl
        .id_pc(id_pc),
493
        .ex_pc(ex_pc),
494 10 unneback
        .multicycle(multicycle),
495
        .wbforw_valid(wbforw_valid),
496
        .sig_syscall(sig_syscall),
497
        .sig_trap(sig_trap),
498
        .force_dslot_fetch(force_dslot_fetch),
499
        .no_more_dslot(no_more_dslot),
500 141 marcus.erl
        .id_void(id_void),
501 10 unneback
        .ex_void(ex_void),
502 141 marcus.erl
        .ex_spr_read(ex_spr_read),
503
        .ex_spr_write(ex_spr_write),
504
        .id_mac_op(id_mac_op),
505 10 unneback
        .id_macrc_op(id_macrc_op),
506
        .ex_macrc_op(ex_macrc_op),
507
        .rfe(rfe),
508
        .du_hwbkpt(du_hwbkpt),
509
        .except_illegal(except_illegal)
510
);
511
 
512
//
513
// Instantiation of register file
514
//
515
or1200_rf or1200_rf(
516
        .clk(clk),
517
        .rst(rst),
518 141 marcus.erl
        .cy_we_i(cy_we_alu),
519
        .cy_we_o(cy_we_rf),
520 10 unneback
        .supv(sr[`OR1200_SR_SM]),
521
        .wb_freeze(wb_freeze),
522
        .addrw(rf_addrw),
523
        .dataw(rf_dataw),
524
        .id_freeze(id_freeze),
525
        .we(rfwb_op[0]),
526 141 marcus.erl
        .flushpipe(wb_flushpipe),
527 10 unneback
        .addra(rf_addra),
528
        .rda(rf_rda),
529
        .dataa(rf_dataa),
530
        .addrb(rf_addrb),
531
        .rdb(rf_rdb),
532
        .datab(rf_datab),
533
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
534
        .spr_write(spr_we),
535
        .spr_addr(spr_addr),
536
        .spr_dat_i(spr_dat_cpu),
537
        .spr_dat_o(spr_dat_rf)
538
);
539
 
540
//
541
// Instantiation of operand muxes
542
//
543
or1200_operandmuxes or1200_operandmuxes(
544
        .clk(clk),
545
        .rst(rst),
546
        .id_freeze(id_freeze),
547
        .ex_freeze(ex_freeze),
548
        .rf_dataa(rf_dataa),
549
        .rf_datab(rf_datab),
550
        .ex_forw(rf_dataw),
551
        .wb_forw(wb_forw),
552 141 marcus.erl
        .simm(id_simm),
553 10 unneback
        .sel_a(sel_a),
554
        .sel_b(sel_b),
555
        .operand_a(operand_a),
556
        .operand_b(operand_b),
557 141 marcus.erl
        .muxed_a(muxed_a),
558 10 unneback
        .muxed_b(muxed_b)
559
);
560
 
561
//
562
// Instantiation of CPU's ALU
563
//
564
or1200_alu or1200_alu(
565
        .a(operand_a),
566
        .b(operand_b),
567
        .mult_mac_result(mult_mac_result),
568
        .macrc_op(ex_macrc_op),
569
        .alu_op(alu_op),
570
        .shrot_op(shrot_op),
571
        .comp_op(comp_op),
572
        .cust5_op(cust5_op),
573
        .cust5_limm(cust5_limm),
574
        .result(alu_dataout),
575 185 julius
        .flagforw(flagforw_alu),
576 141 marcus.erl
        .flag_we(flag_we_alu),
577 10 unneback
        .cyforw(cyforw),
578 141 marcus.erl
        .cy_we(cy_we_alu),
579
        .flag(flag),
580 10 unneback
        .carry(carry)
581
);
582
 
583 185 julius
 
584
`ifdef OR1200_FPU_IMPLEMENTED
585
 
586 10 unneback
//
587 185 julius
// FPU's exception is being dealt with
588
//    
589
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
590
 
591 10 unneback
//
592 185 julius
// Instantiation of FPU
593
//
594
or1200_fpu or1200_fpu(
595
        .clk(clk),
596
        .rst(rst),
597
        .ex_freeze(ex_freeze),
598
        .a(operand_a),
599
        .b(operand_b),
600
        .fpu_op(fpu_op),
601
        .result(fpu_dataout),
602
        .flagforw(flagforw_fpu),
603
        .flag_we(flag_we_fpu),
604
        .sig_fp(sig_fp),
605
        .except_started(fpu_except_started),
606
        .fpcsr_we(fpcsr_we),
607
        .fpcsr(fpcsr),
608
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
609
        .spr_write(spr_we),
610
        .spr_addr(spr_addr),
611
        .spr_dat_i(spr_dat_cpu),
612
        .spr_dat_o(spr_dat_fpu)
613
);
614
`else
615
   assign sig_fp = 0;
616
   assign fpcsr = 0;
617
`endif
618
 
619
 
620
//
621
// Instantiation of CPU's multiply unit
622
//
623 10 unneback
or1200_mult_mac or1200_mult_mac(
624
        .clk(clk),
625
        .rst(rst),
626
        .ex_freeze(ex_freeze),
627
        .id_macrc_op(id_macrc_op),
628
        .macrc_op(ex_macrc_op),
629
        .a(operand_a),
630
        .b(operand_b),
631
        .mac_op(mac_op),
632
        .alu_op(alu_op),
633
        .result(mult_mac_result),
634
        .mac_stall_r(mac_stall),
635
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
636
        .spr_write(spr_we),
637
        .spr_addr(spr_addr),
638
        .spr_dat_i(spr_dat_cpu),
639
        .spr_dat_o(spr_dat_mac)
640
);
641
 
642
//
643
// Instantiation of CPU's SPRS block
644
//
645
or1200_sprs or1200_sprs(
646
        .clk(clk),
647
        .rst(rst),
648
        .addrbase(operand_a),
649 141 marcus.erl
        .addrofs(ex_simm[15:0]),
650 10 unneback
        .dat_i(operand_b),
651 141 marcus.erl
        .ex_spr_read(ex_spr_read),
652
        .ex_spr_write(ex_spr_write),
653 10 unneback
        .flagforw(flagforw),
654
        .flag_we(flag_we),
655
        .flag(flag),
656
        .cyforw(cyforw),
657 141 marcus.erl
        .cy_we(cy_we_rf),
658 10 unneback
        .carry(carry),
659
        .to_wbmux(sprs_dataout),
660
 
661
        .du_addr(du_addr),
662
        .du_dat_du(du_dat_du),
663
        .du_read(du_read),
664
        .du_write(du_write),
665
        .du_dat_cpu(du_dat_cpu),
666 141 marcus.erl
        .boot_adr_sel_i(boot_adr_sel_i),
667 10 unneback
        .spr_addr(spr_addr),
668
        .spr_dat_pic(spr_dat_pic),
669
        .spr_dat_tt(spr_dat_tt),
670
        .spr_dat_pm(spr_dat_pm),
671
        .spr_dat_cfgr(spr_dat_cfgr),
672
        .spr_dat_rf(spr_dat_rf),
673
        .spr_dat_npc(spr_dat_npc),
674
        .spr_dat_ppc(spr_dat_ppc),
675
        .spr_dat_mac(spr_dat_mac),
676
        .spr_dat_dmmu(spr_dat_dmmu),
677
        .spr_dat_immu(spr_dat_immu),
678
        .spr_dat_du(spr_dat_du),
679
        .spr_dat_o(spr_dat_cpu),
680
        .spr_cs(spr_cs),
681
        .spr_we(spr_we),
682
 
683
        .epcr_we(epcr_we),
684
        .eear_we(eear_we),
685
        .esr_we(esr_we),
686
        .pc_we(pc_we),
687
        .epcr(epcr),
688
        .eear(eear),
689
        .esr(esr),
690
        .except_started(except_started),
691
 
692 185 julius
        .fpcsr(fpcsr),
693
        .fpcsr_we(fpcsr_we),
694
        .spr_dat_fpu(spr_dat_fpu),
695
 
696 10 unneback
        .sr_we(sr_we),
697
        .to_sr(to_sr),
698
        .sr(sr),
699
        .branch_op(branch_op)
700
);
701
 
702
//
703
// Instantiation of load/store unit
704
//
705
or1200_lsu or1200_lsu(
706 141 marcus.erl
        .clk(clk),
707
        .rst(rst),
708
        .id_addrbase(muxed_a),
709
        .id_addrofs(id_simm),
710
        .ex_addrbase(operand_a),
711
        .ex_addrofs(ex_simm),
712
        .id_lsu_op(id_lsu_op),
713 10 unneback
        .lsu_datain(operand_b),
714
        .lsu_dataout(lsu_dataout),
715
        .lsu_stall(lsu_stall),
716
        .lsu_unstall(lsu_unstall),
717 141 marcus.erl
        .du_stall(du_stall),
718 10 unneback
        .except_align(except_align),
719
        .except_dtlbmiss(except_dtlbmiss),
720
        .except_dmmufault(except_dmmufault),
721
        .except_dbuserr(except_dbuserr),
722 141 marcus.erl
        .id_freeze(id_freeze),
723
        .ex_freeze(ex_freeze),
724
        .flushpipe(ex_flushpipe),
725 10 unneback
 
726
        .dcpu_adr_o(dcpu_adr_o),
727
        .dcpu_cycstb_o(dcpu_cycstb_o),
728
        .dcpu_we_o(dcpu_we_o),
729
        .dcpu_sel_o(dcpu_sel_o),
730
        .dcpu_tag_o(dcpu_tag_o),
731
        .dcpu_dat_o(dcpu_dat_o),
732
        .dcpu_dat_i(dcpu_dat_i),
733
        .dcpu_ack_i(dcpu_ack_i),
734
        .dcpu_rty_i(dcpu_rty_i),
735
        .dcpu_err_i(dcpu_err_i),
736
        .dcpu_tag_i(dcpu_tag_i)
737
);
738
 
739
//
740
// Instantiation of write-back muxes
741
//
742
or1200_wbmux or1200_wbmux(
743
        .clk(clk),
744
        .rst(rst),
745
        .wb_freeze(wb_freeze),
746
        .rfwb_op(rfwb_op),
747
        .muxin_a(alu_dataout),
748
        .muxin_b(lsu_dataout),
749
        .muxin_c(sprs_dataout),
750 141 marcus.erl
        .muxin_d(ex_pc),
751 185 julius
        .muxin_e(fpu_dataout),
752 10 unneback
        .muxout(rf_dataw),
753
        .muxreg(wb_forw),
754
        .muxreg_valid(wbforw_valid)
755
);
756
 
757
//
758
// Instantiation of freeze logic
759
//
760
or1200_freeze or1200_freeze(
761
        .clk(clk),
762
        .rst(rst),
763
        .multicycle(multicycle),
764 141 marcus.erl
        .flushpipe(wb_flushpipe),
765 10 unneback
        .extend_flush(extend_flush),
766
        .lsu_stall(lsu_stall),
767
        .if_stall(if_stall),
768
        .lsu_unstall(lsu_unstall),
769
        .force_dslot_fetch(force_dslot_fetch),
770
        .abort_ex(abort_ex),
771
        .du_stall(du_stall),
772
        .mac_stall(mac_stall),
773 141 marcus.erl
        .saving_if_insn(saving_if_insn),
774 10 unneback
        .genpc_freeze(genpc_freeze),
775
        .if_freeze(if_freeze),
776
        .id_freeze(id_freeze),
777
        .ex_freeze(ex_freeze),
778
        .wb_freeze(wb_freeze),
779
        .icpu_ack_i(icpu_ack_i),
780
        .icpu_err_i(icpu_err_i)
781
);
782
 
783
//
784
// Instantiation of exception block
785
//
786
or1200_except or1200_except(
787
        .clk(clk),
788
        .rst(rst),
789
        .sig_ibuserr(except_ibuserr),
790
        .sig_dbuserr(except_dbuserr),
791
        .sig_illegal(except_illegal),
792
        .sig_align(except_align),
793
        .sig_range(1'b0),
794
        .sig_dtlbmiss(except_dtlbmiss),
795
        .sig_dmmufault(except_dmmufault),
796
        .sig_int(sig_int),
797
        .sig_syscall(sig_syscall),
798
        .sig_trap(sig_trap),
799
        .sig_itlbmiss(except_itlbmiss),
800
        .sig_immufault(except_immufault),
801
        .sig_tick(sig_tick),
802 185 julius
        .sig_fp(sig_fp),
803
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
804 141 marcus.erl
        .ex_branch_taken(ex_branch_taken),
805 10 unneback
        .icpu_ack_i(icpu_ack_i),
806
        .icpu_err_i(icpu_err_i),
807
        .dcpu_ack_i(dcpu_ack_i),
808
        .dcpu_err_i(dcpu_err_i),
809
        .genpc_freeze(genpc_freeze),
810
        .id_freeze(id_freeze),
811
        .ex_freeze(ex_freeze),
812
        .wb_freeze(wb_freeze),
813
        .if_stall(if_stall),
814
        .if_pc(if_pc),
815
        .id_pc(id_pc),
816 141 marcus.erl
        .ex_pc(ex_pc),
817
        .wb_pc(wb_pc),
818
        .id_flushpipe(id_flushpipe),
819
        .ex_flushpipe(ex_flushpipe),
820 10 unneback
        .extend_flush(extend_flush),
821 141 marcus.erl
        .except_flushpipe(except_flushpipe),
822
        .abort_mvspr(abort_mvspr),
823 10 unneback
        .except_type(except_type),
824
        .except_start(except_start),
825
        .except_started(except_started),
826
        .except_stop(except_stop),
827 141 marcus.erl
        .except_trig(except_trig),
828 10 unneback
        .ex_void(ex_void),
829
        .spr_dat_ppc(spr_dat_ppc),
830
        .spr_dat_npc(spr_dat_npc),
831
 
832 141 marcus.erl
        .datain(spr_dat_cpu),
833
        .branch_op(branch_op),
834 10 unneback
        .du_dsr(du_dsr),
835 141 marcus.erl
        .du_dmr1(du_dmr1),
836
        .du_hwbkpt(du_hwbkpt),
837
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
838 10 unneback
        .epcr_we(epcr_we),
839
        .eear_we(eear_we),
840
        .esr_we(esr_we),
841
        .pc_we(pc_we),
842
        .epcr(epcr),
843
        .eear(eear),
844
        .esr(esr),
845
 
846
        .lsu_addr(dcpu_adr_o),
847
        .sr_we(sr_we),
848
        .to_sr(to_sr),
849
        .sr(sr),
850
        .abort_ex(abort_ex)
851
);
852
 
853
//
854
// Instantiation of configuration registers
855
//
856
or1200_cfgr or1200_cfgr(
857
        .spr_addr(spr_addr),
858
        .spr_dat_o(spr_dat_cfgr)
859
);
860
 
861
endmodule

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