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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Instruction decode                                 ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Majority of instruction decoding is performed here.         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45 141 marcus.erl
// $Log: or1200_ctrl.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55 185 julius
module or1200_ctrl
56
  (
57
   // Clock and reset
58
   clk, rst,
59
 
60
   // Internal i/f
61
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
62
   wb_flushpipe,
63
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
64
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
65
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
66
   rf_addrw, rfwb_op, fpu_op,
67
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
68
   sel_b, id_lsu_op,
69
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
70
   multicycle, wbforw_valid, sig_syscall, sig_trap,
71
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
72
   ex_spr_write,
73
   id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal
74
   );
75 10 unneback
 
76
//
77
// I/O
78
//
79
input                                   clk;
80
input                                   rst;
81
input                                   id_freeze;
82
input                                   ex_freeze;
83
input                                   wb_freeze;
84 141 marcus.erl
output                                  if_flushpipe;
85
output                                  id_flushpipe;
86
output                                  ex_flushpipe;
87
output                                  wb_flushpipe;
88
input                                   extend_flush;
89
input                                   except_flushpipe;
90
input                           abort_mvspr ;
91
input   [31:0]                   if_insn;
92
output  [31:0]                   id_insn;
93
output  [31:0]                   ex_insn;
94
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
95
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
96
input                                           ex_branch_taken;
97 10 unneback
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
98
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
99
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
100
output                                  rf_rda;
101
output                                  rf_rdb;
102
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
103
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
104
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
105
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
106 185 julius
output [`OR1200_FPUOP_WIDTH-1:0]                 fpu_op;
107 141 marcus.erl
input                                   pc_we;
108 10 unneback
output  [31:0]                           wb_insn;
109 141 marcus.erl
output  [31:2]                          id_branch_addrtarget;
110
output  [31:2]                          ex_branch_addrtarget;
111 10 unneback
output  [`OR1200_SEL_WIDTH-1:0]          sel_a;
112
output  [`OR1200_SEL_WIDTH-1:0]          sel_b;
113 141 marcus.erl
output  [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
114 10 unneback
output  [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
115
output  [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
116
output  [4:0]                            cust5_op;
117
output  [5:0]                            cust5_limm;
118 141 marcus.erl
input   [31:0]                          id_pc;
119
input   [31:0]                          ex_pc;
120
output  [31:0]                           id_simm;
121
output  [31:0]                           ex_simm;
122 10 unneback
input                                   wbforw_valid;
123
input                                   du_hwbkpt;
124
output                                  sig_syscall;
125
output                                  sig_trap;
126
output                                  force_dslot_fetch;
127
output                                  no_more_dslot;
128 141 marcus.erl
output                                  id_void;
129 10 unneback
output                                  ex_void;
130 141 marcus.erl
output                                  ex_spr_read;
131
output                                  ex_spr_write;
132
output  [`OR1200_MACOP_WIDTH-1:0]        id_mac_op;
133 10 unneback
output                                  id_macrc_op;
134
output                                  ex_macrc_op;
135
output                                  rfe;
136
output                                  except_illegal;
137
 
138
//
139
// Internal wires and regs
140
//
141 141 marcus.erl
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
142
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
143 10 unneback
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
144 141 marcus.erl
wire                                    if_maci_op;
145 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
146 141 marcus.erl
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
147
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
148
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
149 10 unneback
reg                                     ex_macrc_op;
150
`else
151
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
152
wire                                    ex_macrc_op;
153
`endif
154
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
155
reg     [31:0]                           id_insn;
156
reg     [31:0]                           ex_insn;
157
reg     [31:0]                           wb_insn;
158
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
159
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
160
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
161
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
162
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
163
reg                                     sel_imm;
164 141 marcus.erl
reg     [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
165 10 unneback
reg     [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
166
reg     [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
167 141 marcus.erl
reg     [31:0]                           id_simm;
168
reg     [31:0]                           ex_simm;
169 10 unneback
reg                                     sig_syscall;
170
reg                                     sig_trap;
171
reg                                     except_illegal;
172
wire                                    id_void;
173 141 marcus.erl
wire                                    ex_void;
174
wire                                    wb_void;
175
reg                                     ex_delayslot_dsi;
176
reg                                     ex_delayslot_nop;
177
reg                                     spr_read;
178
reg                                     spr_write;
179
reg     [31:2]                          ex_branch_addrtarget;
180 10 unneback
 
181
//
182
// Register file read addresses
183
//
184
assign rf_addra = if_insn[20:16];
185
assign rf_addrb = if_insn[15:11];
186 141 marcus.erl
assign rf_rda = if_insn[31] || if_maci_op;
187 10 unneback
assign rf_rdb = if_insn[30];
188
 
189
//
190
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
191
// instructions
192
//
193
assign force_dslot_fetch = 1'b0;
194 141 marcus.erl
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
195
 
196 10 unneback
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
197
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
198 141 marcus.erl
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
199 10 unneback
 
200 141 marcus.erl
assign ex_spr_write = spr_write && !abort_mvspr;
201
assign ex_spr_read = spr_read && !abort_mvspr;
202
 
203 10 unneback
//
204 141 marcus.erl
// ex_delayslot_dsi: delay slot insn is in EX stage
205
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
206 10 unneback
//
207 141 marcus.erl
//  ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
208
//  !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage, 
209
//       next different is DS insn, previous different was Jump/Branch
210
//  !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
211
//
212
always @(posedge clk or posedge rst) begin
213
        if (rst) begin
214
                ex_delayslot_nop <= #1 1'b0;
215
                ex_delayslot_dsi <= #1 1'b0;
216
        end
217
        else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
218
                ex_delayslot_nop <= #1 id_void;
219
                ex_delayslot_dsi <= #1 !id_void;
220
        end
221
        else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
222
                ex_delayslot_nop <= #1 1'b0;
223
                ex_delayslot_dsi <= #1 1'b0;
224
        end
225
        else if (!ex_freeze) begin
226
                ex_delayslot_nop <= #1 id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
227
                                                                (ex_branch_op != `OR1200_BRANCHOP_RFE);
228
                ex_delayslot_dsi <= #1 !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
229
                                                                 (ex_branch_op != `OR1200_BRANCHOP_RFE);
230
        end
231
end
232 10 unneback
 
233
//
234 141 marcus.erl
// Flush pipeline
235 10 unneback
//
236 141 marcus.erl
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
237
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
238
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
239
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
240 10 unneback
 
241
//
242 141 marcus.erl
// EX Sign/Zero extension of immediates
243
//
244
always @(posedge clk or posedge rst) begin
245
        if (rst)
246
                ex_simm <= #1 32'h0000_0000;
247
        else if (!ex_freeze) begin
248
                ex_simm <= #1 id_simm;
249
        end
250
end
251
 
252
//
253
// ID Sign/Zero extension of immediate
254
//
255
always @(id_insn) begin
256
        case (id_insn[31:26])     // synopsys parallel_case
257
 
258
        // l.addi
259
        `OR1200_OR32_ADDI:
260
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
261
 
262
        // l.addic
263
        `OR1200_OR32_ADDIC:
264
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
265
 
266
        // l.lxx (load instructions)
267
        `OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
268
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
269
 
270
        // l.muli
271
        `ifdef OR1200_MULT_IMPLEMENTED
272
        `OR1200_OR32_MULI:
273
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
274
        `endif
275
 
276
        // l.maci
277
        `ifdef OR1200_MAC_IMPLEMENTED
278
        `OR1200_OR32_MACI:
279
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
280
        `endif
281
 
282
        // l.mtspr
283
        `OR1200_OR32_MTSPR:
284
                id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
285
 
286
        // l.sxx (store instructions)
287
        `OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
288
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
289
 
290
        // l.xori
291
        `OR1200_OR32_XORI:
292
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
293
 
294
        // l.sfxxi (SFXX with immediate)
295
        `OR1200_OR32_SFXXI:
296
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
297
 
298
        // Instructions with no or zero extended immediate
299
        default:
300
                id_simm = {{16'b0}, id_insn[15:0]};
301
 
302
        endcase
303
end
304
 
305
//
306
// ID Sign extension of branch offset
307
//
308
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
309
 
310
//
311
// EX Sign extension of branch offset
312
//
313
 
314
// pipeline ID and EX branch target address 
315
always @(posedge clk or posedge rst) begin
316
        if (rst)
317
                ex_branch_addrtarget <= #1 32'h00000000;
318
        else if (!ex_freeze)
319
                ex_branch_addrtarget <= #1 id_branch_addrtarget;
320
end
321
// not pipelined
322
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
323
 
324
//
325
// l.maci in IF stage
326
//
327
`ifdef OR1200_MAC_IMPLEMENTED
328
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
329
`else
330
assign if_maci_op = 1'b0;
331
`endif
332
 
333
//
334 10 unneback
// l.macrc in ID stage
335
//
336
`ifdef OR1200_MAC_IMPLEMENTED
337
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
338
`else
339
assign id_macrc_op = 1'b0;
340
`endif
341
 
342
//
343 141 marcus.erl
// l.macrc in EX stage
344
//
345
`ifdef OR1200_MAC_IMPLEMENTED
346
always @(posedge clk or posedge rst) begin
347
        if (rst)
348
                ex_macrc_op <= #1 1'b0;
349
        else if (!ex_freeze & id_freeze | ex_flushpipe)
350
                ex_macrc_op <= #1 1'b0;
351
        else if (!ex_freeze)
352
                ex_macrc_op <= #1 id_macrc_op;
353
end
354
`else
355
assign ex_macrc_op = 1'b0;
356
`endif
357
 
358
//
359 10 unneback
// cust5_op, cust5_limm (L immediate)
360
//
361
assign cust5_op = ex_insn[4:0];
362
assign cust5_limm = ex_insn[10:5];
363
 
364
//
365
//
366
//
367 141 marcus.erl
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
368 10 unneback
 
369
//
370
// Generation of sel_a
371
//
372
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
373
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
374
                sel_a = `OR1200_SEL_EX_FORW;
375
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
376
                sel_a = `OR1200_SEL_WB_FORW;
377
        else
378
                sel_a = `OR1200_SEL_RF;
379
 
380
//
381
// Generation of sel_b
382
//
383
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
384
        if (sel_imm)
385
                sel_b = `OR1200_SEL_IMM;
386
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
387
                sel_b = `OR1200_SEL_EX_FORW;
388
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
389
                sel_b = `OR1200_SEL_WB_FORW;
390
        else
391
                sel_b = `OR1200_SEL_RF;
392
 
393
//
394
// Decode of multicycle
395
//
396
always @(id_insn) begin
397
  case (id_insn[31:26])         // synopsys parallel_case
398
`ifdef UNUSED
399
    // l.lwz
400
    `OR1200_OR32_LWZ:
401
      multicycle = `OR1200_TWO_CYCLES;
402
 
403
    // l.lbz
404
    `OR1200_OR32_LBZ:
405
      multicycle = `OR1200_TWO_CYCLES;
406
 
407
    // l.lbs
408
    `OR1200_OR32_LBS:
409
      multicycle = `OR1200_TWO_CYCLES;
410
 
411
    // l.lhz
412
    `OR1200_OR32_LHZ:
413
      multicycle = `OR1200_TWO_CYCLES;
414
 
415
    // l.lhs
416
    `OR1200_OR32_LHS:
417
      multicycle = `OR1200_TWO_CYCLES;
418
 
419
    // l.sw
420
    `OR1200_OR32_SW:
421
      multicycle = `OR1200_TWO_CYCLES;
422
 
423
    // l.sb
424
    `OR1200_OR32_SB:
425
      multicycle = `OR1200_TWO_CYCLES;
426
 
427
    // l.sh
428
    `OR1200_OR32_SH:
429
      multicycle = `OR1200_TWO_CYCLES;
430
`endif
431 141 marcus.erl
    // l.mfspr
432
    `OR1200_OR32_MFSPR:
433
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
434
 
435 10 unneback
    // ALU instructions except the one with immediate
436
    `OR1200_OR32_ALU:
437 141 marcus.erl
        case (id_insn[3:0]) // synopsys parallel_case
438
        4'h6: multicycle = 2'b11; // l.mul
439
        4'h9: multicycle = 2'b10; // l.div
440
        4'hA: multicycle = 2'b10; // l.divu
441
        4'hB: multicycle = 2'b11; // l.mulu
442
        default: multicycle = 2'b00;
443
        endcase
444 10 unneback
 
445 141 marcus.erl
    `OR1200_OR32_MULI:
446
      multicycle = 2'h3;
447 185 julius
 
448
`ifdef OR1200_FPU_IMPLEMENTED
449
    `OR1200_OR32_FLOAT:
450
      multicycle = `OR1200_FPUOP_CYCLES;
451
`endif
452
 
453 141 marcus.erl
 
454 10 unneback
    // Single cycle instructions
455
    default: begin
456
      multicycle = `OR1200_ONE_CYCLE;
457
    end
458
 
459
  endcase
460
end
461
 
462
//
463
// Register file write address
464
//
465
always @(posedge clk or posedge rst) begin
466
        if (rst)
467
                rf_addrw <= #1 5'd0;
468
        else if (!ex_freeze & id_freeze)
469
                rf_addrw <= #1 5'd00;
470
        else if (!ex_freeze)
471 141 marcus.erl
                case (id_insn[31:26])   // synopsys parallel_case
472
                        `OR1200_OR32_JAL, `OR1200_OR32_JALR:
473 10 unneback
                                rf_addrw <= #1 5'd09;   // link register r9
474
                        default:
475
                                rf_addrw <= #1 id_insn[25:21];
476
                endcase
477
end
478
 
479
//
480
// rf_addrw in wb stage (used in forwarding logic)
481
//
482
always @(posedge clk or posedge rst) begin
483
        if (rst)
484
                wb_rfaddrw <= #1 5'd0;
485
        else if (!wb_freeze)
486
                wb_rfaddrw <= #1 rf_addrw;
487
end
488
 
489
//
490
// Instruction latch in id_insn
491
//
492
always @(posedge clk or posedge rst) begin
493
        if (rst)
494
                id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
495 141 marcus.erl
        else if (id_flushpipe)
496
                id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};        // NOP -> id_insn[16] must be 1
497 10 unneback
        else if (!id_freeze) begin
498
                id_insn <= #1 if_insn;
499
`ifdef OR1200_VERBOSE
500
// synopsys translate_off
501
                $display("%t: id_insn <= %h", $time, if_insn);
502
// synopsys translate_on
503
`endif
504
        end
505
end
506
 
507
//
508
// Instruction latch in ex_insn
509
//
510
always @(posedge clk or posedge rst) begin
511
        if (rst)
512
                ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
513 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
514
                ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
515 10 unneback
        else if (!ex_freeze) begin
516
                ex_insn <= #1 id_insn;
517
`ifdef OR1200_VERBOSE
518
// synopsys translate_off
519
                $display("%t: ex_insn <= %h", $time, id_insn);
520
// synopsys translate_on
521
`endif
522
        end
523
end
524
 
525
//
526
// Instruction latch in wb_insn
527
//
528
always @(posedge clk or posedge rst) begin
529
        if (rst)
530
                wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
531 141 marcus.erl
        // wb_insn should not be changed by exceptions due to correct 
532
        // recording of display_arch_state in the or1200_monitor! 
533
        // wb_insn changed by exception is not used elsewhere! 
534 10 unneback
        else if (!wb_freeze) begin
535
                wb_insn <= #1 ex_insn;
536
        end
537
end
538
 
539
//
540
// Decode of sel_imm
541
//
542
always @(posedge clk or posedge rst) begin
543
        if (rst)
544
                sel_imm <= #1 1'b0;
545
        else if (!id_freeze) begin
546
          case (if_insn[31:26])         // synopsys parallel_case
547
 
548
            // j.jalr
549
            `OR1200_OR32_JALR:
550
              sel_imm <= #1 1'b0;
551
 
552
            // l.jr
553
            `OR1200_OR32_JR:
554
              sel_imm <= #1 1'b0;
555
 
556
            // l.rfe
557
            `OR1200_OR32_RFE:
558
              sel_imm <= #1 1'b0;
559
 
560
            // l.mfspr
561
            `OR1200_OR32_MFSPR:
562
              sel_imm <= #1 1'b0;
563
 
564
            // l.mtspr
565
            `OR1200_OR32_MTSPR:
566
              sel_imm <= #1 1'b0;
567
 
568
            // l.sys, l.brk and all three sync insns
569
            `OR1200_OR32_XSYNC:
570
              sel_imm <= #1 1'b0;
571
 
572
            // l.mac/l.msb
573
`ifdef OR1200_MAC_IMPLEMENTED
574
            `OR1200_OR32_MACMSB:
575
              sel_imm <= #1 1'b0;
576
`endif
577
 
578
            // l.sw
579
            `OR1200_OR32_SW:
580
              sel_imm <= #1 1'b0;
581
 
582
            // l.sb
583
            `OR1200_OR32_SB:
584
              sel_imm <= #1 1'b0;
585
 
586
            // l.sh
587
            `OR1200_OR32_SH:
588
              sel_imm <= #1 1'b0;
589
 
590
            // ALU instructions except the one with immediate
591
            `OR1200_OR32_ALU:
592
              sel_imm <= #1 1'b0;
593
 
594
            // SFXX instructions
595
            `OR1200_OR32_SFXX:
596
              sel_imm <= #1 1'b0;
597
 
598
`ifdef OR1200_OR32_CUST5
599
            // l.cust5 instructions
600
            `OR1200_OR32_CUST5:
601
              sel_imm <= #1 1'b0;
602
`endif
603 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
604
            // FPU instructions
605
            `OR1200_OR32_FLOAT:
606
              sel_imm <= #1 1'b0;
607
`endif
608 10 unneback
            // l.nop
609
            `OR1200_OR32_NOP:
610
              sel_imm <= #1 1'b0;
611
 
612
            // All instructions with immediates
613
            default: begin
614
              sel_imm <= #1 1'b1;
615
            end
616
 
617
          endcase
618
 
619
        end
620
end
621
 
622
//
623
// Decode of except_illegal
624
//
625
always @(posedge clk or posedge rst) begin
626
        if (rst)
627
                except_illegal <= #1 1'b0;
628 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
629 10 unneback
                except_illegal <= #1 1'b0;
630
        else if (!ex_freeze) begin
631 141 marcus.erl
                case (id_insn[31:26])           // synopsys parallel_case
632 10 unneback
 
633 141 marcus.erl
                `OR1200_OR32_J,
634
                `OR1200_OR32_JAL,
635
                `OR1200_OR32_JALR,
636
                `OR1200_OR32_JR,
637
                `OR1200_OR32_BNF,
638
                `OR1200_OR32_BF,
639
                `OR1200_OR32_RFE,
640
                `OR1200_OR32_MOVHI,
641
                `OR1200_OR32_MFSPR,
642
                `OR1200_OR32_XSYNC,
643 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
644 141 marcus.erl
                `OR1200_OR32_MACI,
645 10 unneback
`endif
646 141 marcus.erl
                `OR1200_OR32_LWZ,
647
                `OR1200_OR32_LBZ,
648
                `OR1200_OR32_LBS,
649
                `OR1200_OR32_LHZ,
650
                `OR1200_OR32_LHS,
651
                `OR1200_OR32_ADDI,
652
                `OR1200_OR32_ADDIC,
653
                `OR1200_OR32_ANDI,
654
                `OR1200_OR32_ORI,
655
                `OR1200_OR32_XORI,
656 10 unneback
`ifdef OR1200_MULT_IMPLEMENTED
657 141 marcus.erl
                `OR1200_OR32_MULI,
658 10 unneback
`endif
659 141 marcus.erl
                `OR1200_OR32_SH_ROTI,
660
                `OR1200_OR32_SFXXI,
661
                `OR1200_OR32_MTSPR,
662 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
663 141 marcus.erl
                `OR1200_OR32_MACMSB,
664 10 unneback
`endif
665 141 marcus.erl
                `OR1200_OR32_SW,
666
                `OR1200_OR32_SB,
667
                `OR1200_OR32_SH,
668
                `OR1200_OR32_SFXX,
669 10 unneback
`ifdef OR1200_OR32_CUST5
670 141 marcus.erl
                `OR1200_OR32_CUST5,
671 10 unneback
`endif
672 141 marcus.erl
        `OR1200_OR32_NOP:
673
                        except_illegal <= #1 1'b0;
674 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
675
            `OR1200_OR32_FLOAT:
676
                        // Check it's not a double precision instruction
677
                        except_illegal <= #1 id_insn[`OR1200_FPUOP_DOUBLE_BIT];
678
`endif
679 10 unneback
 
680 141 marcus.erl
        `OR1200_OR32_ALU:
681
                        except_illegal <= #1 1'b0
682 10 unneback
 
683 141 marcus.erl
`ifdef OR1200_MULT_IMPLEMENTED
684
`ifdef OR1200_IMPL_DIV
685
`else
686
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
687
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
688
`endif
689
`else
690
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
691
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
692
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
693
`endif
694
 
695
`ifdef OR1200_IMPL_ADDC
696
`else
697
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
698
`endif
699
 
700
`ifdef OR1200_IMPL_ALU_ROTATE
701
`else
702
                                | (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
703
`endif
704
 
705
`ifdef OR1200_IMPL_SUB
706
`else
707
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
708
`endif
709
                                ;
710
 
711
                // Illegal and OR1200 unsupported instructions
712
                default:
713
                        except_illegal <= #1 1'b1;
714
 
715
                endcase
716 10 unneback
 
717
        end
718
end
719
 
720
//
721
// Decode of alu_op
722
//
723
always @(posedge clk or posedge rst) begin
724
        if (rst)
725
                alu_op <= #1 `OR1200_ALUOP_NOP;
726 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
727 10 unneback
                alu_op <= #1 `OR1200_ALUOP_NOP;
728
        else if (!ex_freeze) begin
729
          case (id_insn[31:26])         // synopsys parallel_case
730
 
731
            // l.movhi
732
            `OR1200_OR32_MOVHI:
733
              alu_op <= #1 `OR1200_ALUOP_MOVHI;
734
 
735
            // l.addi
736
            `OR1200_OR32_ADDI:
737
              alu_op <= #1 `OR1200_ALUOP_ADD;
738
 
739
            // l.addic
740
            `OR1200_OR32_ADDIC:
741
              alu_op <= #1 `OR1200_ALUOP_ADDC;
742
 
743
            // l.andi
744
            `OR1200_OR32_ANDI:
745
              alu_op <= #1 `OR1200_ALUOP_AND;
746
 
747
            // l.ori
748
            `OR1200_OR32_ORI:
749
              alu_op <= #1 `OR1200_ALUOP_OR;
750
 
751
            // l.xori
752
            `OR1200_OR32_XORI:
753
              alu_op <= #1 `OR1200_ALUOP_XOR;
754
 
755
            // l.muli
756
`ifdef OR1200_MULT_IMPLEMENTED
757
            `OR1200_OR32_MULI:
758
              alu_op <= #1 `OR1200_ALUOP_MUL;
759
`endif
760
 
761
            // Shift and rotate insns with immediate
762
            `OR1200_OR32_SH_ROTI:
763
              alu_op <= #1 `OR1200_ALUOP_SHROT;
764
 
765
            // SFXX insns with immediate
766
            `OR1200_OR32_SFXXI:
767
              alu_op <= #1 `OR1200_ALUOP_COMP;
768
 
769
            // ALU instructions except the one with immediate
770
            `OR1200_OR32_ALU:
771
              alu_op <= #1 id_insn[3:0];
772
 
773
            // SFXX instructions
774
            `OR1200_OR32_SFXX:
775
              alu_op <= #1 `OR1200_ALUOP_COMP;
776
 
777
`ifdef OR1200_OR32_CUST5
778
            // l.cust5 instructions
779
            `OR1200_OR32_CUST5:
780
              alu_op <= #1 `OR1200_ALUOP_CUST5;
781
`endif
782
 
783
            // Default
784
            default: begin
785
              alu_op <= #1 `OR1200_ALUOP_NOP;
786
            end
787
 
788
          endcase
789
 
790
        end
791
end
792
 
793
//
794 141 marcus.erl
// Decode of spr_read, spr_write
795
//
796
always @(posedge clk or posedge rst) begin
797
        if (rst) begin
798
                spr_read <= #1 1'b0;
799
                spr_write <= #1 1'b0;
800
        end
801
        else if (!ex_freeze & id_freeze | ex_flushpipe) begin
802
                spr_read <= #1 1'b0;
803
                spr_write <= #1 1'b0;
804
        end
805
        else if (!ex_freeze) begin
806
                case (id_insn[31:26])     // synopsys parallel_case
807
 
808
                // l.mfspr
809
                `OR1200_OR32_MFSPR: begin
810
                        spr_read <= #1 1'b1;
811
                        spr_write <= #1 1'b0;
812
                end
813
 
814
                // l.mtspr
815
                `OR1200_OR32_MTSPR: begin
816
                        spr_read <= #1 1'b0;
817
                        spr_write <= #1 1'b1;
818
                end
819
 
820
                // Default
821
                default: begin
822
                        spr_read <= #1 1'b0;
823
                        spr_write <= #1 1'b0;
824
                end
825
 
826
                endcase
827
        end
828
end
829
 
830
//
831 10 unneback
// Decode of mac_op
832
//
833
`ifdef OR1200_MAC_IMPLEMENTED
834 141 marcus.erl
always @(id_insn) begin
835
        case (id_insn[31:26])           // synopsys parallel_case
836 10 unneback
 
837 141 marcus.erl
        // l.maci
838
        `OR1200_OR32_MACI:
839
                id_mac_op <= #1 `OR1200_MACOP_MAC;
840 10 unneback
 
841 141 marcus.erl
        // l.mac, l.msb
842
        `OR1200_OR32_MACMSB:
843
                id_mac_op <= #1 id_insn[2:0];
844 10 unneback
 
845 141 marcus.erl
        // Illegal and OR1200 unsupported instructions
846
        default:
847
                id_mac_op <= #1 `OR1200_MACOP_NOP;
848 10 unneback
 
849 141 marcus.erl
        endcase
850 10 unneback
end
851 141 marcus.erl
 
852
always @(posedge clk or posedge rst) begin
853
        if (rst)
854
                ex_mac_op <= #1 `OR1200_MACOP_NOP;
855
        else if (!ex_freeze & id_freeze | ex_flushpipe)
856
                ex_mac_op <= #1 `OR1200_MACOP_NOP;
857
        else if (!ex_freeze)
858
                ex_mac_op <= #1 id_mac_op;
859
end
860
 
861
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
862 10 unneback
`else
863 141 marcus.erl
assign id_mac_op = `OR1200_MACOP_NOP;
864 10 unneback
assign mac_op = `OR1200_MACOP_NOP;
865
`endif
866
 
867
//
868
// Decode of shrot_op
869
//
870
always @(posedge clk or posedge rst) begin
871
        if (rst)
872
                shrot_op <= #1 `OR1200_SHROTOP_NOP;
873 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
874 10 unneback
                shrot_op <= #1 `OR1200_SHROTOP_NOP;
875
        else if (!ex_freeze) begin
876
                shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
877
        end
878
end
879
 
880
//
881
// Decode of rfwb_op
882
//
883
always @(posedge clk or posedge rst) begin
884
        if (rst)
885
                rfwb_op <= #1 `OR1200_RFWBOP_NOP;
886 141 marcus.erl
        else  if (!ex_freeze & id_freeze | ex_flushpipe)
887 10 unneback
                rfwb_op <= #1 `OR1200_RFWBOP_NOP;
888
        else  if (!ex_freeze) begin
889
                case (id_insn[31:26])           // synopsys parallel_case
890
 
891 141 marcus.erl
                // j.jal
892
                `OR1200_OR32_JAL:
893 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
894 10 unneback
 
895 141 marcus.erl
                // j.jalr
896
                `OR1200_OR32_JALR:
897 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LR, 1'b1};
898 10 unneback
 
899 141 marcus.erl
                // l.movhi
900
                `OR1200_OR32_MOVHI:
901 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
902 10 unneback
 
903 141 marcus.erl
                // l.mfspr
904
                `OR1200_OR32_MFSPR:
905 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_SPRS, 1'b1};
906 10 unneback
 
907 141 marcus.erl
                // l.lwz
908
                `OR1200_OR32_LWZ:
909 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
910 10 unneback
 
911 141 marcus.erl
                // l.lbz
912
                `OR1200_OR32_LBZ:
913 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
914 10 unneback
 
915 141 marcus.erl
                // l.lbs
916
                `OR1200_OR32_LBS:
917 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
918 10 unneback
 
919 141 marcus.erl
                // l.lhz
920
                `OR1200_OR32_LHZ:
921 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
922 10 unneback
 
923 141 marcus.erl
                // l.lhs
924
                `OR1200_OR32_LHS:
925 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_LSU, 1'b1};
926 10 unneback
 
927 141 marcus.erl
                // l.addi
928
                `OR1200_OR32_ADDI:
929 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
930 10 unneback
 
931 141 marcus.erl
                // l.addic
932
                `OR1200_OR32_ADDIC:
933 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
934 10 unneback
 
935 141 marcus.erl
                // l.andi
936
                `OR1200_OR32_ANDI:
937 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
938 10 unneback
 
939 141 marcus.erl
                // l.ori
940
                `OR1200_OR32_ORI:
941 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
942 10 unneback
 
943 141 marcus.erl
                // l.xori
944
                `OR1200_OR32_XORI:
945 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
946 10 unneback
 
947 141 marcus.erl
                // l.muli
948 10 unneback
`ifdef OR1200_MULT_IMPLEMENTED
949 141 marcus.erl
                `OR1200_OR32_MULI:
950 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
951 10 unneback
`endif
952
 
953 141 marcus.erl
                // Shift and rotate insns with immediate
954
                `OR1200_OR32_SH_ROTI:
955 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
956 10 unneback
 
957 141 marcus.erl
                // ALU instructions except the one with immediate
958
                `OR1200_OR32_ALU:
959 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
960 10 unneback
 
961
`ifdef OR1200_OR32_CUST5
962 141 marcus.erl
                // l.cust5 instructions
963
                `OR1200_OR32_CUST5:
964 186 julius
                        rfwb_op <= #1 {`OR1200_RFWBOP_ALU, 1'b1};
965 10 unneback
`endif
966 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
967
                  // FPU instructions, lf.XXX.s, except sfxx
968
                  `OR1200_OR32_FLOAT:
969
                    rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]};
970
`endif
971 141 marcus.erl
                // Instructions w/o register-file write-back
972
                default:
973
                        rfwb_op <= #1 `OR1200_RFWBOP_NOP;
974 10 unneback
 
975 141 marcus.erl
 
976 10 unneback
                endcase
977
        end
978
end
979
 
980
//
981 141 marcus.erl
// Decode of id_branch_op
982 10 unneback
//
983
always @(posedge clk or posedge rst) begin
984
        if (rst)
985 141 marcus.erl
                id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
986
        else if (id_flushpipe)
987
                id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
988 10 unneback
        else if (!id_freeze) begin
989
                case (if_insn[31:26])           // synopsys parallel_case
990 141 marcus.erl
 
991
                // l.j
992
                `OR1200_OR32_J:
993
                        id_branch_op <= #1 `OR1200_BRANCHOP_J;
994 10 unneback
 
995 141 marcus.erl
                // j.jal
996
                `OR1200_OR32_JAL:
997
                        id_branch_op <= #1 `OR1200_BRANCHOP_J;
998 10 unneback
 
999 141 marcus.erl
                // j.jalr
1000
                `OR1200_OR32_JALR:
1001
                        id_branch_op <= #1 `OR1200_BRANCHOP_JR;
1002 10 unneback
 
1003 141 marcus.erl
                // l.jr
1004
                `OR1200_OR32_JR:
1005
                        id_branch_op <= #1 `OR1200_BRANCHOP_JR;
1006 10 unneback
 
1007 141 marcus.erl
                // l.bnf
1008
                `OR1200_OR32_BNF:
1009
                        id_branch_op <= #1 `OR1200_BRANCHOP_BNF;
1010 10 unneback
 
1011 141 marcus.erl
                // l.bf
1012
                `OR1200_OR32_BF:
1013
                        id_branch_op <= #1 `OR1200_BRANCHOP_BF;
1014 10 unneback
 
1015 141 marcus.erl
                // l.rfe
1016
                `OR1200_OR32_RFE:
1017
                        id_branch_op <= #1 `OR1200_BRANCHOP_RFE;
1018 10 unneback
 
1019 141 marcus.erl
                // Non branch instructions
1020
                default:
1021
                        id_branch_op <= #1 `OR1200_BRANCHOP_NOP;
1022
 
1023 10 unneback
                endcase
1024
        end
1025
end
1026
 
1027
//
1028 141 marcus.erl
// Generation of ex_branch_op
1029 10 unneback
//
1030
always @(posedge clk or posedge rst)
1031
        if (rst)
1032 141 marcus.erl
                ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
1033
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1034
                ex_branch_op <= #1 `OR1200_BRANCHOP_NOP;
1035 10 unneback
        else if (!ex_freeze)
1036 141 marcus.erl
                ex_branch_op <= #1 id_branch_op;
1037 10 unneback
 
1038
//
1039 141 marcus.erl
// Decode of id_lsu_op
1040 10 unneback
//
1041 141 marcus.erl
always @(id_insn) begin
1042
        case (id_insn[31:26])           // synopsys parallel_case
1043
 
1044
        // l.lwz
1045
        `OR1200_OR32_LWZ:
1046
                id_lsu_op <= #1 `OR1200_LSUOP_LWZ;
1047
 
1048
        // l.lbz
1049
        `OR1200_OR32_LBZ:
1050
                id_lsu_op <= #1 `OR1200_LSUOP_LBZ;
1051
 
1052
        // l.lbs
1053
        `OR1200_OR32_LBS:
1054
                id_lsu_op <= #1 `OR1200_LSUOP_LBS;
1055
 
1056
        // l.lhz
1057
        `OR1200_OR32_LHZ:
1058
                id_lsu_op <= #1 `OR1200_LSUOP_LHZ;
1059
 
1060
        // l.lhs
1061
        `OR1200_OR32_LHS:
1062
                id_lsu_op <= #1 `OR1200_LSUOP_LHS;
1063
 
1064
        // l.sw
1065
        `OR1200_OR32_SW:
1066
                id_lsu_op <= #1 `OR1200_LSUOP_SW;
1067
 
1068
        // l.sb
1069
        `OR1200_OR32_SB:
1070
                id_lsu_op <= #1 `OR1200_LSUOP_SB;
1071
 
1072
        // l.sh
1073
        `OR1200_OR32_SH:
1074
                id_lsu_op <= #1 `OR1200_LSUOP_SH;
1075
 
1076
        // Non load/store instructions
1077
        default:
1078
                id_lsu_op <= #1 `OR1200_LSUOP_NOP;
1079
 
1080
        endcase
1081 10 unneback
end
1082
 
1083
//
1084
// Decode of comp_op
1085
//
1086
always @(posedge clk or posedge rst) begin
1087
        if (rst) begin
1088
                comp_op <= #1 4'd0;
1089 141 marcus.erl
        end else if (!ex_freeze & id_freeze | ex_flushpipe)
1090 10 unneback
                comp_op <= #1 4'd0;
1091
        else if (!ex_freeze)
1092
                comp_op <= #1 id_insn[24:21];
1093
end
1094
 
1095 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
1096 10 unneback
//
1097 185 julius
// Decode of FPU ops
1098
//
1099
   assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT), id_insn[`OR1200_FPUOP_WIDTH-2:0]};
1100
`else
1101
   assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
1102
`endif
1103
 
1104
 
1105
//
1106 10 unneback
// Decode of l.sys
1107
//
1108
always @(posedge clk or posedge rst) begin
1109
        if (rst)
1110
                sig_syscall <= #1 1'b0;
1111 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1112 10 unneback
                sig_syscall <= #1 1'b0;
1113
        else if (!ex_freeze) begin
1114
`ifdef OR1200_VERBOSE
1115
// synopsys translate_off
1116
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
1117
                        $display("Generating sig_syscall");
1118
// synopsys translate_on
1119
`endif
1120
                sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
1121
        end
1122
end
1123
 
1124
//
1125
// Decode of l.trap
1126
//
1127
always @(posedge clk or posedge rst) begin
1128
        if (rst)
1129
                sig_trap <= #1 1'b0;
1130 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1131 10 unneback
                sig_trap <= #1 1'b0;
1132
        else if (!ex_freeze) begin
1133
`ifdef OR1200_VERBOSE
1134
// synopsys translate_off
1135
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1136
                        $display("Generating sig_trap");
1137
// synopsys translate_on
1138
`endif
1139
                sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1140
                        | du_hwbkpt;
1141
        end
1142
end
1143
 
1144
endmodule

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