URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Blame information for rev 294

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction decode                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Majority of instruction decoding is performed here.         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_ctrl.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_ctrl
  (
   // Clock and reset
   clk, rst,
 
   // Internal i/f
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
   wb_flushpipe,
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
   rf_addrw, rfwb_op, fpu_op,
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
   sel_b, id_lsu_op,
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
   ex_spr_write,
   id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
   );
 
//
// I/O
//
input                                   clk;
input                                   rst;
input                                   id_freeze;
input                                   ex_freeze;
input                                   wb_freeze;
output                                  if_flushpipe;
output                                  id_flushpipe;
output                                  ex_flushpipe;
output                                  wb_flushpipe;
input                                   extend_flush;
input                                   except_flushpipe;
input                           abort_mvspr ;
input   [31:0]                   if_insn;
output  [31:0]                   id_insn;
output  [31:0]                   ex_insn;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
input                                           ex_branch_taken;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output                                  rf_rda;
output                                  rf_rdb;
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
input                                   pc_we;
output  [31:0]                           wb_insn;
output  [31:2]                          id_branch_addrtarget;
output  [31:2]                          ex_branch_addrtarget;
output  [`OR1200_SEL_WIDTH-1:0]          sel_a;
output  [`OR1200_SEL_WIDTH-1:0]          sel_b;
output  [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
output  [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
output  [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
output  [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
output  [4:0]                            cust5_op;
output  [5:0]                            cust5_limm;
input   [31:0]                          id_pc;
input   [31:0]                          ex_pc;
output  [31:0]                           id_simm;
output  [31:0]                           ex_simm;
input                                   wbforw_valid;
input                                   du_hwbkpt;
output                                  sig_syscall;
output                                  sig_trap;
output                                  force_dslot_fetch;
output                                  no_more_dslot;
output                                  id_void;
output                                  ex_void;
output                                  ex_spr_read;
output                                  ex_spr_write;
output  [`OR1200_MACOP_WIDTH-1:0]        id_mac_op;
output                                  id_macrc_op;
output                                  ex_macrc_op;
output                                  rfe;
output                                  except_illegal;
output                                  dc_no_writethrough;
 
 
//
// Internal wires and regs
//
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
wire                                    if_maci_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
reg                                     ex_macrc_op;
`else
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
wire                                    ex_macrc_op;
`endif
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
reg     [31:0]                           id_insn;
reg     [31:0]                           ex_insn;
reg     [31:0]                           wb_insn;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
reg                                     sel_imm;
reg     [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
reg     [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
reg     [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
reg     [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
reg     [31:0]                           id_simm;
reg     [31:0]                           ex_simm;
reg                                     sig_syscall;
reg                                     sig_trap;
reg                                     except_illegal;
wire                                    id_void;
wire                                    ex_void;
wire                                    wb_void;
reg                                     ex_delayslot_dsi;
reg                                     ex_delayslot_nop;
reg                                     spr_read;
reg                                     spr_write;
reg     [31:2]                          ex_branch_addrtarget;
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
reg                                     dc_no_writethrough;
`endif
 
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
assign rf_rda = if_insn[31] || if_maci_op;
assign rf_rdb = if_insn[30];
 
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
assign force_dslot_fetch = 1'b0;
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
 
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
 
assign ex_spr_write = spr_write && !abort_mvspr;
assign ex_spr_read = spr_read && !abort_mvspr;
 
//
// ex_delayslot_dsi: delay slot insn is in EX stage
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
//
//  ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
//  !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage, 
//       next different is DS insn, previous different was Jump/Branch
//  !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_delayslot_nop <=  1'b0;
                ex_delayslot_dsi <=  1'b0;
        end
        else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
                ex_delayslot_nop <=  id_void;
                ex_delayslot_dsi <=  !id_void;
        end
        else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
                ex_delayslot_nop <=  1'b0;
                ex_delayslot_dsi <=  1'b0;
        end
        else if (!ex_freeze) begin
                ex_delayslot_nop <=  id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
                                                                (ex_branch_op != `OR1200_BRANCHOP_RFE);
                ex_delayslot_dsi <=  !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
                                                                 (ex_branch_op != `OR1200_BRANCHOP_RFE);
        end
end
 
//
// Flush pipeline
//
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// EX Sign/Zero extension of immediates
//
always @(posedge clk or posedge rst) begin
        if (rst)
                ex_simm <=  32'h0000_0000;
        else if (!ex_freeze) begin
                ex_simm <=  id_simm;
        end
end
 
//
// ID Sign/Zero extension of immediate
//
always @(id_insn) begin
        case (id_insn[31:26])     // synopsys parallel_case
 
        // l.addi
        `OR1200_OR32_ADDI:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
 
        // l.addic
        `OR1200_OR32_ADDIC:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
 
        // l.lxx (load instructions)
        `OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
 
        // l.muli
        `ifdef OR1200_MULT_IMPLEMENTED
        `OR1200_OR32_MULI:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
        `endif
 
        // l.maci
        `ifdef OR1200_MAC_IMPLEMENTED
        `OR1200_OR32_MACI:
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
        `endif
 
        // l.mtspr
        `OR1200_OR32_MTSPR:
                id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
 
        // l.sxx (store instructions)
        `OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
 
        // l.xori
        `OR1200_OR32_XORI:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
 
        // l.sfxxi (SFXX with immediate)
        `OR1200_OR32_SFXXI:
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
 
        // Instructions with no or zero extended immediate
        default:
                id_simm = {{16'b0}, id_insn[15:0]};
 
        endcase
end
 
//
// ID Sign extension of branch offset
//
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
 
//
// EX Sign extension of branch offset
//
 
// pipeline ID and EX branch target address 
always @(posedge clk or posedge rst) begin
        if (rst)
                ex_branch_addrtarget <=  32'h00000000;
        else if (!ex_freeze)
                ex_branch_addrtarget <=  id_branch_addrtarget;
end
// not pipelined
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
 
//
// l.maci in IF stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
`else
assign if_maci_op = 1'b0;
`endif
 
//
// l.macrc in ID stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
`else
assign id_macrc_op = 1'b0;
`endif
 
//
// l.macrc in EX stage
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or posedge rst) begin
        if (rst)
                ex_macrc_op <=  1'b0;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                ex_macrc_op <=  1'b0;
        else if (!ex_freeze)
                ex_macrc_op <=  id_macrc_op;
end
`else
assign ex_macrc_op = 1'b0;
`endif
 
//
// cust5_op, cust5_limm (L immediate)
//
assign cust5_op = ex_insn[4:0];
assign cust5_limm = ex_insn[10:5];
 
//
//
//
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
 
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
                sel_a = `OR1200_SEL_EX_FORW;
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
                sel_a = `OR1200_SEL_WB_FORW;
        else
                sel_a = `OR1200_SEL_RF;
 
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
        if (sel_imm)
                sel_b = `OR1200_SEL_IMM;
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
                sel_b = `OR1200_SEL_EX_FORW;
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
                sel_b = `OR1200_SEL_WB_FORW;
        else
                sel_b = `OR1200_SEL_RF;
 
//
// Decode of multicycle
//
always @(id_insn) begin
  case (id_insn[31:26])         // synopsys parallel_case
`ifdef UNUSED
    // l.lwz
    `OR1200_OR32_LWZ:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.lbz
    `OR1200_OR32_LBZ:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.lbs
    `OR1200_OR32_LBS:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.lhz
    `OR1200_OR32_LHZ:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.lhs
    `OR1200_OR32_LHS:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.sw
    `OR1200_OR32_SW:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.sb
    `OR1200_OR32_SB:
      multicycle = `OR1200_TWO_CYCLES;
 
    // l.sh
    `OR1200_OR32_SH:
      multicycle = `OR1200_TWO_CYCLES;
`endif
    // l.mfspr
    `OR1200_OR32_MFSPR:
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
 
    // ALU instructions except the one with immediate
    `OR1200_OR32_ALU:
        case (id_insn[3:0]) // synopsys parallel_case
        4'h6: multicycle = 2'b11; // l.mul
        4'h9: multicycle = 2'b10; // l.div
        4'hA: multicycle = 2'b10; // l.divu
        4'hB: multicycle = 2'b11; // l.mulu
        default: multicycle = 2'b00;
        endcase
 
    `OR1200_OR32_MULI:
      multicycle = 2'h3;
 
    // Single cycle instructions
    default: begin
      multicycle = `OR1200_ONE_CYCLE;
    end
  endcase
end // always @ (id_insn)
 
//
// Encode wait_on signal
//    
always @(id_insn) begin
   case (id_insn[31:26])                // synopsys parallel_case
`ifdef OR1200_FPU_IMPLEMENTED
       `OR1200_OR32_FLOAT: begin
         wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
       end
`endif
`ifndef OR1200_DC_WRITHROUGH
     // l.mtspr
     `OR1200_OR32_MTSPR: begin
        wait_on = `OR1200_WAIT_ON_MTSPR;
     end
`endif
     default: begin
        wait_on = 0;
     end
   endcase // case (id_insn[31:26])
end // always @ (id_insn)
 
 
 
 
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rf_addrw <=  5'd0;
        else if (!ex_freeze & id_freeze)
                rf_addrw <=  5'd00;
        else if (!ex_freeze)
                case (id_insn[31:26])   // synopsys parallel_case
                        `OR1200_OR32_JAL, `OR1200_OR32_JALR:
                                rf_addrw <=  5'd09;     // link register r9
                        default:
                                rf_addrw <=  id_insn[25:21];
                endcase
end
 
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_rfaddrw <=  5'd0;
        else if (!wb_freeze)
                wb_rfaddrw <=  rf_addrw;
end
 
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
        if (rst)
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (id_flushpipe)
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};        // NOP -> id_insn[16] must be 1
        else if (!id_freeze) begin
                id_insn <=  if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
        if (rst)
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};   // NOP -> ex_insn[16] must be 1
        else if (!ex_freeze) begin
                ex_insn <=  id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
        end
end
 
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
        if (rst)
                wb_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
        // wb_insn should not be changed by exceptions due to correct 
        // recording of display_arch_state in the or1200_monitor! 
        // wb_insn changed by exception is not used elsewhere! 
        else if (!wb_freeze) begin
                wb_insn <=  ex_insn;
        end
end
 
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sel_imm <=  1'b0;
        else if (!id_freeze) begin
          case (if_insn[31:26])         // synopsys parallel_case
 
            // j.jalr
            `OR1200_OR32_JALR:
              sel_imm <=  1'b0;
 
            // l.jr
            `OR1200_OR32_JR:
              sel_imm <=  1'b0;
 
            // l.rfe
            `OR1200_OR32_RFE:
              sel_imm <=  1'b0;
 
            // l.mfspr
            `OR1200_OR32_MFSPR:
              sel_imm <=  1'b0;
 
            // l.mtspr
            `OR1200_OR32_MTSPR:
              sel_imm <=  1'b0;
 
            // l.sys, l.brk and all three sync insns
            `OR1200_OR32_XSYNC:
              sel_imm <=  1'b0;
 
            // l.mac/l.msb
`ifdef OR1200_MAC_IMPLEMENTED
            `OR1200_OR32_MACMSB:
              sel_imm <=  1'b0;
`endif
 
            // l.sw
            `OR1200_OR32_SW:
              sel_imm <=  1'b0;
 
            // l.sb
            `OR1200_OR32_SB:
              sel_imm <=  1'b0;
 
            // l.sh
            `OR1200_OR32_SH:
              sel_imm <=  1'b0;
 
            // ALU instructions except the one with immediate
            `OR1200_OR32_ALU:
              sel_imm <=  1'b0;
 
            // SFXX instructions
            `OR1200_OR32_SFXX:
              sel_imm <=  1'b0;
 
`ifdef OR1200_OR32_CUST5
            // l.cust5 instructions
            `OR1200_OR32_CUST5:
              sel_imm <=  1'b0;
`endif
`ifdef OR1200_FPU_IMPLEMENTED
            // FPU instructions
            `OR1200_OR32_FLOAT:
              sel_imm <=  1'b0;
`endif
            // l.nop
            `OR1200_OR32_NOP:
              sel_imm <=  1'b0;
 
            // All instructions with immediates
            default: begin
              sel_imm <=  1'b1;
            end
 
          endcase
 
        end
end
 
//
// Decode of except_illegal
//
always @(posedge clk or posedge rst) begin
        if (rst)
                except_illegal <=  1'b0;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                except_illegal <=  1'b0;
        else if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys parallel_case
 
                `OR1200_OR32_J,
                `OR1200_OR32_JAL,
                `OR1200_OR32_JALR,
                `OR1200_OR32_JR,
                `OR1200_OR32_BNF,
                `OR1200_OR32_BF,
                `OR1200_OR32_RFE,
                `OR1200_OR32_MOVHI,
                `OR1200_OR32_MFSPR,
                `OR1200_OR32_XSYNC,
`ifdef OR1200_MAC_IMPLEMENTED
                `OR1200_OR32_MACI,
`endif
                `OR1200_OR32_LWZ,
                `OR1200_OR32_LBZ,
                `OR1200_OR32_LBS,
                `OR1200_OR32_LHZ,
                `OR1200_OR32_LHS,
                `OR1200_OR32_ADDI,
                `OR1200_OR32_ADDIC,
                `OR1200_OR32_ANDI,
                `OR1200_OR32_ORI,
                `OR1200_OR32_XORI,
`ifdef OR1200_MULT_IMPLEMENTED
                `OR1200_OR32_MULI,
`endif
                `OR1200_OR32_SH_ROTI,
                `OR1200_OR32_SFXXI,
                `OR1200_OR32_MTSPR,
`ifdef OR1200_MAC_IMPLEMENTED
                `OR1200_OR32_MACMSB,
`endif
                `OR1200_OR32_SW,
                `OR1200_OR32_SB,
                `OR1200_OR32_SH,
                `OR1200_OR32_SFXX,
`ifdef OR1200_OR32_CUST5
                `OR1200_OR32_CUST5,
`endif
        `OR1200_OR32_NOP:
                        except_illegal <=  1'b0;
`ifdef OR1200_FPU_IMPLEMENTED
            `OR1200_OR32_FLOAT:
                        // Check it's not a double precision instruction
                        except_illegal <=  id_insn[`OR1200_FPUOP_DOUBLE_BIT];
`endif
 
        `OR1200_OR32_ALU:
                        except_illegal <=  1'b0
 
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`else
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
`endif
`else
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
`endif
 
`ifdef OR1200_IMPL_ADDC
`else
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
`endif
 
`ifdef OR1200_IMPL_ALU_ROTATE
`else
                                | (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
`endif
 
`ifdef OR1200_IMPL_SUB
`else
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
`endif
                                ;
 
                // Illegal and OR1200 unsupported instructions
                default:
                        except_illegal <=  1'b1;
 
                endcase
 
        end
end
 
//
// Decode of alu_op
//
always @(posedge clk or posedge rst) begin
        if (rst)
                alu_op <=  `OR1200_ALUOP_NOP;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                alu_op <=  `OR1200_ALUOP_NOP;
        else if (!ex_freeze) begin
          case (id_insn[31:26])         // synopsys parallel_case
 
            // l.movhi
            `OR1200_OR32_MOVHI:
              alu_op <=  `OR1200_ALUOP_MOVHI;
 
            // l.addi
            `OR1200_OR32_ADDI:
              alu_op <=  `OR1200_ALUOP_ADD;
 
            // l.addic
            `OR1200_OR32_ADDIC:
              alu_op <=  `OR1200_ALUOP_ADDC;
 
            // l.andi
            `OR1200_OR32_ANDI:
              alu_op <=  `OR1200_ALUOP_AND;
 
            // l.ori
            `OR1200_OR32_ORI:
              alu_op <=  `OR1200_ALUOP_OR;
 
            // l.xori
            `OR1200_OR32_XORI:
              alu_op <=  `OR1200_ALUOP_XOR;
 
            // l.muli
`ifdef OR1200_MULT_IMPLEMENTED
            `OR1200_OR32_MULI:
              alu_op <=  `OR1200_ALUOP_MUL;
`endif
 
            // Shift and rotate insns with immediate
            `OR1200_OR32_SH_ROTI:
              alu_op <=  `OR1200_ALUOP_SHROT;
 
            // SFXX insns with immediate
            `OR1200_OR32_SFXXI:
              alu_op <=  `OR1200_ALUOP_COMP;
 
            // ALU instructions except the one with immediate
            `OR1200_OR32_ALU:
              alu_op <=  id_insn[3:0];
 
            // SFXX instructions
            `OR1200_OR32_SFXX:
              alu_op <=  `OR1200_ALUOP_COMP;
 
`ifdef OR1200_OR32_CUST5
            // l.cust5 instructions
            `OR1200_OR32_CUST5:
              alu_op <=  `OR1200_ALUOP_CUST5;
`endif
 
            // Default
            default: begin
              alu_op <=  `OR1200_ALUOP_NOP;
            end
 
          endcase
 
        end
end
 
//
// Decode of spr_read, spr_write
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                spr_read <=  1'b0;
                spr_write <=  1'b0;
        end
        else if (!ex_freeze & id_freeze | ex_flushpipe) begin
                spr_read <=  1'b0;
                spr_write <=  1'b0;
        end
        else if (!ex_freeze) begin
                case (id_insn[31:26])     // synopsys parallel_case
 
                // l.mfspr
                `OR1200_OR32_MFSPR: begin
                        spr_read <=  1'b1;
                        spr_write <=  1'b0;
                end
 
                // l.mtspr
                `OR1200_OR32_MTSPR: begin
                        spr_read <=  1'b0;
                        spr_write <=  1'b1;
                end
 
                // Default
                default: begin
                        spr_read <=  1'b0;
                        spr_write <=  1'b0;
                end
 
                endcase
        end
end
 
//
// Decode of mac_op
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(id_insn) begin
        case (id_insn[31:26])           // synopsys parallel_case
 
        // l.maci
        `OR1200_OR32_MACI:
                id_mac_op <=  `OR1200_MACOP_MAC;
 
        // l.mac, l.msb
        `OR1200_OR32_MACMSB:
                id_mac_op <=  id_insn[2:0];
 
        // Illegal and OR1200 unsupported instructions
        default:
                id_mac_op <=  `OR1200_MACOP_NOP;
 
        endcase
end
 
always @(posedge clk or posedge rst) begin
        if (rst)
                ex_mac_op <=  `OR1200_MACOP_NOP;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                ex_mac_op <=  `OR1200_MACOP_NOP;
        else if (!ex_freeze)
                ex_mac_op <=  id_mac_op;
end
 
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
`else
assign id_mac_op = `OR1200_MACOP_NOP;
assign mac_op = `OR1200_MACOP_NOP;
`endif
 
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst) begin
        if (rst)
                shrot_op <=  `OR1200_SHROTOP_NOP;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                shrot_op <=  `OR1200_SHROTOP_NOP;
        else if (!ex_freeze) begin
                shrot_op <=  id_insn[`OR1200_SHROTOP_POS];
        end
end
 
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst) begin
        if (rst)
                rfwb_op <=  `OR1200_RFWBOP_NOP;
        else  if (!ex_freeze & id_freeze | ex_flushpipe)
                rfwb_op <=  `OR1200_RFWBOP_NOP;
        else  if (!ex_freeze) begin
                case (id_insn[31:26])           // synopsys parallel_case
 
                // j.jal
                `OR1200_OR32_JAL:
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
 
                // j.jalr
                `OR1200_OR32_JALR:
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
 
                // l.movhi
                `OR1200_OR32_MOVHI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.mfspr
                `OR1200_OR32_MFSPR:
                        rfwb_op <=  {`OR1200_RFWBOP_SPRS, 1'b1};
 
                // l.lwz
                `OR1200_OR32_LWZ:
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
 
                // l.lbz
                `OR1200_OR32_LBZ:
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
 
                // l.lbs
                `OR1200_OR32_LBS:
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
 
                // l.lhz
                `OR1200_OR32_LHZ:
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
 
                // l.lhs
                `OR1200_OR32_LHS:
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
 
                // l.addi
                `OR1200_OR32_ADDI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.addic
                `OR1200_OR32_ADDIC:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.andi
                `OR1200_OR32_ANDI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.ori
                `OR1200_OR32_ORI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.xori
                `OR1200_OR32_XORI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // l.muli
`ifdef OR1200_MULT_IMPLEMENTED
                `OR1200_OR32_MULI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
`endif
 
                // Shift and rotate insns with immediate
                `OR1200_OR32_SH_ROTI:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
                // ALU instructions except the one with immediate
                `OR1200_OR32_ALU:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
 
`ifdef OR1200_OR32_CUST5
                // l.cust5 instructions
                `OR1200_OR32_CUST5:
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
`endif
`ifdef OR1200_FPU_IMPLEMENTED
                  // FPU instructions, lf.XXX.s, except sfxx
                  `OR1200_OR32_FLOAT:
                    rfwb_op <=  {`OR1200_RFWBOP_FPU,!id_insn[3]};
`endif
                // Instructions w/o register-file write-back
                default:
                        rfwb_op <=  `OR1200_RFWBOP_NOP;
 
 
                endcase
        end
end
 
//
// Decode of id_branch_op
//
always @(posedge clk or posedge rst) begin
        if (rst)
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
        else if (id_flushpipe)
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
        else if (!id_freeze) begin
                case (if_insn[31:26])           // synopsys parallel_case
 
                // l.j
                `OR1200_OR32_J:
                        id_branch_op <=  `OR1200_BRANCHOP_J;
 
                // j.jal
                `OR1200_OR32_JAL:
                        id_branch_op <=  `OR1200_BRANCHOP_J;
 
                // j.jalr
                `OR1200_OR32_JALR:
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
 
                // l.jr
                `OR1200_OR32_JR:
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
 
                // l.bnf
                `OR1200_OR32_BNF:
                        id_branch_op <=  `OR1200_BRANCHOP_BNF;
 
                // l.bf
                `OR1200_OR32_BF:
                        id_branch_op <=  `OR1200_BRANCHOP_BF;
 
                // l.rfe
                `OR1200_OR32_RFE:
                        id_branch_op <=  `OR1200_BRANCHOP_RFE;
 
                // Non branch instructions
                default:
                        id_branch_op <=  `OR1200_BRANCHOP_NOP;
 
                endcase
        end
end
 
//
// Generation of ex_branch_op
//
always @(posedge clk or posedge rst)
        if (rst)
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
        else if (!ex_freeze)
                ex_branch_op <=  id_branch_op;
 
//
// Decode of id_lsu_op
//
always @(id_insn) begin
        case (id_insn[31:26])           // synopsys parallel_case
 
        // l.lwz
        `OR1200_OR32_LWZ:
                id_lsu_op <=  `OR1200_LSUOP_LWZ;
 
        // l.lbz
        `OR1200_OR32_LBZ:
                id_lsu_op <=  `OR1200_LSUOP_LBZ;
 
        // l.lbs
        `OR1200_OR32_LBS:
                id_lsu_op <=  `OR1200_LSUOP_LBS;
 
        // l.lhz
        `OR1200_OR32_LHZ:
                id_lsu_op <=  `OR1200_LSUOP_LHZ;
 
        // l.lhs
        `OR1200_OR32_LHS:
                id_lsu_op <=  `OR1200_LSUOP_LHS;
 
        // l.sw
        `OR1200_OR32_SW:
                id_lsu_op <=  `OR1200_LSUOP_SW;
 
        // l.sb
        `OR1200_OR32_SB:
                id_lsu_op <=  `OR1200_LSUOP_SB;
 
        // l.sh
        `OR1200_OR32_SH:
                id_lsu_op <=  `OR1200_LSUOP_SH;
 
        // Non load/store instructions
        default:
                id_lsu_op <=  `OR1200_LSUOP_NOP;
 
        endcase
end
 
//
// Decode of comp_op
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                comp_op <=  4'd0;
        end else if (!ex_freeze & id_freeze | ex_flushpipe)
                comp_op <=  4'd0;
        else if (!ex_freeze)
                comp_op <=  id_insn[24:21];
end
 
`ifdef OR1200_FPU_IMPLEMENTED
//
// Decode of FPU ops
//
   assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
                    id_insn[`OR1200_FPUOP_WIDTH-2:0]};
`else
   assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
`endif
 
 
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_syscall <=  1'b0;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                sig_syscall <=  1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
                        $display("Generating sig_syscall");
// synopsys translate_on
`endif
                sig_syscall <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
        end
end
 
//
// Decode of l.trap
//
always @(posedge clk or posedge rst) begin
        if (rst)
                sig_trap <=  1'b0;
        else if (!ex_freeze & id_freeze | ex_flushpipe)
                sig_trap <=  1'b0;
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
                        $display("Generating sig_trap");
// synopsys translate_on
`endif
                sig_trap <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
                        | du_hwbkpt;
        end
end
 
// Decode destination register address for data cache to check if store ops
// are being done from the stack register (r1) or frame pointer register (r2)
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
always @(posedge clk or posedge rst) begin
   if (rst)
     dc_no_writethrough <= 0;
   else if (!ex_freeze)
     dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
end
`else
 
   assign dc_no_writethrough = 0;
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction decode ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// Majority of instruction decoding is performed here. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`//`
45	141	marcus.erl	`// $Log: or1200_ctrl.v,v $`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Major update:`
48			`// Structure reordered and bugs fixed.`
49	10	unneback
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "or1200_defines.v"
54
55	185	julius	`module or1200_ctrl`
56			`(`
57			`// Clock and reset`
58			`clk, rst,`
59
60			`// Internal i/f`
61			`except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,`
62			`wb_flushpipe,`
63			`id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,`
64			`id_branch_op, ex_branch_op, ex_branch_taken, pc_we,`
65			`rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,`
66			`rf_addrw, rfwb_op, fpu_op,`
67			`wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,`
68			`sel_b, id_lsu_op,`
69			`cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,`
70	258	julius	`multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,`
71	185	julius	`force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,`
72			`ex_spr_write,`
73	258	julius	`id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough`
74	185	julius	`);`
75	10	unneback
76			`//`
77			`// I/O`
78			`//`
79			`input clk;`
80			`input rst;`
81			`input id_freeze;`
82			`input ex_freeze;`
83			`input wb_freeze;`
84	141	marcus.erl	`output if_flushpipe;`
85			`output id_flushpipe;`
86			`output ex_flushpipe;`
87			`output wb_flushpipe;`
88			`input extend_flush;`
89			`input except_flushpipe;`
90			`input abort_mvspr ;`
91			`input [31:0] if_insn;`
92			`output [31:0] id_insn;`
93			`output [31:0] ex_insn;`
94			output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
95			output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
96			`input ex_branch_taken;`
97	10	unneback	output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
98			output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
99			output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
100			`output rf_rda;`
101			`output rf_rdb;`
102			output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
103			output [`OR1200_MACOP_WIDTH-1:0] mac_op;
104			output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
105			output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
106	258	julius	output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
107	141	marcus.erl	`input pc_we;`
108	10	unneback	`output [31:0] wb_insn;`
109	141	marcus.erl	`output [31:2] id_branch_addrtarget;`
110			`output [31:2] ex_branch_addrtarget;`
111	10	unneback	output [`OR1200_SEL_WIDTH-1:0] sel_a;
112			output [`OR1200_SEL_WIDTH-1:0] sel_b;
113	141	marcus.erl	output [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
114	10	unneback	output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
115			output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
116	258	julius	output [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
117	10	unneback	`output [4:0] cust5_op;`
118			`output [5:0] cust5_limm;`
119	141	marcus.erl	`input [31:0] id_pc;`
120			`input [31:0] ex_pc;`
121			`output [31:0] id_simm;`
122			`output [31:0] ex_simm;`
123	10	unneback	`input wbforw_valid;`
124			`input du_hwbkpt;`
125			`output sig_syscall;`
126			`output sig_trap;`
127			`output force_dslot_fetch;`
128			`output no_more_dslot;`
129	141	marcus.erl	`output id_void;`
130	10	unneback	`output ex_void;`
131	141	marcus.erl	`output ex_spr_read;`
132			`output ex_spr_write;`
133			output [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
134	10	unneback	`output id_macrc_op;`
135			`output ex_macrc_op;`
136			`output rfe;`
137			`output except_illegal;`
138	258	julius	`output dc_no_writethrough;`
139
140
141	10	unneback	`//`
142			`// Internal wires and regs`
143			`//`
144	141	marcus.erl	reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
145			reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
146	10	unneback	reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
147	141	marcus.erl	`wire if_maci_op;`
148	10	unneback	`ifdef OR1200_MAC_IMPLEMENTED
149	141	marcus.erl	reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op;
150			reg [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
151			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
152	10	unneback	`reg ex_macrc_op;`
153			`else
154			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
155			`wire ex_macrc_op;`
156			`endif
157			reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
158			`reg [31:0] id_insn;`
159			`reg [31:0] ex_insn;`
160			`reg [31:0] wb_insn;`
161			reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
162			reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
163			reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
164			reg [`OR1200_SEL_WIDTH-1:0] sel_a;
165			reg [`OR1200_SEL_WIDTH-1:0] sel_b;
166			`reg sel_imm;`
167	141	marcus.erl	reg [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
168	10	unneback	reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
169			reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
170	258	julius	reg [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
171	141	marcus.erl	`reg [31:0] id_simm;`
172			`reg [31:0] ex_simm;`
173	10	unneback	`reg sig_syscall;`
174			`reg sig_trap;`
175			`reg except_illegal;`
176			`wire id_void;`
177	141	marcus.erl	`wire ex_void;`
178			`wire wb_void;`
179			`reg ex_delayslot_dsi;`
180			`reg ex_delayslot_nop;`
181			`reg spr_read;`
182			`reg spr_write;`
183			`reg [31:2] ex_branch_addrtarget;`
184	258	julius	`ifdef OR1200_DC_NOSTACKWRITETHROUGH
185			`reg dc_no_writethrough;`
186			`endif
187
188	10	unneback	`//`
189			`// Register file read addresses`
190			`//`
191			`assign rf_addra = if_insn[20:16];`
192			`assign rf_addrb = if_insn[15:11];`
193	141	marcus.erl	`assign rf_rda = if_insn[31] \|\| if_maci_op;`
194	10	unneback	`assign rf_rdb = if_insn[30];`
195
196			`//`
197			`// Force fetch of delay slot instruction when jump/branch is preceeded by load/store`
198			`// instructions`
199			`//`
200			`assign force_dslot_fetch = 1'b0;`
201	141	marcus.erl	assign no_more_dslot = (\|ex_branch_op & !id_void & ex_branch_taken) \| (ex_branch_op == `OR1200_BRANCHOP_RFE);
202
203	10	unneback	assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
204			assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
205	141	marcus.erl	assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
206	10	unneback
207	141	marcus.erl	`assign ex_spr_write = spr_write && !abort_mvspr;`
208			`assign ex_spr_read = spr_read && !abort_mvspr;`
209
210	10	unneback	`//`
211	141	marcus.erl	`// ex_delayslot_dsi: delay slot insn is in EX stage`
212			`// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)`
213	10	unneback	`//`
214	141	marcus.erl	`// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage`
215			`// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,`
216			`// next different is DS insn, previous different was Jump/Branch`
217			`// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage`
218			`//`
219			`always @(posedge clk or posedge rst) begin`
220			`if (rst) begin`
221	258	julius	`ex_delayslot_nop <= 1'b0;`
222			`ex_delayslot_dsi <= 1'b0;`
223	141	marcus.erl	`end`
224			`else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin`
225	258	julius	`ex_delayslot_nop <= id_void;`
226			`ex_delayslot_dsi <= !id_void;`
227	141	marcus.erl	`end`
228			`else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin`
229	258	julius	`ex_delayslot_nop <= 1'b0;`
230			`ex_delayslot_dsi <= 1'b0;`
231	141	marcus.erl	`end`
232			`else if (!ex_freeze) begin`
233	258	julius	ex_delayslot_nop <= id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
234	141	marcus.erl	(ex_branch_op != `OR1200_BRANCHOP_RFE);
235	258	julius	ex_delayslot_dsi <= !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
236	141	marcus.erl	(ex_branch_op != `OR1200_BRANCHOP_RFE);
237			`end`
238			`end`
239	10	unneback
240			`//`
241	141	marcus.erl	`// Flush pipeline`
242	10	unneback	`//`
243	141	marcus.erl	`assign if_flushpipe = except_flushpipe \| pc_we \| extend_flush;`
244			`assign id_flushpipe = except_flushpipe \| pc_we \| extend_flush;`
245			`assign ex_flushpipe = except_flushpipe \| pc_we \| extend_flush;`
246			`assign wb_flushpipe = except_flushpipe \| pc_we \| extend_flush;`
247	10	unneback
248			`//`
249	141	marcus.erl	`// EX Sign/Zero extension of immediates`
250			`//`
251			`always @(posedge clk or posedge rst) begin`
252			`if (rst)`
253	258	julius	`ex_simm <= 32'h0000_0000;`
254	141	marcus.erl	`else if (!ex_freeze) begin`
255	258	julius	`ex_simm <= id_simm;`
256	141	marcus.erl	`end`
257			`end`
258
259			`//`
260			`// ID Sign/Zero extension of immediate`
261			`//`
262			`always @(id_insn) begin`
263			`case (id_insn[31:26]) // synopsys parallel_case`
264
265			`// l.addi`
266			`OR1200_OR32_ADDI:
267			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
268
269			`// l.addic`
270			`OR1200_OR32_ADDIC:
271			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
272
273			`// l.lxx (load instructions)`
274			`OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
275			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
276
277			`// l.muli`
278			`ifdef OR1200_MULT_IMPLEMENTED
279			`OR1200_OR32_MULI:
280			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
281			`endif
282
283			`// l.maci`
284			`ifdef OR1200_MAC_IMPLEMENTED
285			`OR1200_OR32_MACI:
286			`id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};`
287			`endif
288
289			`// l.mtspr`
290			`OR1200_OR32_MTSPR:
291			`id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};`
292
293			`// l.sxx (store instructions)`
294			`OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
295			`id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};`
296
297			`// l.xori`
298			`OR1200_OR32_XORI:
299			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
300
301			`// l.sfxxi (SFXX with immediate)`
302			`OR1200_OR32_SFXXI:
303			`id_simm = {{16{id_insn[15]}}, id_insn[15:0]};`
304
305			`// Instructions with no or zero extended immediate`
306			`default:`
307			`id_simm = {{16'b0}, id_insn[15:0]};`
308
309			`endcase`
310			`end`
311
312			`//`
313			`// ID Sign extension of branch offset`
314			`//`
315			`assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];`
316
317			`//`
318			`// EX Sign extension of branch offset`
319			`//`
320
321			`// pipeline ID and EX branch target address`
322			`always @(posedge clk or posedge rst) begin`
323			`if (rst)`
324	258	julius	`ex_branch_addrtarget <= 32'h00000000;`
325	141	marcus.erl	`else if (!ex_freeze)`
326	258	julius	`ex_branch_addrtarget <= id_branch_addrtarget;`
327	141	marcus.erl	`end`
328			`// not pipelined`
329			`//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];`
330
331			`//`
332			`// l.maci in IF stage`
333			`//`
334			`ifdef OR1200_MAC_IMPLEMENTED
335			assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
336			`else
337			`assign if_maci_op = 1'b0;`
338			`endif
339
340			`//`
341	10	unneback	`// l.macrc in ID stage`
342			`//`
343			`ifdef OR1200_MAC_IMPLEMENTED
344			assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
345			`else
346			`assign id_macrc_op = 1'b0;`
347			`endif
348
349			`//`
350	141	marcus.erl	`// l.macrc in EX stage`
351			`//`
352			`ifdef OR1200_MAC_IMPLEMENTED
353			`always @(posedge clk or posedge rst) begin`
354			`if (rst)`
355	258	julius	`ex_macrc_op <= 1'b0;`
356	141	marcus.erl	`else if (!ex_freeze & id_freeze \| ex_flushpipe)`
357	258	julius	`ex_macrc_op <= 1'b0;`
358	141	marcus.erl	`else if (!ex_freeze)`
359	258	julius	`ex_macrc_op <= id_macrc_op;`
360	141	marcus.erl	`end`
361			`else
362			`assign ex_macrc_op = 1'b0;`
363			`endif
364
365			`//`
366	10	unneback	`// cust5_op, cust5_limm (L immediate)`
367			`//`
368			`assign cust5_op = ex_insn[4:0];`
369			`assign cust5_limm = ex_insn[10:5];`
370
371			`//`
372			`//`
373			`//`
374	141	marcus.erl	assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) \| (ex_branch_op == `OR1200_BRANCHOP_RFE);
375	10	unneback
376			`//`
377			`// Generation of sel_a`
378			`//`
379			`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
380			`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`
381			sel_a = `OR1200_SEL_EX_FORW;
382			`else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)`
383			sel_a = `OR1200_SEL_WB_FORW;
384			`else`
385			sel_a = `OR1200_SEL_RF;
386
387			`//`
388			`// Generation of sel_b`
389			`//`
390			`always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
391			`if (sel_imm)`
392			sel_b = `OR1200_SEL_IMM;
393			`else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])`
394			sel_b = `OR1200_SEL_EX_FORW;
395			`else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)`
396			sel_b = `OR1200_SEL_WB_FORW;
397			`else`
398			sel_b = `OR1200_SEL_RF;
399
400			`//`
401			`// Decode of multicycle`
402			`//`
403			`always @(id_insn) begin`
404			`case (id_insn[31:26]) // synopsys parallel_case`
405			`ifdef UNUSED
406			`// l.lwz`
407			`OR1200_OR32_LWZ:
408			multicycle = `OR1200_TWO_CYCLES;
409
410			`// l.lbz`
411			`OR1200_OR32_LBZ:
412			multicycle = `OR1200_TWO_CYCLES;
413
414			`// l.lbs`
415			`OR1200_OR32_LBS:
416			multicycle = `OR1200_TWO_CYCLES;
417
418			`// l.lhz`
419			`OR1200_OR32_LHZ:
420			multicycle = `OR1200_TWO_CYCLES;
421
422			`// l.lhs`
423			`OR1200_OR32_LHS:
424			multicycle = `OR1200_TWO_CYCLES;
425
426			`// l.sw`
427			`OR1200_OR32_SW:
428			multicycle = `OR1200_TWO_CYCLES;
429
430			`// l.sb`
431			`OR1200_OR32_SB:
432			multicycle = `OR1200_TWO_CYCLES;
433
434			`// l.sh`
435			`OR1200_OR32_SH:
436			multicycle = `OR1200_TWO_CYCLES;
437			`endif
438	141	marcus.erl	`// l.mfspr`
439			`OR1200_OR32_MFSPR:
440			multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
441
442	10	unneback	`// ALU instructions except the one with immediate`
443			`OR1200_OR32_ALU:
444	141	marcus.erl	`case (id_insn[3:0]) // synopsys parallel_case`
445			`4'h6: multicycle = 2'b11; // l.mul`
446			`4'h9: multicycle = 2'b10; // l.div`
447			`4'hA: multicycle = 2'b10; // l.divu`
448			`4'hB: multicycle = 2'b11; // l.mulu`
449			`default: multicycle = 2'b00;`
450			`endcase`
451	10	unneback
452	141	marcus.erl	`OR1200_OR32_MULI:
453			`multicycle = 2'h3;`
454
455	10	unneback	`// Single cycle instructions`
456			`default: begin`
457			multicycle = `OR1200_ONE_CYCLE;
458	258	julius	`end`
459	10	unneback	`endcase`
460	258	julius	`end // always @ (id_insn)`
461	10	unneback
462			`//`
463	258	julius	`// Encode wait_on signal`
464			`//`
465			`always @(id_insn) begin`
466			`case (id_insn[31:26]) // synopsys parallel_case`
467			`ifdef OR1200_FPU_IMPLEMENTED
468			`OR1200_OR32_FLOAT: begin
469			wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
470			`end`
471			`endif
472			`ifndef OR1200_DC_WRITHROUGH
473			`// l.mtspr`
474			`OR1200_OR32_MTSPR: begin
475			wait_on = `OR1200_WAIT_ON_MTSPR;
476			`end`
477			`endif
478			`default: begin`
479			`wait_on = 0;`
480			`end`
481			`endcase // case (id_insn[31:26])`
482			`end // always @ (id_insn)`
483
484
485
486
487			`//`
488	10	unneback	`// Register file write address`
489			`//`
490			`always @(posedge clk or posedge rst) begin`
491			`if (rst)`
492	258	julius	`rf_addrw <= 5'd0;`
493	10	unneback	`else if (!ex_freeze & id_freeze)`
494	258	julius	`rf_addrw <= 5'd00;`
495	10	unneback	`else if (!ex_freeze)`
496	141	marcus.erl	`case (id_insn[31:26]) // synopsys parallel_case`
497			`OR1200_OR32_JAL, `OR1200_OR32_JALR:
498	258	julius	`rf_addrw <= 5'd09; // link register r9`
499	10	unneback	`default:`
500	258	julius	`rf_addrw <= id_insn[25:21];`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Blame information for rev 294