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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_fsm.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed. 
//
// Revision 1.9  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.6  2002/03/28 19:10:40  lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, biu_sel, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we, tag_valid, dc_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcqmem_cycstb_i;
input                           dcqmem_ci_i;
input                           dcqmem_we_i;
input   [3:0]                    dcqmem_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output              biu_sel;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
output              tag_valid;
output  [31:0]                   dc_addr;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
reg                             cache_inhibit;
reg             cache_miss;
//wire                          tagcomp_miss_wide;
wire                            first_store_hit_ack;
 
//
// Generate of DCRAM write enables
//
//assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
assign dcram_we = {4{load & biudata_valid & !cache_inhibit & !hitmiss_eval}} |
                  {4{first_store_hit_ack}} & dcqmem_sel_i;
//assign tag_we = biu_read & biudata_valid & !cache_inhibit;
assign tag_we = load & (biudata_valid & (!cache_inhibit | !cache_miss) | biudata_error) & !hitmiss_eval |
                store & (biudata_valid & cache_inhibit & !cache_miss | biudata_error) & !hitmiss_eval;
assign tag_valid = biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
//assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign biu_read = ((hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load)) & (dcqmem_cycstb_i | biudata_valid);
assign biu_read = (state == `OR1200_DCFSM_CLOAD) & (hitmiss_eval ? ((tagcomp_miss | dcqmem_ci_i) & dcqmem_cycstb_i) : (cache_miss & !cache_inhibit & biudata_valid | dcqmem_cycstb_i & !biudata_error)) |
                  (state == `OR1200_DCFSM_LREFILL3) & !(biudata_valid & !cnt) & !biudata_error;
//assign biu_write = store;
//assign biu_write = store & dcqmem_cycstb_i;
assign biu_write = store & dcqmem_cycstb_i;
assign biu_sel = load;
 
//assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
assign dc_addr = (!(load | store) | hitmiss_eval) ? start_addr : saved_addr;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
//assign tagcomp_miss_wide = tagcomp_miss | (saved_addr != start_addr);
//assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss_wide & !cache_inhibit | first_store_hit_ack;
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i | first_store_hit_ack;
//assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss_wide & biudata_valid & !cache_inhibit;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !hitmiss_eval & !cache_miss & biudata_valid & !cache_inhibit;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
//assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
//              | (state == `OR1200_DCFSM_LREFILL3)
//`ifdef OR1200_DC_STORE_REFILL
//              | (state == `OR1200_DCFSM_SREFILL4)
//`endif
//              ;
assign burst = load & (hitmiss_eval ? !dcqmem_ci_i : !cache_inhibit);
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
        cache_miss <= #1 1'b0;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
        `OR1200_DCFSM_IDLE : begin
            if (dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
                state <= #1 `OR1200_DCFSM_CSTORE;
            else if (!dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store
                state <= #1 `OR1200_DCFSM_CLOAD;
            cache_inhibit <= #1 1'b0;         // not dcqmem_ci_i because it is delayed (due to DTLB)
            hitmiss_eval <= #1 dc_en & dcqmem_cycstb_i  ;
            store <= #1 dc_en & dcqmem_cycstb_i & dcqmem_we_i;
            load <= #1 dc_en & dcqmem_cycstb_i & !dcqmem_we_i;
        end
        `OR1200_DCFSM_CLOAD: begin      // load
            if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
                state <= #1 `OR1200_DCFSM_LREFILL3;
            end
            else if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_valid || biudata_error) || hitmiss_eval && !tagcomp_miss && !dcqmem_ci_i) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                load <= #1 1'b0;
            end
            hitmiss_eval <= #1 1'b0;
            cnt <= #1 `OR1200_DCLS-2;
            if (hitmiss_eval) begin
                cache_inhibit <= #1 dcqmem_ci_i;
                cache_miss <= #1 tagcomp_miss;
            end
            if (hitmiss_eval)
                saved_addr_r <= #1 start_addr;
            else if (biudata_valid)
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
        end
        `OR1200_DCFSM_LREFILL3 : begin
            if (!dc_en || biudata_valid && !cnt || biudata_error) begin                     // finish/abort
                state <= #1 `OR1200_DCFSM_IDLE;
                load <= #1 1'b0;
            end
            if (biudata_valid) begin
                cnt <= #1 cnt - 1'b1;
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
            end
        end
        `OR1200_DCFSM_CSTORE: begin     // store
            hitmiss_eval <= 1'b0;
            if (hitmiss_eval) begin
                cache_inhibit <= #1 dcqmem_ci_i;
                cache_miss <= #1 tagcomp_miss;
            end
            if (hitmiss_eval)
                saved_addr_r <= #1 start_addr;
`ifdef OR1200_DC_STORE_REFILL
            else if (biudata_valid)
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;
            cnt <= #1 `OR1200_DCLS-1;
            if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin
                state <= #1 `OR1200_DCFSM_SREFILL4;
                store <= #1 1'b0;
                load <= #1 1'b1;
            end
            else
`endif
            if (!dcqmem_cycstb_i || !hitmiss_eval && (biudata_error || biudata_valid)) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                store <= #1 1'b0;
            end
`ifdef OR1200_DC_STORE_REFILL
        `OR1200_DCFSM_SREFILL4 : begin
            if (!dc_en) begin                       // somebody just turned off DC therefore we abort
                cnt <= #1 3'd0;                     // DC will have to be invalidated before
                state <= #1 `OR1200_DCFSM_IDLE;     // it can be turned on again
                load <= #1 1'b0;
            end
            else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
                cnt <= #1 cnt - 1'd1;
                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
            end
            else if (biudata_valid) begin           // last load of line refill
                state <= #1 `OR1200_DCFSM_IDLE;
                load <= #1 1'b0;
            end
`endif
        end
 
        default:
            state <= #1 `OR1200_DCFSM_IDLE;
    endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_dc_fsm.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Minor update:`
49			`// Bugs fixed.`
50			`//`
51			`// Revision 1.9 2004/06/08 18:17:36 lampret`
52			`// Non-functional changes. Coding style fixes.`
53			`//`
54	10	unneback	`// Revision 1.8 2004/04/05 08:29:57 lampret`
55			`// Merged branch_qmem into main tree.`
56			`//`
57			`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
58			`// Added embedded memory QMEM.`
59			`//`
60			`// Revision 1.7 2002/03/29 15:16:55 lampret`
61			`// Some of the warnings fixed.`
62			`//`
63			`// Revision 1.6 2002/03/28 19:10:40 lampret`
64			`// Optimized cache controller FSM.`
65			`//`
66			`// Revision 1.1.1.1 2002/03/21 16:55:45 lampret`
67			`// First import of the "new" XESS XSV environment.`
68			`//`
69			`//`
70			`// Revision 1.5 2002/02/11 04:33:17 lampret`
71			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
72			`//`
73			`// Revision 1.4 2002/02/01 19:56:54 lampret`
74			`// Fixed combinational loops.`
75			`//`
76			`// Revision 1.3 2002/01/28 01:15:59 lampret`
77			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
78			`//`
79			`// Revision 1.2 2002/01/14 06:18:22 lampret`
80			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
81			`//`
82			`// Revision 1.1 2002/01/03 08:16:15 lampret`
83			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
84			`//`
85			`// Revision 1.9 2001/10/21 17:57:16 lampret`
86			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
87			`//`
88			`// Revision 1.8 2001/10/19 23:28:46 lampret`
89			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
90			`//`
91			`// Revision 1.7 2001/10/14 13:12:09 lampret`
92			`// MP3 version.`
93			`//`
94			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
95			`// no message`
96			`//`
97			`// Revision 1.2 2001/08/09 13:39:33 lampret`
98			`// Major clean-up.`
99			`//`
100			`// Revision 1.1 2001/07/20 00:46:03 lampret`
101			`// Development version of RTL. Libraries are missing.`
102			`//`
103			`//`
104
105			`// synopsys translate_off`
106			`include "timescale.v"
107			`// synopsys translate_on`
108			`include "or1200_defines.v"
109
110			`define OR1200_DCFSM_IDLE 3'd0
111			`define OR1200_DCFSM_CLOAD 3'd1
112			`define OR1200_DCFSM_LREFILL3 3'd2
113			`define OR1200_DCFSM_CSTORE 3'd3
114			`define OR1200_DCFSM_SREFILL4 3'd4
115
116			`//`
117			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
118			`//`
119
120			`module or1200_dc_fsm(`
121			`// Clock and reset`
122			`clk, rst,`
123
124			`// Internal i/f to top level DC`
125			`dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,`
126			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
127	141	marcus.erl	`dcram_we, biu_read, biu_write, biu_sel, first_hit_ack, first_miss_ack, first_miss_err,`
128			`burst, tag_we, tag_valid, dc_addr`
129	10	unneback	`);`
130
131			`//`
132			`// I/O`
133			`//`
134			`input clk;`
135			`input rst;`
136			`input dc_en;`
137			`input dcqmem_cycstb_i;`
138			`input dcqmem_ci_i;`
139			`input dcqmem_we_i;`
140			`input [3:0] dcqmem_sel_i;`
141			`input tagcomp_miss;`
142			`input biudata_valid;`
143			`input biudata_error;`
144			`input [31:0] start_addr;`
145			`output [31:0] saved_addr;`
146			`output [3:0] dcram_we;`
147			`output biu_read;`
148			`output biu_write;`
149	141	marcus.erl	`output biu_sel;`
150	10	unneback	`output first_hit_ack;`
151			`output first_miss_ack;`
152			`output first_miss_err;`
153			`output burst;`
154			`output tag_we;`
155	141	marcus.erl	`output tag_valid;`
156	10	unneback	`output [31:0] dc_addr;`
157
158			`//`
159			`// Internal wires and regs`
160			`//`
161			`reg [31:0] saved_addr_r;`
162			`reg [2:0] state;`
163			`reg [2:0] cnt;`
164			`reg hitmiss_eval;`
165			`reg store;`
166			`reg load;`
167			`reg cache_inhibit;`
168	141	marcus.erl	`reg cache_miss;`
169			`//wire tagcomp_miss_wide;`
170	10	unneback	`wire first_store_hit_ack;`
171
172			`//`
173			`// Generate of DCRAM write enables`
174			`//`
175	141	marcus.erl	`//assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} \| {4{first_store_hit_ack}} & dcqmem_sel_i;`
176			`assign dcram_we = {4{load & biudata_valid & !cache_inhibit & !hitmiss_eval}} \|`
177			`{4{first_store_hit_ack}} & dcqmem_sel_i;`
178			`//assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
179			`assign tag_we = load & (biudata_valid & (!cache_inhibit \| !cache_miss) \| biudata_error) & !hitmiss_eval \|`
180			`store & (biudata_valid & cache_inhibit & !cache_miss \| biudata_error) & !hitmiss_eval;`
181			`assign tag_valid = biudata_valid & !cache_inhibit;`
182	10	unneback
183			`//`
184			`// BIU read and write`
185			`//`
186	141	marcus.erl	`//assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
187			`//assign biu_read = ((hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load)) & (dcqmem_cycstb_i \| biudata_valid);`
188			assign biu_read = (state == `OR1200_DCFSM_CLOAD) & (hitmiss_eval ? ((tagcomp_miss \| dcqmem_ci_i) & dcqmem_cycstb_i) : (cache_miss & !cache_inhibit & biudata_valid \| dcqmem_cycstb_i & !biudata_error)) \|
189			(state == `OR1200_DCFSM_LREFILL3) & !(biudata_valid & !cnt) & !biudata_error;
190			`//assign biu_write = store;`
191			`//assign biu_write = store & dcqmem_cycstb_i;`
192			`assign biu_write = store & dcqmem_cycstb_i;`
193			`assign biu_sel = load;`
194	10	unneback
195	141	marcus.erl	`//assign dc_addr = (biu_read \| biu_write) & !hitmiss_eval ? saved_addr : start_addr;`
196			`assign dc_addr = (!(load \| store) \| hitmiss_eval) ? start_addr : saved_addr;`
197	10	unneback	`assign saved_addr = saved_addr_r;`
198
199			`//`
200			`// Assert for cache hit first word ready`
201			`// Assert for store cache hit first word ready`
202			`// Assert for cache miss first word stored/loaded OK`
203			`// Assert for cache miss first word stored/loaded with an error`
204			`//`
205	141	marcus.erl	`//assign tagcomp_miss_wide = tagcomp_miss \| (saved_addr != start_addr);`
206			//assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss_wide & !cache_inhibit \| first_store_hit_ack;
207			assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i \| first_store_hit_ack;
208			//assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss_wide & biudata_valid & !cache_inhibit;
209			assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !hitmiss_eval & !cache_miss & biudata_valid & !cache_inhibit;
210	10	unneback	assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
211			assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
212
213			`//`
214			`// Assert burst when doing reload of complete cache line`
215			`//`
216	141	marcus.erl	//assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
217			// \| (state == `OR1200_DCFSM_LREFILL3)
218			//`ifdef OR1200_DC_STORE_REFILL
219			// \| (state == `OR1200_DCFSM_SREFILL4)
220			//`endif
221			`// ;`
222			`assign burst = load & (hitmiss_eval ? !dcqmem_ci_i : !cache_inhibit);`
223	10	unneback
224			`//`
225			`// Main DC FSM`
226			`//`
227			`always @(posedge clk or posedge rst) begin`
228			`if (rst) begin`
229			state <= #1 `OR1200_DCFSM_IDLE;
230			`saved_addr_r <= #1 32'b0;`
231			`hitmiss_eval <= #1 1'b0;`
232			`store <= #1 1'b0;`
233			`load <= #1 1'b0;`
234			`cnt <= #1 3'b000;`
235	141	marcus.erl	`cache_miss <= #1 1'b0;`
236	10	unneback	`cache_inhibit <= #1 1'b0;`
237			`end`
238			`else`
239			`case (state) // synopsys parallel_case`
240	141	marcus.erl	`OR1200_DCFSM_IDLE : begin
241			`if (dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store`
242			state <= #1 `OR1200_DCFSM_CSTORE;
243			`else if (!dcqmem_we_i & dc_en & dcqmem_cycstb_i) // store`
244			state <= #1 `OR1200_DCFSM_CLOAD;
245			`cache_inhibit <= #1 1'b0; // not dcqmem_ci_i because it is delayed (due to DTLB)`
246			`hitmiss_eval <= #1 dc_en & dcqmem_cycstb_i ;`
247			`store <= #1 dc_en & dcqmem_cycstb_i & dcqmem_we_i;`
248			`load <= #1 dc_en & dcqmem_cycstb_i & !dcqmem_we_i;`
249			`end`
250			`OR1200_DCFSM_CLOAD: begin // load
251			`if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin`
252			state <= #1 `OR1200_DCFSM_LREFILL3;
253			`end`
254			`else if (!dcqmem_cycstb_i \|\| !hitmiss_eval && (biudata_valid \|\| biudata_error) \|\| hitmiss_eval && !tagcomp_miss && !dcqmem_ci_i) begin`
255			state <= #1 `OR1200_DCFSM_IDLE;
256			`load <= #1 1'b0;`
257			`end`
258			`hitmiss_eval <= #1 1'b0;`
259			cnt <= #1 `OR1200_DCLS-2;
260			`if (hitmiss_eval) begin`
261			`cache_inhibit <= #1 dcqmem_ci_i;`
262			`cache_miss <= #1 tagcomp_miss;`
263			`end`
264			`if (hitmiss_eval)`
265			`saved_addr_r <= #1 start_addr;`
266			`else if (biudata_valid)`
267			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;`
268			`end`
269			`OR1200_DCFSM_LREFILL3 : begin
270			`if (!dc_en \|\| biudata_valid && !cnt \|\| biudata_error) begin // finish/abort`
271			state <= #1 `OR1200_DCFSM_IDLE;
272			`load <= #1 1'b0;`
273			`end`
274			`if (biudata_valid) begin`
275			`cnt <= #1 cnt - 1'b1;`
276			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;`
277			`end`
278			`end`
279			`OR1200_DCFSM_CSTORE: begin // store
280			`hitmiss_eval <= 1'b0;`
281			`if (hitmiss_eval) begin`
282			`cache_inhibit <= #1 dcqmem_ci_i;`
283			`cache_miss <= #1 tagcomp_miss;`
284			`end`
285			`if (hitmiss_eval)`
286			`saved_addr_r <= #1 start_addr;`
287	10	unneback	`ifdef OR1200_DC_STORE_REFILL
288	141	marcus.erl	`else if (biudata_valid)`
289			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'b1;`
290			cnt <= #1 `OR1200_DCLS-1;
291			`if (!hitmiss_eval && cache_miss && !cache_inhibit && biudata_valid) begin`
292			state <= #1 `OR1200_DCFSM_SREFILL4;
293			`store <= #1 1'b0;`
294			`load <= #1 1'b1;`
295			`end`
296			`else`
297	10	unneback	`endif
298	141	marcus.erl	`if (!dcqmem_cycstb_i \|\| !hitmiss_eval && (biudata_error \|\| biudata_valid)) begin`
299			state <= #1 `OR1200_DCFSM_IDLE;
300			`store <= #1 1'b0;`
301			`end`
302	10	unneback	`ifdef OR1200_DC_STORE_REFILL
303	141	marcus.erl	`OR1200_DCFSM_SREFILL4 : begin
304			`if (!dc_en) begin // somebody just turned off DC therefore we abort`
305			`cnt <= #1 3'd0; // DC will have to be invalidated before`
306			state <= #1 `OR1200_DCFSM_IDLE; // it can be turned on again
307			`load <= #1 1'b0;`
308			`end`
309			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
310			`cnt <= #1 cnt - 1'd1;`
311			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;`
312			`end`
313			`else if (biudata_valid) begin // last load of line refill`
314			state <= #1 `OR1200_DCFSM_IDLE;
315			`load <= #1 1'b0;`
316			`end`
317	10	unneback	`endif
318	141	marcus.erl	`end`
319
320			`default:`
321			state <= #1 `OR1200_DCFSM_IDLE;
322			`endcase`
323	10	unneback	`end`
324
325			`endmodule`

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