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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 162

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_ram.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
// Revision 1.6  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.2  2003/12/10 15:28:28  simons
// Support for ram with byte selects added.
//
// Revision 1.2.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                          mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
   or1200_spram_32_bw #
     (
      .aw(10),
      .dw(32)
      )
`endif
`ifdef OR1200_DC_1W_8KB
   or1200_spram_32_bw #
     (
      .aw(11),
      .dw(32)
      )
`endif
   dc_ram
     (
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_si_i),
      .mbist_so_o(mbist_so_o),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .clk(clk),
      .ce(en),
      .we(we),
      .addr(addr),
      .di(datain),
      .doq(dataout)
      );
`endif
 
endmodule // or1200_dc_ram

Line No.	Rev	Author	Line
1	10	unneback
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's DC RAMs ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// Instatiation of DC RAM blocks. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47	141	marcus.erl	`// $Log: or1200_dc_ram.v,v $`
48			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
49			`// Minor update:`
50			`// Coding style changed.`
51			`//`
52			`// Revision 1.6 2004/06/08 18:17:36 lampret`
53			`// Non-functional changes. Coding style fixes.`
54			`//`
55	10	unneback	`// Revision 1.5 2004/04/05 08:29:57 lampret`
56			`// Merged branch_qmem into main tree.`
57			`//`
58			`// Revision 1.2.4.2 2003/12/10 15:28:28 simons`
59			`// Support for ram with byte selects added.`
60			`//`
61			`// Revision 1.2.4.1 2003/12/09 11:46:48 simons`
62			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
63			`//`
64			`// Revision 1.2 2002/10/17 20:04:40 lampret`
65			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
66			`//`
67			`// Revision 1.1 2002/01/03 08:16:15 lampret`
68			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
69			`//`
70			`// Revision 1.8 2001/10/21 17:57:16 lampret`
71			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
72			`//`
73			`// Revision 1.7 2001/10/14 13:12:09 lampret`
74			`// MP3 version.`
75			`//`
76			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
77			`// no message`
78			`//`
79			`// Revision 1.2 2001/08/09 13:39:33 lampret`
80			`// Major clean-up.`
81			`//`
82			`// Revision 1.1 2001/07/20 00:46:03 lampret`
83			`// Development version of RTL. Libraries are missing.`
84			`//`
85			`//`
86
87			`// synopsys translate_off`
88			`include "timescale.v"
89			`// synopsys translate_on`
90			`include "or1200_defines.v"
91
92			`module or1200_dc_ram(`
93			`// Reset and clock`
94			`clk, rst,`
95
96			`ifdef OR1200_BIST
97			`// RAM BIST`
98			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
99			`endif
100
101			`// Internal i/f`
102			`addr, en, we, datain, dataout`
103			`);`
104
105			parameter dw = `OR1200_OPERAND_WIDTH;
106			parameter aw = `OR1200_DCINDX;
107
108			`//`
109			`// I/O`
110			`//`
111			`input clk;`
112			`input rst;`
113			`input [aw-1:0] addr;`
114			`input en;`
115			`input [3:0] we;`
116			`input [dw-1:0] datain;`
117			`output [dw-1:0] dataout;`
118
119			`ifdef OR1200_BIST
120			`//`
121			`// RAM BIST`
122			`//`
123			`input mbist_si_i;`
124			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
125			`output mbist_so_o;`
126			`endif
127
128			`ifdef OR1200_NO_DC
129
130			`//`
131			`// Data cache not implemented`
132			`//`
133			`assign dataout = {dw{1'b0}};`
134			`ifdef OR1200_BIST
135			`assign mbist_so_o = mbist_si_i;`
136			`endif
137
138			`else
139
140			`//`
141			`// Instantiation of RAM block`
142			`//`
143			`ifdef OR1200_DC_1W_4KB
144	141	marcus.erl	`or1200_spram_32_bw #`
145			`(`
146			`.aw(10),`
147			`.dw(32)`
148			`)`
149	10	unneback	`endif
150			`ifdef OR1200_DC_1W_8KB
151	141	marcus.erl	`or1200_spram_32_bw #`
152			`(`
153			`.aw(11),`
154			`.dw(32)`
155			`)`
156	10	unneback	`endif
157	141	marcus.erl	`dc_ram`
158			`(`
159	10	unneback	`ifdef OR1200_BIST
160	141	marcus.erl	`// RAM BIST`
161			`.mbist_si_i(mbist_si_i),`
162			`.mbist_so_o(mbist_so_o),`
163			`.mbist_ctrl_i(mbist_ctrl_i),`
164	10	unneback	`endif
165	141	marcus.erl	`.clk(clk),`
166			`.ce(en),`
167			`.we(we),`
168			`.addr(addr),`
169			`.di(datain),`
170			`.doq(dataout)`
171			`);`
172	10	unneback	`endif
173	141	marcus.erl
174			`endmodule // or1200_dc_ram`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 162