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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Blame information for rev 146

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all DC blocks.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_dc_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Bugs fixed. 
50
//
51
// Revision 1.8  2004/04/05 08:29:57  lampret
52
// Merged branch_qmem into main tree.
53
//
54 10 unneback
// Revision 1.6.4.2  2003/12/09 11:46:48  simons
55
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
56
//
57
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
58
// Added embedded memory QMEM.
59
//
60
// Revision 1.6  2002/10/17 20:04:40  lampret
61
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
62
//
63
// Revision 1.5  2002/08/18 19:54:47  lampret
64
// Added store buffer.
65
//
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// Revision 1.4  2002/02/11 04:33:17  lampret
67
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
69
// Revision 1.3  2002/01/28 01:16:00  lampret
70
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
71
//
72
// Revision 1.2  2002/01/14 06:18:22  lampret
73
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
74
//
75
// Revision 1.1  2002/01/03 08:16:15  lampret
76
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
78
// Revision 1.10  2001/10/21 17:57:16  lampret
79
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
80
//
81
// Revision 1.9  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.4  2001/08/13 03:36:20  lampret
88
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
90
// Revision 1.3  2001/08/09 13:39:33  lampret
91
// Major clean-up.
92
//
93
// Revision 1.2  2001/07/22 03:31:53  lampret
94
// Fixed RAM's oen bug. Cache bypass under development.
95
//
96
// Revision 1.1  2001/07/20 00:46:03  lampret
97
// Development version of RTL. Libraries are missing.
98
//
99
//
100
 
101
// synopsys translate_off
102
`include "timescale.v"
103
// synopsys translate_on
104
`include "or1200_defines.v"
105
 
106
//
107
// Data cache
108
//
109
module or1200_dc_top(
110
        // Rst, clk and clock control
111
        clk, rst,
112
 
113
        // External i/f
114
        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
115
        dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
116
 
117
        // Internal i/f
118
        dc_en,
119
        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
120
        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
121
        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
122
 
123
`ifdef OR1200_BIST
124
        // RAM BIST
125
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
126
`endif
127
 
128
        // SPRs
129
        spr_cs, spr_write, spr_dat_i
130
);
131
 
132
parameter dw = `OR1200_OPERAND_WIDTH;
133
 
134
//
135
// I/O
136
//
137
 
138
//
139
// Clock and reset
140
//
141
input                           clk;
142
input                           rst;
143
 
144
//
145
// External I/F
146
//
147
output  [dw-1:0]         dcsb_dat_o;
148
output  [31:0]                   dcsb_adr_o;
149
output                          dcsb_cyc_o;
150
output                          dcsb_stb_o;
151
output                          dcsb_we_o;
152
output  [3:0]                    dcsb_sel_o;
153
output                          dcsb_cab_o;
154
input   [dw-1:0]         dcsb_dat_i;
155
input                           dcsb_ack_i;
156
input                           dcsb_err_i;
157
 
158
//
159
// Internal I/F
160
//
161
input                           dc_en;
162
input   [31:0]                   dcqmem_adr_i;
163
input                           dcqmem_cycstb_i;
164
input                           dcqmem_ci_i;
165
input                           dcqmem_we_i;
166
input   [3:0]                    dcqmem_sel_i;
167
input   [3:0]                    dcqmem_tag_i;
168
input   [dw-1:0]         dcqmem_dat_i;
169
output  [dw-1:0]         dcqmem_dat_o;
170
output                          dcqmem_ack_o;
171
output                          dcqmem_rty_o;
172
output                          dcqmem_err_o;
173
output  [3:0]                    dcqmem_tag_o;
174
 
175
`ifdef OR1200_BIST
176
//
177
// RAM BIST
178
//
179
input mbist_si_i;
180
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
181
output mbist_so_o;
182
`endif
183
 
184
//
185
// SPR access
186
//
187
input                           spr_cs;
188
input                           spr_write;
189
input   [31:0]                   spr_dat_i;
190
 
191
//
192
// Internal wires and regs
193
//
194
wire                            tag_v;
195
wire    [`OR1200_DCTAG_W-2:0]    tag;
196
wire    [dw-1:0]         to_dcram;
197
wire    [dw-1:0]         from_dcram;
198
wire    [31:0]                   saved_addr;
199
wire    [3:0]                    dcram_we;
200
wire                            dctag_we;
201
wire    [31:0]                   dc_addr;
202
wire                            dcfsm_biu_read;
203
wire                            dcfsm_biu_write;
204 141 marcus.erl
wire                dcfsm_biu_sel;
205 10 unneback
reg                             tagcomp_miss;
206
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
207
wire                            dctag_en;
208
wire                            dctag_v;
209
wire                            dc_inv;
210
wire                            dcfsm_first_hit_ack;
211
wire                            dcfsm_first_miss_ack;
212
wire                            dcfsm_first_miss_err;
213
wire                            dcfsm_burst;
214
wire                            dcfsm_tag_we;
215 141 marcus.erl
wire                dcfsm_tag_valid;
216 10 unneback
`ifdef OR1200_BIST
217
//
218
// RAM BIST
219
//
220
wire                            mbist_ram_so;
221
wire                            mbist_tag_so;
222
wire                            mbist_ram_si = mbist_si_i;
223
wire                            mbist_tag_si = mbist_ram_so;
224
assign                          mbist_so_o = mbist_tag_so;
225
`endif
226
 
227
//
228
// Simple assignments
229
//
230
assign dcsb_adr_o = dc_addr;
231
assign dc_inv = spr_cs & spr_write;
232
assign dctag_we = dcfsm_tag_we | dc_inv;
233
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
234
assign dctag_en = dc_inv | dc_en;
235 141 marcus.erl
//assign dctag_v = ~dc_inv;
236
assign dctag_v = dc_inv ? 1'b0 : dcfsm_tag_valid;
237 10 unneback
 
238
//
239
// Data to BIU is from DCRAM when DC is enabled or from LSU when
240
// DC is disabled
241
//
242
assign dcsb_dat_o = dcqmem_dat_i;
243
 
244
//
245
// Bypases of the DC when DC is disabled
246
//
247
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
248
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
249
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
250 141 marcus.erl
//assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
251
assign dcsb_sel_o = (dc_en & dcfsm_burst) ? 4'b1111 : dcqmem_sel_i;
252
//assign dcsb_cab_o = (dc_en) ? dcsb_cyc_o & dcfsm_burst : 1'b0;
253
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
254 10 unneback
assign dcqmem_rty_o = ~dcqmem_ack_o;
255
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
256
 
257
//
258
// DC/LSU normal and error termination
259
//
260
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
261
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
262
 
263
//
264
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
265
//
266
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
267
 
268
//
269
// Select between input data generated by LSU or by BIU
270
//
271 141 marcus.erl
//assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
272
assign to_dcram = (dcfsm_biu_sel) ? dcsb_dat_i : dcqmem_dat_i;
273 10 unneback
 
274
//
275
// Select between data generated by DCRAM or passed by BIU
276
//
277
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
278
 
279
//
280
// Tag comparison
281
//
282 141 marcus.erl
//always @(tag or saved_addr or tag_v) begin
283
//      if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
284
always @(tag or dcqmem_adr_i or tag_v) begin
285
        if ((tag != dcqmem_adr_i[31:`OR1200_DCTAGL]) || !tag_v)
286 10 unneback
                tagcomp_miss = 1'b1;
287
        else
288
                tagcomp_miss = 1'b0;
289
end
290
 
291
//
292
// Instantiation of DC Finite State Machine
293
//
294
or1200_dc_fsm or1200_dc_fsm(
295
        .clk(clk),
296
        .rst(rst),
297
        .dc_en(dc_en),
298
        .dcqmem_cycstb_i(dcqmem_cycstb_i),
299
        .dcqmem_ci_i(dcqmem_ci_i),
300
        .dcqmem_we_i(dcqmem_we_i),
301
        .dcqmem_sel_i(dcqmem_sel_i),
302
        .tagcomp_miss(tagcomp_miss),
303
        .biudata_valid(dcsb_ack_i),
304
        .biudata_error(dcsb_err_i),
305
        .start_addr(dcqmem_adr_i),
306
        .saved_addr(saved_addr),
307
        .dcram_we(dcram_we),
308
        .biu_read(dcfsm_biu_read),
309
        .biu_write(dcfsm_biu_write),
310 141 marcus.erl
    .biu_sel(dcfsm_biu_sel),
311 10 unneback
        .first_hit_ack(dcfsm_first_hit_ack),
312
        .first_miss_ack(dcfsm_first_miss_ack),
313
        .first_miss_err(dcfsm_first_miss_err),
314
        .burst(dcfsm_burst),
315
        .tag_we(dcfsm_tag_we),
316 141 marcus.erl
    .tag_valid(dcfsm_tag_valid),
317 10 unneback
        .dc_addr(dc_addr)
318
);
319
 
320
//
321
// Instantiation of DC main memory
322
//
323
or1200_dc_ram or1200_dc_ram(
324
        .clk(clk),
325
        .rst(rst),
326
`ifdef OR1200_BIST
327
        // RAM BIST
328
        .mbist_si_i(mbist_ram_si),
329
        .mbist_so_o(mbist_ram_so),
330
        .mbist_ctrl_i(mbist_ctrl_i),
331
`endif
332
        .addr(dc_addr[`OR1200_DCINDXH:2]),
333
        .en(dc_en),
334
        .we(dcram_we),
335
        .datain(to_dcram),
336
        .dataout(from_dcram)
337
);
338
 
339
//
340
// Instantiation of DC TAG memory
341
//
342
or1200_dc_tag or1200_dc_tag(
343
        .clk(clk),
344
        .rst(rst),
345
`ifdef OR1200_BIST
346
        // RAM BIST
347
        .mbist_si_i(mbist_tag_si),
348
        .mbist_so_o(mbist_tag_so),
349
        .mbist_ctrl_i(mbist_ctrl_i),
350
`endif
351
        .addr(dctag_addr),
352
        .en(dctag_en),
353
        .we(dctag_we),
354
        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
355
        .tag_v(tag_v),
356
        .tag(tag)
357
);
358
 
359
endmodule

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