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1 10 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's definitions                                        ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Parameters of the OR1200 core                               ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - add parameters that are missing                          ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 141 marcus.erl 
// $Log: or1200_defines.v,v $
47 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48 
// Minor update:
49 
// Defines added, bugs fixed.
50 
//
51 
// Revision 1.45  2006/04/09 01:32:29  lampret
52 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
53 
//
54 10 unneback 
// Revision 1.44  2005/10/19 11:37:56  jcastillo
55 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
56 
//
57 
// Revision 1.43  2005/01/07 09:23:39  andreje
58 
// l.ff1 and l.cmov instructions added
59 
//
60 
// Revision 1.42  2004/06/08 18:17:36  lampret
61 
// Non-functional changes. Coding style fixes.
62 
//
63 
// Revision 1.41  2004/05/09 20:03:20  lampret
64 
// By default l.cust5 insns are disabled
65 
//
66 
// Revision 1.40  2004/05/09 19:49:04  lampret
67 
// Added some l.cust5 custom instructions as example
68 
//
69 
// Revision 1.39  2004/04/08 11:00:46  simont
70 
// Add support for 512B instruction cache.
71 
//
72 
// Revision 1.38  2004/04/05 08:29:57  lampret
73 
// Merged branch_qmem into main tree.
74 
//
75 
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
76 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
77 
//
78 
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
79 
// interface to debug changed; no more opselect; stb-ack protocol
80 
//
81 
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
82 
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
83 
//
84 
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
85 
// Exception prefix configuration changed.
86 
//
87 
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
88 
// Static exception prefix.
89 
//
90 
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
91 
// Added embedded memory QMEM.
92 
//
93 
// Revision 1.35  2003/04/24 00:16:07  lampret
94 
// No functional changes. Added defines to disable implementation of multiplier/MAC
95 
//
96 
// Revision 1.34  2003/04/20 22:23:57  lampret
97 
// No functional change. Only added customization for exception vectors.
98 
//
99 
// Revision 1.33  2003/04/07 20:56:07  lampret
100 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
101 
//
102 
// Revision 1.32  2003/04/07 01:26:57  lampret
103 
// RFRAM defines comments updated. Altera LPM option added.
104 
//
105 
// Revision 1.31  2002/12/08 08:57:56  lampret
106 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
107 
//
108 
// Revision 1.30  2002/10/28 15:09:22  mohor
109 
// Previous check-in was done by mistake.
110 
//
111 
// Revision 1.29  2002/10/28 15:03:50  mohor
112 
// Signal scanb_sen renamed to scanb_en.
113 
//
114 
// Revision 1.28  2002/10/17 20:04:40  lampret
115 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
116 
//
117 
// Revision 1.27  2002/09/16 03:13:23  lampret
118 
// Removed obsolete comment.
119 
//
120 
// Revision 1.26  2002/09/08 05:52:16  lampret
121 
// Added optional l.div/l.divu insns. By default they are disabled.
122 
//
123 
// Revision 1.25  2002/09/07 19:16:10  lampret
124 
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
125 
//
126 
// Revision 1.24  2002/09/07 05:42:02  lampret
127 
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
128 
//
129 
// Revision 1.23  2002/09/04 00:50:34  lampret
130 
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
131 
//
132 
// Revision 1.22  2002/09/03 22:28:21  lampret
133 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
134 
//
135 
// Revision 1.21  2002/08/22 02:18:55  lampret
136 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
137 
//
138 
// Revision 1.20  2002/08/18 21:59:45  lampret
139 
// Disable SB until it is tested
140 
//
141 
// Revision 1.19  2002/08/18 19:53:08  lampret
142 
// Added store buffer.
143 
//
144 
// Revision 1.18  2002/08/15 06:04:11  lampret
145 
// Fixed Xilinx trace buffer address. REported by Taylor Su.
146 
//
147 
// Revision 1.17  2002/08/12 05:31:44  lampret
148 
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
149 
//
150 
// Revision 1.16  2002/07/14 22:17:17  lampret
151 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
152 
//
153 
// Revision 1.15  2002/06/08 16:20:21  lampret
154 
// Added defines for enabling generic FF based memory macro for register file.
155 
//
156 
// Revision 1.14  2002/03/29 16:24:06  lampret
157 
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
158 
//
159 
// Revision 1.13  2002/03/29 15:16:55  lampret
160 
// Some of the warnings fixed.
161 
//
162 
// Revision 1.12  2002/03/28 19:25:42  lampret
163 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
164 
//
165 
// Revision 1.11  2002/03/28 19:13:17  lampret
166 
// Updated defines.
167 
//
168 
// Revision 1.10  2002/03/14 00:30:24  lampret
169 
// Added alternative for critical path in DU.
170 
//
171 
// Revision 1.9  2002/03/11 01:26:26  lampret
172 
// Fixed async loop. Changed multiplier type for ASIC.
173 
//
174 
// Revision 1.8  2002/02/11 04:33:17  lampret
175 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
176 
//
177 
// Revision 1.7  2002/02/01 19:56:54  lampret
178 
// Fixed combinational loops.
179 
//
180 
// Revision 1.6  2002/01/19 14:10:22  lampret
181 
// Fixed OR1200_XILINX_RAM32X1D.
182 
//
183 
// Revision 1.5  2002/01/18 07:56:00  lampret
184 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
185 
//
186 
// Revision 1.4  2002/01/14 09:44:12  lampret
187 
// Default ASIC configuration does not sample WB inputs.
188 
//
189 
// Revision 1.3  2002/01/08 00:51:08  lampret
190 
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
191 
//
192 
// Revision 1.2  2002/01/03 21:23:03  lampret
193 
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
194 
//
195 
// Revision 1.1  2002/01/03 08:16:15  lampret
196 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
197 
//
198 
// Revision 1.20  2001/12/04 05:02:36  lampret
199 
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
200 
//
201 
// Revision 1.19  2001/11/27 19:46:57  lampret
202 
// Now FPGA and ASIC target are separate.
203 
//
204 
// Revision 1.18  2001/11/23 21:42:31  simons
205 
// Program counter divided to PPC and NPC.
206 
//
207 
// Revision 1.17  2001/11/23 08:38:51  lampret
208 
// Changed DSR/DRR behavior and exception detection.
209 
//
210 
// Revision 1.16  2001/11/20 21:30:38  lampret
211 
// Added OR1200_REGISTERED_INPUTS.
212 
//
213 
// Revision 1.15  2001/11/19 14:29:48  simons
214 
// Cashes disabled.
215 
//
216 
// Revision 1.14  2001/11/13 10:02:21  lampret
217 
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
218 
//
219 
// Revision 1.13  2001/11/12 01:45:40  lampret
220 
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
221 
//
222 
// Revision 1.12  2001/11/10 03:43:57  lampret
223 
// Fixed exceptions.
224 
//
225 
// Revision 1.11  2001/11/02 18:57:14  lampret
226 
// Modified virtual silicon instantiations.
227 
//
228 
// Revision 1.10  2001/10/21 17:57:16  lampret
229 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
230 
//
231 
// Revision 1.9  2001/10/19 23:28:46  lampret
232 
// Fixed some synthesis warnings. Configured with caches and MMUs.
233 
//
234 
// Revision 1.8  2001/10/14 13:12:09  lampret
235 
// MP3 version.
236 
//
237 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
238 
// no message
239 
//
240 
// Revision 1.3  2001/08/17 08:01:19  lampret
241 
// IC enable/disable.
242 
//
243 
// Revision 1.2  2001/08/13 03:36:20  lampret
244 
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
245 
//
246 
// Revision 1.1  2001/08/09 13:39:33  lampret
247 
// Major clean-up.
248 
//
249 
// Revision 1.2  2001/07/22 03:31:54  lampret
250 
// Fixed RAM's oen bug. Cache bypass under development.
251 
//
252 
// Revision 1.1  2001/07/20 00:46:03  lampret
253 
// Development version of RTL. Libraries are missing.
254 
//
255 
//
256 
 
257 
//
258 
// Dump VCD
259 
//
260 
//`define OR1200_VCD_DUMP
261 
 
262 
//
263 
// Generate debug messages during simulation
264 
//
265 
//`define OR1200_VERBOSE
266 
 
267 
//  `define OR1200_ASIC
268 
////////////////////////////////////////////////////////
269 
//
270 
// Typical configuration for an ASIC
271 
//
272 
`ifdef OR1200_ASIC
273 
 
274 
//
275 
// Target ASIC memories
276 
//
277 
//`define OR1200_ARTISAN_SSP
278 
//`define OR1200_ARTISAN_SDP
279 
//`define OR1200_ARTISAN_STP
280 
`define OR1200_VIRTUALSILICON_SSP
281 
//`define OR1200_VIRTUALSILICON_STP_T1
282 
//`define OR1200_VIRTUALSILICON_STP_T2
283 
 
284 
//
285 
// Do not implement Data cache
286 
//
287 
//`define OR1200_NO_DC
288 
 
289 
//
290 
// Do not implement Insn cache
291 
//
292 
//`define OR1200_NO_IC
293 
 
294 
//
295 
// Do not implement Data MMU
296 
//
297 
//`define OR1200_NO_DMMU
298 
 
299 
//
300 
// Do not implement Insn MMU
301 
//
302 
//`define OR1200_NO_IMMU
303 
 
304 
//
305 
// Select between ASIC optimized and generic multiplier
306 
//
307 
//`define OR1200_ASIC_MULTP2_32X32
308 
`define OR1200_GENERIC_MULTP2_32X32
309 
 
310 
//
311 
// Size/type of insn/data cache if implemented
312 
//
313 
// `define OR1200_IC_1W_512B
314 
// `define OR1200_IC_1W_4KB
315 
`define OR1200_IC_1W_8KB
316 
// `define OR1200_DC_1W_4KB
317 
`define OR1200_DC_1W_8KB
318 
 
319 
`else
320 
 
321 
 
322 
/////////////////////////////////////////////////////////
323 
//
324 
// Typical configuration for an FPGA
325 
//
326 
 
327 
//
328 
// Target FPGA memories
329 
//
330 
//`define OR1200_ALTERA_LPM
331 
//`define OR1200_XILINX_RAMB16
332 
//`define OR1200_XILINX_RAMB4
333 
//`define OR1200_XILINX_RAM32X1D
334 
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
335 141 marcus.erl 
`define OR1200_ACTEL
336 10 unneback 
 
337 
//
338 
// Do not implement Data cache
339 
//
340 
`define OR1200_NO_DC
341 
 
342 
//
343 
// Do not implement Insn cache
344 
//
345 141 marcus.erl 
//`define OR1200_NO_IC
346 10 unneback 
 
347 
//
348 
// Do not implement Data MMU
349 
//
350 141 marcus.erl 
//`define OR1200_NO_DMMU
351 10 unneback 
 
352 
//
353 
// Do not implement Insn MMU
354 
//
355 141 marcus.erl 
//`define OR1200_NO_IMMU
356 10 unneback 
 
357 
//
358 
// Select between ASIC and generic multiplier
359 
//
360 
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
361 
//
362 
//`define OR1200_ASIC_MULTP2_32X32
363 
`define OR1200_GENERIC_MULTP2_32X32
364 
 
365 
//
366 
// Size/type of insn/data cache if implemented
367 
// (consider available FPGA memory resources)
368 
//
369 
//`define OR1200_IC_1W_512B
370 141 marcus.erl 
//`define OR1200_IC_1W_4KB
371 
`define OR1200_IC_1W_8KB
372 10 unneback 
`define OR1200_DC_1W_4KB
373 
//`define OR1200_DC_1W_8KB
374 
 
375 
`endif
376 
 
377 
 
378 
//////////////////////////////////////////////////////////
379 
//
380 
// Do not change below unless you know what you are doing
381 
//
382 
 
383 
//
384 
// Enable RAM BIST
385 
//
386 
// At the moment this only works for Virtual Silicon
387 
// single port RAMs. For other RAMs it has not effect.
388 
// Special wrapper for VS RAMs needs to be provided
389 
// with scan flops to facilitate bist scan.
390 
//
391 
//`define OR1200_BIST
392 
 
393 
//
394 
// Register OR1200 WISHBONE outputs
395 
// (must be defined/enabled)
396 
//
397 
`define OR1200_REGISTERED_OUTPUTS
398 
 
399 
//
400 
// Register OR1200 WISHBONE inputs
401 
//
402 
// (must be undefined/disabled)
403 
//
404 
//`define OR1200_REGISTERED_INPUTS
405 
 
406 
//
407 
// Disable bursts if they are not supported by the
408 
// memory subsystem (only affect cache line fill)
409 
//
410 
//`define OR1200_NO_BURSTS
411 
//
412 
 
413 
//
414 
// WISHBONE retry counter range
415 
//
416 
// 2^value range for retry counter. Retry counter
417 
// is activated whenever *wb_rty_i is asserted and
418 
// until retry counter expires, corresponding
419 
// WISHBONE interface is deactivated.
420 
//
421 
// To disable retry counters and *wb_rty_i all together,
422 
// undefine this macro.
423 
//
424 
//`define OR1200_WB_RETRY 7
425 
 
426 
//
427 
// WISHBONE Consecutive Address Burst
428 
//
429 
// This was used prior to WISHBONE B3 specification
430 
// to identify bursts. It is no longer needed but
431 
// remains enabled for compatibility with old designs.
432 
//
433 
// To remove *wb_cab_o ports undefine this macro.
434 
//
435 141 marcus.erl 
//`define OR1200_WB_CAB
436 10 unneback 
 
437 
//
438 
// WISHBONE B3 compatible interface
439 
//
440 
// This follows the WISHBONE B3 specification.
441 
// It is not enabled by default because most
442 
// designs still don't use WB b3.
443 
//
444 
// To enable *wb_cti_o/*wb_bte_o ports,
445 
// define this macro.
446 
//
447 141 marcus.erl 
`define OR1200_WB_B3
448 10 unneback 
 
449 
//
450 141 marcus.erl 
// LOG all WISHBONE accesses
451 
//
452 
`define OR1200_LOG_WB_ACCESS
453 
 
454 
//
455 10 unneback 
// Enable additional synthesis directives if using
456 
// _Synopsys_ synthesis tool
457 
//
458 
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
459 
 
460 
//
461 
// Enables default statement in some case blocks
462 
// and disables Synopsys synthesis directive full_case
463 
//
464 
// By default it is enabled. When disabled it
465 
// can increase clock frequency.
466 
//
467 
`define OR1200_CASE_DEFAULT
468 
 
469 
//
470 
// Operand width / register file address width
471 
//
472 
// (DO NOT CHANGE)
473 
//
474 
`define OR1200_OPERAND_WIDTH            32
475 
`define OR1200_REGFILE_ADDR_WIDTH       5
476 
 
477 
//
478 
// l.add/l.addi/l.and and optional l.addc/l.addic
479 
// also set (compare) flag when result of their
480 
// operation equals zero
481 
//
482 
// At the time of writing this, default or32
483 
// C/C++ compiler doesn't generate code that
484 
// would benefit from this optimization.
485 
//
486 
// By default this optimization is disabled to
487 
// save area.
488 
//
489 
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
490 
 
491 
//
492 
// Implement l.addc/l.addic instructions
493 
//
494 
// By default implementation of l.addc/l.addic
495 
// instructions is enabled in case you need them.
496 
// If you don't use them, then disable implementation
497 
// to save area.
498 
//
499 141 marcus.erl 
//`define OR1200_IMPL_ADDC
500 10 unneback 
 
501 
//
502 141 marcus.erl 
// Implement l.sub instruction
503 
//
504 
// By default implementation of l.sub instructions
505 
// is enabled to be compliant with the simulator.
506 
// If you don't use carry bit, then disable
507 
// implementation to save area.
508 
//
509 
`define OR1200_IMPL_SUB
510 
 
511 
//
512 10 unneback 
// Implement carry bit SR[CY]
513 
//
514 141 marcus.erl 
//
515 10 unneback 
// By default implementation of SR[CY] is enabled
516 141 marcus.erl 
// to be compliant with the simulator. However SR[CY]
517 
// is explicitly only used by l.addc/l.addic/l.sub
518 
// instructions and if these three insns are not
519 10 unneback 
// implemented there is not much point having SR[CY].
520 
//
521 141 marcus.erl 
//`define OR1200_IMPL_CY
522 10 unneback 
 
523 
//
524 
// Implement optional l.div/l.divu instructions
525 
//
526 
// By default divide instructions are not implemented
527 
// to save area and increase clock frequency. or32 C/C++
528 
// compiler can use soft library for division.
529 
//
530 
// To implement divide, multiplier needs to be implemented.
531 
//
532 
//`define OR1200_IMPL_DIV
533 
 
534 
//
535 
// Implement rotate in the ALU
536 
//
537 
// At the time of writing this, or32
538 
// C/C++ compiler doesn't generate rotate
539 
// instructions. However or32 assembler
540 
// can assemble code that uses rotate insn.
541 
// This means that rotate instructions
542 
// must be used manually inserted.
543 
//
544 
// By default implementation of rotate
545 
// is disabled to save area and increase
546 
// clock frequency.
547 
//
548 
//`define OR1200_IMPL_ALU_ROTATE
549 
 
550 
//
551 
// Type of ALU compare to implement
552 
//
553 
// Try either one to find what yields
554 
// higher clock frequencyin your case.
555 
//
556 
//`define OR1200_IMPL_ALU_COMP1
557 
`define OR1200_IMPL_ALU_COMP2
558 
 
559 
//
560 
// Implement multiplier
561 
//
562 
// By default multiplier is implemented
563 
//
564 141 marcus.erl 
//`define OR1200_MULT_IMPLEMENTED
565 10 unneback 
 
566 
//
567 
// Implement multiply-and-accumulate
568 
//
569 
// By default MAC is implemented. To
570 
// implement MAC, multiplier needs to be
571 
// implemented.
572 
//
573 141 marcus.erl 
//`define OR1200_MAC_IMPLEMENTED
574 10 unneback 
 
575 
//
576 
// Low power, slower multiplier
577 
//
578 
// Select between low-power (larger) multiplier
579 
// and faster multiplier. The actual difference
580 
// is only AND logic that prevents distribution
581 
// of operands into the multiplier when instruction
582 
// in execution is not multiply instruction
583 
//
584 
//`define OR1200_LOWPWR_MULT
585 
 
586 
//
587 
// Clock ratio RISC clock versus WB clock
588 
//
589 
// If you plan to run WB:RISC clock fixed to 1:1, disable
590 
// both defines
591 
//
592 
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
593 
// and use clmode to set ratio
594 
//
595 
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
596 
// clmode to set ratio
597 
//
598 141 marcus.erl 
//`define OR1200_CLKDIV_2_SUPPORTED
599 10 unneback 
//`define OR1200_CLKDIV_4_SUPPORTED
600 
 
601 
//
602 
// Type of register file RAM
603 
//
604 
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
605 
//`define OR1200_RFRAM_TWOPORT
606 
//
607 
// Memory macro dual port (see or1200_dpram_32x32.v)
608 141 marcus.erl 
`define OR1200_RFRAM_DUALPORT
609 
 
610 10 unneback 
//
611 
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
612 141 marcus.erl 
//`define OR1200_RFRAM_GENERIC
613 
//  Generic register file supports - 16 registers
614 
`ifdef OR1200_RFRAM_GENERIC
615 
//    `define OR1200_RFRAM_16REG
616 
`endif
617 10 unneback 
 
618 
//
619 
// Type of mem2reg aligner to implement.
620 
//
621 
// Once OR1200_IMPL_MEM2REG2 yielded faster
622 
// circuit, however with today tools it will
623 
// most probably give you slower circuit.
624 
//
625 
`define OR1200_IMPL_MEM2REG1
626 
//`define OR1200_IMPL_MEM2REG2
627 
 
628 
//
629 
// ALUOPs
630 
//
631 
`define OR1200_ALUOP_WIDTH      4
632 
`define OR1200_ALUOP_NOP        4'd4
633 
/* Order defined by arith insns that have two source operands both in regs
634 
   (see binutils/include/opcode/or32.h) */
635 
`define OR1200_ALUOP_ADD        4'd0
636 
`define OR1200_ALUOP_ADDC       4'd1
637 
`define OR1200_ALUOP_SUB        4'd2
638 
`define OR1200_ALUOP_AND        4'd3
639 
`define OR1200_ALUOP_OR         4'd4
640 
`define OR1200_ALUOP_XOR        4'd5
641 
`define OR1200_ALUOP_MUL        4'd6
642 
`define OR1200_ALUOP_CUST5      4'd7
643 
`define OR1200_ALUOP_SHROT      4'd8
644 
`define OR1200_ALUOP_DIV        4'd9
645 
`define OR1200_ALUOP_DIVU       4'd10
646 
/* Order not specifically defined. */
647 
`define OR1200_ALUOP_IMM        4'd11
648 
`define OR1200_ALUOP_MOVHI      4'd12
649 
`define OR1200_ALUOP_COMP       4'd13
650 
`define OR1200_ALUOP_MTSR       4'd14
651 
`define OR1200_ALUOP_MFSR       4'd15
652 141 marcus.erl 
`define OR1200_ALUOP_CMOV       4'd14
653 
`define OR1200_ALUOP_FF1        4'd15
654 10 unneback 
//
655 
// MACOPs
656 
//
657 141 marcus.erl 
`define OR1200_MACOP_WIDTH      3
658 
`define OR1200_MACOP_NOP        3'b000
659 
`define OR1200_MACOP_MAC        3'b001
660 
`define OR1200_MACOP_MSB        3'b010
661 10 unneback 
 
662 
//
663 
// Shift/rotate ops
664 
//
665 
`define OR1200_SHROTOP_WIDTH    2
666 
`define OR1200_SHROTOP_NOP      2'd0
667 
`define OR1200_SHROTOP_SLL      2'd0
668 
`define OR1200_SHROTOP_SRL      2'd1
669 
`define OR1200_SHROTOP_SRA      2'd2
670 
`define OR1200_SHROTOP_ROR      2'd3
671 
 
672 
// Execution cycles per instruction
673 
`define OR1200_MULTICYCLE_WIDTH 2
674 
`define OR1200_ONE_CYCLE                2'd0
675 
`define OR1200_TWO_CYCLES               2'd1
676 
 
677 
// Operand MUX selects
678 
`define OR1200_SEL_WIDTH                2
679 
`define OR1200_SEL_RF                   2'd0
680 
`define OR1200_SEL_IMM                  2'd1
681 
`define OR1200_SEL_EX_FORW              2'd2
682 
`define OR1200_SEL_WB_FORW              2'd3
683 
 
684 
//
685 
// BRANCHOPs
686 
//
687 
`define OR1200_BRANCHOP_WIDTH           3
688 
`define OR1200_BRANCHOP_NOP             3'd0
689 
`define OR1200_BRANCHOP_J               3'd1
690 
`define OR1200_BRANCHOP_JR              3'd2
691 
`define OR1200_BRANCHOP_BAL             3'd3
692 
`define OR1200_BRANCHOP_BF              3'd4
693 
`define OR1200_BRANCHOP_BNF             3'd5
694 
`define OR1200_BRANCHOP_RFE             3'd6
695 
 
696 
//
697 
// LSUOPs
698 
//
699 
// Bit 0: sign extend
700 
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
701 
// Bit 3: 0 load, 1 store
702 
`define OR1200_LSUOP_WIDTH              4
703 
`define OR1200_LSUOP_NOP                4'b0000
704 
`define OR1200_LSUOP_LBZ                4'b0010
705 
`define OR1200_LSUOP_LBS                4'b0011
706 
`define OR1200_LSUOP_LHZ                4'b0100
707 
`define OR1200_LSUOP_LHS                4'b0101
708 
`define OR1200_LSUOP_LWZ                4'b0110
709 
`define OR1200_LSUOP_LWS                4'b0111
710 141 marcus.erl 
`define OR1200_LSUOP_LD                 4'b0001
711 
`define OR1200_LSUOP_SD                 4'b1000
712 
`define OR1200_LSUOP_SB                 4'b1010
713 
`define OR1200_LSUOP_SH                 4'b1100
714 
`define OR1200_LSUOP_SW                 4'b1110
715 10 unneback 
 
716 141 marcus.erl 
// Number of bits of load/store EA precalculated in ID stage
717 
// for balancing ID and EX stages.
718 
//
719 
// Valid range: 2,3,...,30,31
720 
`define OR1200_LSUEA_PRECALC            2
721 
 
722 10 unneback 
// FETCHOPs
723 
`define OR1200_FETCHOP_WIDTH            1
724 
`define OR1200_FETCHOP_NOP              1'b0
725 
`define OR1200_FETCHOP_LW               1'b1
726 
 
727 
//
728 
// Register File Write-Back OPs
729 
//
730 
// Bit 0: register file write enable
731 
// Bits 2-1: write-back mux selects
732 
`define OR1200_RFWBOP_WIDTH             3
733 
`define OR1200_RFWBOP_NOP               3'b000
734 
`define OR1200_RFWBOP_ALU               3'b001
735 
`define OR1200_RFWBOP_LSU               3'b011
736 
`define OR1200_RFWBOP_SPRS              3'b101
737 
`define OR1200_RFWBOP_LR                3'b111
738 
 
739 
// Compare instructions
740 
`define OR1200_COP_SFEQ       3'b000
741 
`define OR1200_COP_SFNE       3'b001
742 
`define OR1200_COP_SFGT       3'b010
743 
`define OR1200_COP_SFGE       3'b011
744 
`define OR1200_COP_SFLT       3'b100
745 
`define OR1200_COP_SFLE       3'b101
746 
`define OR1200_COP_X          3'b111
747 
`define OR1200_SIGNED_COMPARE 'd3
748 
`define OR1200_COMPOP_WIDTH     4
749 
 
750 
//
751 
// TAGs for instruction bus
752 
//
753 
`define OR1200_ITAG_IDLE        4'h0    // idle bus
754 
`define OR1200_ITAG_NI          4'h1    // normal insn
755 
`define OR1200_ITAG_BE          4'hb    // Bus error exception
756 
`define OR1200_ITAG_PE          4'hc    // Page fault exception
757 
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
758 
 
759 
//
760 
// TAGs for data bus
761 
//
762 
`define OR1200_DTAG_IDLE        4'h0    // idle bus
763 
`define OR1200_DTAG_ND          4'h1    // normal data
764 
`define OR1200_DTAG_AE          4'ha    // Alignment exception
765 
`define OR1200_DTAG_BE          4'hb    // Bus error exception
766 
`define OR1200_DTAG_PE          4'hc    // Page fault exception
767 
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
768 
 
769 
 
770 
//////////////////////////////////////////////
771 
//
772 
// ORBIS32 ISA specifics
773 
//
774 
 
775 
// SHROT_OP position in machine word
776 
`define OR1200_SHROTOP_POS              7:6
777 
 
778 
// ALU instructions multicycle field in machine word
779 
`define OR1200_ALUMCYC_POS              9:8
780 
 
781 
//
782 
// Instruction opcode groups (basic)
783 
//
784 
`define OR1200_OR32_J                 6'b000000
785 
`define OR1200_OR32_JAL               6'b000001
786 
`define OR1200_OR32_BNF               6'b000011
787 
`define OR1200_OR32_BF                6'b000100
788 
`define OR1200_OR32_NOP               6'b000101
789 
`define OR1200_OR32_MOVHI             6'b000110
790 
`define OR1200_OR32_XSYNC             6'b001000
791 
`define OR1200_OR32_RFE               6'b001001
792 
/* */
793 
`define OR1200_OR32_JR                6'b010001
794 
`define OR1200_OR32_JALR              6'b010010
795 
`define OR1200_OR32_MACI              6'b010011
796 
/* */
797 
`define OR1200_OR32_LWZ               6'b100001
798 
`define OR1200_OR32_LBZ               6'b100011
799 
`define OR1200_OR32_LBS               6'b100100
800 
`define OR1200_OR32_LHZ               6'b100101
801 
`define OR1200_OR32_LHS               6'b100110
802 
`define OR1200_OR32_ADDI              6'b100111
803 
`define OR1200_OR32_ADDIC             6'b101000
804 
`define OR1200_OR32_ANDI              6'b101001
805 
`define OR1200_OR32_ORI               6'b101010
806 
`define OR1200_OR32_XORI              6'b101011
807 
`define OR1200_OR32_MULI              6'b101100
808 
`define OR1200_OR32_MFSPR             6'b101101
809 
`define OR1200_OR32_SH_ROTI           6'b101110
810 
`define OR1200_OR32_SFXXI             6'b101111
811 
/* */
812 
`define OR1200_OR32_MTSPR             6'b110000
813 
`define OR1200_OR32_MACMSB            6'b110001
814 
/* */
815 
`define OR1200_OR32_SW                6'b110101
816 
`define OR1200_OR32_SB                6'b110110
817 
`define OR1200_OR32_SH                6'b110111
818 
`define OR1200_OR32_ALU               6'b111000
819 
`define OR1200_OR32_SFXX              6'b111001
820 
//`define OR1200_OR32_CUST5             6'b111100
821 
 
822 
 
823 
/////////////////////////////////////////////////////
824 
//
825 
// Exceptions
826 
//
827 
 
828 
//
829 
// Exception vectors per OR1K architecture:
830 
// 0xPPPPP100 - reset
831 
// 0xPPPPP200 - bus error
832 
// ... etc
833 
// where P represents exception prefix.
834 
//
835 
// Exception vectors can be customized as per
836 
// the following formula:
837 
// 0xPPPPPNVV - exception N
838 
//
839 
// P represents exception prefix
840 
// N represents exception N
841 
// VV represents length of the individual vector space,
842 
//   usually it is 8 bits wide and starts with all bits zero
843 
//
844 
 
845 
//
846 
// PPPPP and VV parts
847 
//
848 
// Sum of these two defines needs to be 28
849 
//
850 141 marcus.erl 
`define OR1200_EXCEPT_EPH0_P    20'h00000
851 
`define OR1200_EXCEPT_EPH1_P    20'hF0000
852 
`define OR1200_EXCEPT_V             8'h00
853 10 unneback 
 
854 
//
855 
// N part width
856 
//
857 
`define OR1200_EXCEPT_WIDTH 4
858 
 
859 
//
860 
// Definition of exception vectors
861 
//
862 
// To avoid implementation of a certain exception,
863 
// simply comment out corresponding line
864 
//
865 
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
866 
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
867 
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
868 
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
869 
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
870 
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
871 
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
872 
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
873 
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
874 
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
875 
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
876 
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
877 
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
878 
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
879 
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
880 
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
881 
 
882 
 
883 
/////////////////////////////////////////////////////
884 
//
885 
// SPR groups
886 
//
887 
 
888 
// Bits that define the group
889 
`define OR1200_SPR_GROUP_BITS   15:11
890 
 
891 
// Width of the group bits
892 
`define OR1200_SPR_GROUP_WIDTH  5
893 
 
894 
// Bits that define offset inside the group
895 
`define OR1200_SPR_OFS_BITS 10:0
896 
 
897 
// List of groups
898 
`define OR1200_SPR_GROUP_SYS    5'd00
899 
`define OR1200_SPR_GROUP_DMMU   5'd01
900 
`define OR1200_SPR_GROUP_IMMU   5'd02
901 
`define OR1200_SPR_GROUP_DC     5'd03
902 
`define OR1200_SPR_GROUP_IC     5'd04
903 
`define OR1200_SPR_GROUP_MAC    5'd05
904 
`define OR1200_SPR_GROUP_DU     5'd06
905 
`define OR1200_SPR_GROUP_PM     5'd08
906 
`define OR1200_SPR_GROUP_PIC    5'd09
907 
`define OR1200_SPR_GROUP_TT     5'd10
908 
 
909 
 
910 
/////////////////////////////////////////////////////
911 
//
912 
// System group
913 
//
914 
 
915 
//
916 
// System registers
917 
//
918 
`define OR1200_SPR_CFGR         7'd0
919 
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
920 
`define OR1200_SPR_NPC          11'd16
921 
`define OR1200_SPR_SR           11'd17
922 
`define OR1200_SPR_PPC          11'd18
923 
`define OR1200_SPR_EPCR         11'd32
924 
`define OR1200_SPR_EEAR         11'd48
925 
`define OR1200_SPR_ESR          11'd64
926 
 
927 
//
928 
// SR bits
929 
//
930 141 marcus.erl 
`define OR1200_SR_WIDTH 17
931 10 unneback 
`define OR1200_SR_SM   0
932 
`define OR1200_SR_TEE  1
933 
`define OR1200_SR_IEE  2
934 
`define OR1200_SR_DCE  3
935 
`define OR1200_SR_ICE  4
936 
`define OR1200_SR_DME  5
937 
`define OR1200_SR_IME  6
938 
`define OR1200_SR_LEE  7
939 
`define OR1200_SR_CE   8
940 
`define OR1200_SR_F    9
941 
`define OR1200_SR_CY   10       // Unused
942 
`define OR1200_SR_OV   11       // Unused
943 
`define OR1200_SR_OVE  12       // Unused
944 
`define OR1200_SR_DSX  13       // Unused
945 
`define OR1200_SR_EPH  14
946 
`define OR1200_SR_FO   15
947 141 marcus.erl 
`define OR1200_SR_TED  16
948 10 unneback 
`define OR1200_SR_CID  31:28    // Unimplemented
949 
 
950 
//
951 
// Bits that define offset inside the group
952 
//
953 
`define OR1200_SPROFS_BITS 10:0
954 
 
955 
//
956 
// Default Exception Prefix
957 
//
958 
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
959 
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
960 
//
961 
`define OR1200_SR_EPH_DEF       1'b0
962 
 
963 
/////////////////////////////////////////////////////
964 
//
965 
// Power Management (PM)
966 
//
967 
 
968 
// Define it if you want PM implemented
969 141 marcus.erl 
//`define OR1200_PM_IMPLEMENTED
970 10 unneback 
 
971 
// Bit positions inside PMR (don't change)
972 
`define OR1200_PM_PMR_SDF 3:0
973 
`define OR1200_PM_PMR_DME 4
974 
`define OR1200_PM_PMR_SME 5
975 
`define OR1200_PM_PMR_DCGE 6
976 
`define OR1200_PM_PMR_UNUSED 31:7
977 
 
978 
// PMR offset inside PM group of registers
979 
`define OR1200_PM_OFS_PMR 11'b0
980 
 
981 
// PM group
982 
`define OR1200_SPRGRP_PM 5'd8
983 
 
984 
// Define if PMR can be read/written at any address inside PM group
985 
`define OR1200_PM_PARTIAL_DECODING
986 
 
987 
// Define if reading PMR is allowed
988 
`define OR1200_PM_READREGS
989 
 
990 
// Define if unused PMR bits should be zero
991 
`define OR1200_PM_UNUSED_ZERO
992 
 
993 
 
994 
/////////////////////////////////////////////////////
995 
//
996 
// Debug Unit (DU)
997 
//
998 
 
999 
// Define it if you want DU implemented
1000 
`define OR1200_DU_IMPLEMENTED
1001 
 
1002 
//
1003 
// Define if you want HW Breakpoints
1004 
// (if HW breakpoints are not implemented
1005 
// only default software trapping is
1006 
// possible with l.trap insn - this is
1007 
// however already enough for use
1008 
// with or32 gdb)
1009 
//
1010 
//`define OR1200_DU_HWBKPTS
1011 
 
1012 
// Number of DVR/DCR pairs if HW breakpoints enabled
1013 141 marcus.erl 
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number !
1014 
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS
1015 10 unneback 
`define OR1200_DU_DVRDCR_PAIRS 8
1016 
 
1017 
// Define if you want trace buffer
1018 141 marcus.erl 
//      (for now only available for Xilinx Virtex FPGAs)
1019 10 unneback 
//`define OR1200_DU_TB_IMPLEMENTED
1020 
 
1021 141 marcus.erl 
 
1022 10 unneback 
//
1023 
// Address offsets of DU registers inside DU group
1024 
//
1025 
// To not implement a register, doq not define its address
1026 
//
1027 
`ifdef OR1200_DU_HWBKPTS
1028 
`define OR1200_DU_DVR0          11'd0
1029 
`define OR1200_DU_DVR1          11'd1
1030 
`define OR1200_DU_DVR2          11'd2
1031 
`define OR1200_DU_DVR3          11'd3
1032 
`define OR1200_DU_DVR4          11'd4
1033 
`define OR1200_DU_DVR5          11'd5
1034 
`define OR1200_DU_DVR6          11'd6
1035 
`define OR1200_DU_DVR7          11'd7
1036 
`define OR1200_DU_DCR0          11'd8
1037 
`define OR1200_DU_DCR1          11'd9
1038 
`define OR1200_DU_DCR2          11'd10
1039 
`define OR1200_DU_DCR3          11'd11
1040 
`define OR1200_DU_DCR4          11'd12
1041 
`define OR1200_DU_DCR5          11'd13
1042 
`define OR1200_DU_DCR6          11'd14
1043 
`define OR1200_DU_DCR7          11'd15
1044 
`endif
1045 
`define OR1200_DU_DMR1          11'd16
1046 
`ifdef OR1200_DU_HWBKPTS
1047 
`define OR1200_DU_DMR2          11'd17
1048 
`define OR1200_DU_DWCR0         11'd18
1049 
`define OR1200_DU_DWCR1         11'd19
1050 
`endif
1051 
`define OR1200_DU_DSR           11'd20
1052 
`define OR1200_DU_DRR           11'd21
1053 
`ifdef OR1200_DU_TB_IMPLEMENTED
1054 
`define OR1200_DU_TBADR         11'h0ff
1055 
`define OR1200_DU_TBIA          11'h1xx
1056 
`define OR1200_DU_TBIM          11'h2xx
1057 
`define OR1200_DU_TBAR          11'h3xx
1058 
`define OR1200_DU_TBTS          11'h4xx
1059 
`endif
1060 
 
1061 
// Position of offset bits inside SPR address
1062 
`define OR1200_DUOFS_BITS       10:0
1063 
 
1064 
// DCR bits
1065 
`define OR1200_DU_DCR_DP        0
1066 
`define OR1200_DU_DCR_CC        3:1
1067 
`define OR1200_DU_DCR_SC        4
1068 
`define OR1200_DU_DCR_CT        7:5
1069 
 
1070 
// DMR1 bits
1071 
`define OR1200_DU_DMR1_CW0      1:0
1072 
`define OR1200_DU_DMR1_CW1      3:2
1073 
`define OR1200_DU_DMR1_CW2      5:4
1074 
`define OR1200_DU_DMR1_CW3      7:6
1075 
`define OR1200_DU_DMR1_CW4      9:8
1076 
`define OR1200_DU_DMR1_CW5      11:10
1077 
`define OR1200_DU_DMR1_CW6      13:12
1078 
`define OR1200_DU_DMR1_CW7      15:14
1079 
`define OR1200_DU_DMR1_CW8      17:16
1080 
`define OR1200_DU_DMR1_CW9      19:18
1081 
`define OR1200_DU_DMR1_CW10     21:20
1082 
`define OR1200_DU_DMR1_ST       22
1083 
`define OR1200_DU_DMR1_BT       23
1084 
`define OR1200_DU_DMR1_DXFW     24
1085 
`define OR1200_DU_DMR1_ETE      25
1086 
 
1087 
// DMR2 bits
1088 
`define OR1200_DU_DMR2_WCE0     0
1089 
`define OR1200_DU_DMR2_WCE1     1
1090 
`define OR1200_DU_DMR2_AWTC     12:2
1091 
`define OR1200_DU_DMR2_WGB      23:13
1092 
 
1093 
// DWCR bits
1094 
`define OR1200_DU_DWCR_COUNT    15:0
1095 
`define OR1200_DU_DWCR_MATCH    31:16
1096 
 
1097 
// DSR bits
1098 
`define OR1200_DU_DSR_WIDTH     14
1099 
`define OR1200_DU_DSR_RSTE      0
1100 
`define OR1200_DU_DSR_BUSEE     1
1101 
`define OR1200_DU_DSR_DPFE      2
1102 
`define OR1200_DU_DSR_IPFE      3
1103 
`define OR1200_DU_DSR_TTE       4
1104 
`define OR1200_DU_DSR_AE        5
1105 
`define OR1200_DU_DSR_IIE       6
1106 
`define OR1200_DU_DSR_IE        7
1107 
`define OR1200_DU_DSR_DME       8
1108 
`define OR1200_DU_DSR_IME       9
1109 
`define OR1200_DU_DSR_RE        10
1110 
`define OR1200_DU_DSR_SCE       11
1111 
`define OR1200_DU_DSR_BE        12
1112 
`define OR1200_DU_DSR_TE        13
1113 
 
1114 
// DRR bits
1115 
`define OR1200_DU_DRR_RSTE      0
1116 
`define OR1200_DU_DRR_BUSEE     1
1117 
`define OR1200_DU_DRR_DPFE      2
1118 
`define OR1200_DU_DRR_IPFE      3
1119 
`define OR1200_DU_DRR_TTE       4
1120 
`define OR1200_DU_DRR_AE        5
1121 
`define OR1200_DU_DRR_IIE       6
1122 
`define OR1200_DU_DRR_IE        7
1123 
`define OR1200_DU_DRR_DME       8
1124 
`define OR1200_DU_DRR_IME       9
1125 
`define OR1200_DU_DRR_RE        10
1126 
`define OR1200_DU_DRR_SCE       11
1127 
`define OR1200_DU_DRR_BE        12
1128 
`define OR1200_DU_DRR_TE        13
1129 
 
1130 
// Define if reading DU regs is allowed
1131 
`define OR1200_DU_READREGS
1132 
 
1133 
// Define if unused DU registers bits should be zero
1134 
`define OR1200_DU_UNUSED_ZERO
1135 
 
1136 
// Define if IF/LSU status is not needed by devel i/f
1137 
`define OR1200_DU_STATUS_UNIMPLEMENTED
1138 
 
1139 
/////////////////////////////////////////////////////
1140 
//
1141 
// Programmable Interrupt Controller (PIC)
1142 
//
1143 
 
1144 
// Define it if you want PIC implemented
1145 
`define OR1200_PIC_IMPLEMENTED
1146 
 
1147 
// Define number of interrupt inputs (2-31)
1148 141 marcus.erl 
`define OR1200_PIC_INTS 31
1149 10 unneback 
 
1150 
// Address offsets of PIC registers inside PIC group
1151 
`define OR1200_PIC_OFS_PICMR 2'd0
1152 
`define OR1200_PIC_OFS_PICSR 2'd2
1153 
 
1154 
// Position of offset bits inside SPR address
1155 
`define OR1200_PICOFS_BITS 1:0
1156 
 
1157 
// Define if you want these PIC registers to be implemented
1158 
`define OR1200_PIC_PICMR
1159 
`define OR1200_PIC_PICSR
1160 
 
1161 
// Define if reading PIC registers is allowed
1162 
`define OR1200_PIC_READREGS
1163 
 
1164 
// Define if unused PIC register bits should be zero
1165 
`define OR1200_PIC_UNUSED_ZERO
1166 
 
1167 
 
1168 
/////////////////////////////////////////////////////
1169 
//
1170 
// Tick Timer (TT)
1171 
//
1172 
 
1173 
// Define it if you want TT implemented
1174 
`define OR1200_TT_IMPLEMENTED
1175 
 
1176 
// Address offsets of TT registers inside TT group
1177 
`define OR1200_TT_OFS_TTMR 1'd0
1178 
`define OR1200_TT_OFS_TTCR 1'd1
1179 
 
1180 
// Position of offset bits inside SPR group
1181 
`define OR1200_TTOFS_BITS 0
1182 
 
1183 
// Define if you want these TT registers to be implemented
1184 
`define OR1200_TT_TTMR
1185 
`define OR1200_TT_TTCR
1186 
 
1187 
// TTMR bits
1188 
`define OR1200_TT_TTMR_TP 27:0
1189 
`define OR1200_TT_TTMR_IP 28
1190 
`define OR1200_TT_TTMR_IE 29
1191 
`define OR1200_TT_TTMR_M 31:30
1192 
 
1193 
// Define if reading TT registers is allowed
1194 
`define OR1200_TT_READREGS
1195 
 
1196 
 
1197 
//////////////////////////////////////////////
1198 
//
1199 
// MAC
1200 
//
1201 
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1202 
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1203 
 
1204 
//
1205 
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1206 
//
1207 
// According to architecture manual there is no shift, so default value is 0.
1208 
//
1209 
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
1210 
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
1211 
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
1212 
// dest_GPR = {MACHI,MACLO}[59:28]
1213 
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1214 
 
1215 
 
1216 
//////////////////////////////////////////////
1217 
//
1218 
// Data MMU (DMMU)
1219 
//
1220 
 
1221 
//
1222 
// Address that selects between TLB TR and MR
1223 
//
1224 
`define OR1200_DTLB_TM_ADDR     7
1225 
 
1226 
//
1227 
// DTLBMR fields
1228 
//
1229 
`define OR1200_DTLBMR_V_BITS    0
1230 
`define OR1200_DTLBMR_CID_BITS  4:1
1231 
`define OR1200_DTLBMR_RES_BITS  11:5
1232 
`define OR1200_DTLBMR_VPN_BITS  31:13
1233 
 
1234 
//
1235 
// DTLBTR fields
1236 
//
1237 
`define OR1200_DTLBTR_CC_BITS   0
1238 
`define OR1200_DTLBTR_CI_BITS   1
1239 
`define OR1200_DTLBTR_WBC_BITS  2
1240 
`define OR1200_DTLBTR_WOM_BITS  3
1241 
`define OR1200_DTLBTR_A_BITS    4
1242 
`define OR1200_DTLBTR_D_BITS    5
1243 
`define OR1200_DTLBTR_URE_BITS  6
1244 
`define OR1200_DTLBTR_UWE_BITS  7
1245 
`define OR1200_DTLBTR_SRE_BITS  8
1246 
`define OR1200_DTLBTR_SWE_BITS  9
1247 
`define OR1200_DTLBTR_RES_BITS  11:10
1248 
`define OR1200_DTLBTR_PPN_BITS  31:13
1249 
 
1250 
//
1251 
// DTLB configuration
1252 
//
1253 
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1254 
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1255 
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1256 
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1257 
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1258 
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1259 
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1260 
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1261 
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1262 
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1263 
 
1264 
//
1265 
// Cache inhibit while DMMU is not enabled/implemented
1266 
//
1267 
// cache inhibited 0GB-4GB              1'b1
1268 
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1269 
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1270 
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1271 
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1272 
// cached 0GB-4GB                       1'b0
1273 
//
1274 
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1275 
 
1276 
 
1277 
//////////////////////////////////////////////
1278 
//
1279 
// Insn MMU (IMMU)
1280 
//
1281 
 
1282 
//
1283 
// Address that selects between TLB TR and MR
1284 
//
1285 
`define OR1200_ITLB_TM_ADDR     7
1286 
 
1287 
//
1288 
// ITLBMR fields
1289 
//
1290 
`define OR1200_ITLBMR_V_BITS    0
1291 
`define OR1200_ITLBMR_CID_BITS  4:1
1292 
`define OR1200_ITLBMR_RES_BITS  11:5
1293 
`define OR1200_ITLBMR_VPN_BITS  31:13
1294 
 
1295 
//
1296 
// ITLBTR fields
1297 
//
1298 
`define OR1200_ITLBTR_CC_BITS   0
1299 
`define OR1200_ITLBTR_CI_BITS   1
1300 
`define OR1200_ITLBTR_WBC_BITS  2
1301 
`define OR1200_ITLBTR_WOM_BITS  3
1302 
`define OR1200_ITLBTR_A_BITS    4
1303 
`define OR1200_ITLBTR_D_BITS    5
1304 
`define OR1200_ITLBTR_SXE_BITS  6
1305 
`define OR1200_ITLBTR_UXE_BITS  7
1306 
`define OR1200_ITLBTR_RES_BITS  11:8
1307 
`define OR1200_ITLBTR_PPN_BITS  31:13
1308 
 
1309 
//
1310 
// ITLB configuration
1311 
//
1312 
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1313 
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1314 
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1315 
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1316 
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1317 
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1318 
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1319 
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1320 
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1321 
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1322 
 
1323 
//
1324 
// Cache inhibit while IMMU is not enabled/implemented
1325 
// Note: all combinations that use icpu_adr_i cause async loop
1326 
//
1327 
// cache inhibited 0GB-4GB              1'b1
1328 
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1329 
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1330 
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1331 
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1332 
// cached 0GB-4GB                       1'b0
1333 
//
1334 
`define OR1200_IMMU_CI                  1'b0
1335 
 
1336 
 
1337 
/////////////////////////////////////////////////
1338 
//
1339 
// Insn cache (IC)
1340 
//
1341 
 
1342 
// 3 for 8 bytes, 4 for 16 bytes etc
1343 
`define OR1200_ICLS             4
1344 
 
1345 
//
1346 
// IC configurations
1347 
//
1348 
`ifdef OR1200_IC_1W_512B
1349 
`define OR1200_ICSIZE   9     // 512
1350 
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1351 
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1352 
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1353 
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1354 
`define OR1200_ICTAG_W  24
1355 
`endif
1356 
`ifdef OR1200_IC_1W_4KB
1357 
`define OR1200_ICSIZE                   12                      // 4096
1358 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1359 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1360 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1361 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1362 
`define OR1200_ICTAG_W                  21
1363 
`endif
1364 
`ifdef OR1200_IC_1W_8KB
1365 
`define OR1200_ICSIZE                   13                      // 8192
1366 
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1367 
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1368 
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1369 
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1370 
`define OR1200_ICTAG_W                  20
1371 
`endif
1372 
 
1373 
 
1374 
/////////////////////////////////////////////////
1375 
//
1376 
// Data cache (DC)
1377 
//
1378 
 
1379 
// 3 for 8 bytes, 4 for 16 bytes etc
1380 
`define OR1200_DCLS             4
1381 
 
1382 
// Define to perform store refill (potential performance penalty)
1383 
// `define OR1200_DC_STORE_REFILL
1384 
 
1385 
//
1386 
// DC configurations
1387 
//
1388 
`ifdef OR1200_DC_1W_4KB
1389 
`define OR1200_DCSIZE                   12                      // 4096
1390 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1391 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1392 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1393 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1394 
`define OR1200_DCTAG_W                  21
1395 
`endif
1396 
`ifdef OR1200_DC_1W_8KB
1397 
`define OR1200_DCSIZE                   13                      // 8192
1398 
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1399 
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1400 
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1401 
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1402 
`define OR1200_DCTAG_W                  20
1403 
`endif
1404 
 
1405 
/////////////////////////////////////////////////
1406 
//
1407 
// Store buffer (SB)
1408 
//
1409 
 
1410 
//
1411 
// Store buffer
1412 
//
1413 
// It will improve performance by "caching" CPU stores
1414 
// using store buffer. This is most important for function
1415 
// prologues because DC can only work in write though mode
1416 
// and all stores would have to complete external WB writes
1417 
// to memory.
1418 
// Store buffer is between DC and data BIU.
1419 
// All stores will be stored into store buffer and immediately
1420 
// completed by the CPU, even though actual external writes
1421 
// will be performed later. As a consequence store buffer masks
1422 
// all data bus errors related to stores (data bus errors
1423 
// related to loads are delivered normally).
1424 
// All pending CPU loads will wait until store buffer is empty to
1425 
// ensure strict memory model. Right now this is necessary because
1426 
// we don't make destinction between cached and cache inhibited
1427 
// address space, so we simply empty store buffer until loads
1428 
// can begin.
1429 
//
1430 
// It makes design a bit bigger, depending what is the number of
1431 
// entries in SB FIFO. Number of entries can be changed further
1432 
// down.
1433 
//
1434 
//`define OR1200_SB_IMPLEMENTED
1435 
 
1436 
//
1437 
// Number of store buffer entries
1438 
//
1439 
// Verified number of entries are 4 and 8 entries
1440 
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1441 
// always match 2**OR1200_SB_LOG.
1442 
// To disable store buffer, undefine
1443 
// OR1200_SB_IMPLEMENTED.
1444 
//
1445 
`define OR1200_SB_LOG           2       // 2 or 3
1446 
`define OR1200_SB_ENTRIES       4       // 4 or 8
1447 
 
1448 
 
1449 
/////////////////////////////////////////////////
1450 
//
1451 
// Quick Embedded Memory (QMEM)
1452 
//
1453 
 
1454 
//
1455 
// Quick Embedded Memory
1456 
//
1457 
// Instantiation of dedicated insn/data memory (RAM or ROM).
1458 
// Insn fetch has effective throughput 1insn / clock cycle.
1459 
// Data load takes two clock cycles / access, data store
1460 
// takes 1 clock cycle / access (if there is no insn fetch)).
1461 
// Memory instantiation is shared between insn and data,
1462 
// meaning if insn fetch are performed, data load/store
1463 
// performance will be lower.
1464 
//
1465 
// Main reason for QMEM is to put some time critical functions
1466 
// into this memory and to have predictable and fast access
1467 
// to these functions. (soft fpu, context switch, exception
1468 
// handlers, stack, etc)
1469 
//
1470 
// It makes design a bit bigger and slower. QMEM sits behind
1471 
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1472 
// used with QMEM and QMEM is seen by the CPU just like any other
1473 
// memory in the system). IC/DC are sitting behind QMEM so the
1474 
// whole design timing might be worse with QMEM implemented.
1475 
//
1476 141 marcus.erl 
//`define OR1200_QMEM_IMPLEMENTED
1477 10 unneback 
 
1478 
//
1479 
// Base address and mask of QMEM
1480 
//
1481 
// Base address defines first address of QMEM. Mask defines
1482 
// QMEM range in address space. Actual size of QMEM is however
1483 
// determined with instantiated RAM/ROM. However bigger
1484 
// mask will reserve more address space for QMEM, but also
1485 
// make design faster, while more tight mask will take
1486 
// less address space but also make design slower. If
1487 
// instantiated RAM/ROM is smaller than space reserved with
1488 
// the mask, instatiated RAM/ROM will also be shadowed
1489 
// at higher addresses in reserved space.
1490 
//
1491 
`define OR1200_QMEM_IADDR       32'h0080_0000
1492 141 marcus.erl 
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1493 
`define OR1200_QMEM_DADDR       32'h0080_0000
1494 
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1495 10 unneback 
 
1496 
//
1497 
// QMEM interface byte-select capability
1498 
//
1499 
// To enable qmem_sel* ports, define this macro.
1500 
//
1501 
//`define OR1200_QMEM_BSEL
1502 
 
1503 
//
1504 
// QMEM interface acknowledge
1505 
//
1506 
// To enable qmem_ack port, define this macro.
1507 
//
1508 
//`define OR1200_QMEM_ACK
1509 
 
1510 
/////////////////////////////////////////////////////
1511 
//
1512 
// VR, UPR and Configuration Registers
1513 
//
1514 
//
1515 
// VR, UPR and configuration registers are optional. If
1516 
// implemented, operating system can automatically figure
1517 
// out how to use the processor because it knows
1518 
// what units are available in the processor and how they
1519 
// are configured.
1520 
//
1521 
// This section must be last in or1200_defines.v file so
1522 
// that all units are already configured and thus
1523 
// configuration registers are properly set.
1524 
//
1525 
 
1526 
// Define if you want configuration registers implemented
1527 
`define OR1200_CFGR_IMPLEMENTED
1528 
 
1529 
// Define if you want full address decode inside SYS group
1530 
`define OR1200_SYS_FULL_DECODE
1531 
 
1532 
// Offsets of VR, UPR and CFGR registers
1533 
`define OR1200_SPRGRP_SYS_VR            4'h0
1534 
`define OR1200_SPRGRP_SYS_UPR           4'h1
1535 
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1536 
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1537 
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1538 
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1539 
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1540 
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1541 
 
1542 
// VR fields
1543 
`define OR1200_VR_REV_BITS              5:0
1544 
`define OR1200_VR_RES1_BITS             15:6
1545 
`define OR1200_VR_CFG_BITS              23:16
1546 
`define OR1200_VR_VER_BITS              31:24
1547 
 
1548 
// VR values
1549 
`define OR1200_VR_REV                   6'h01
1550 
`define OR1200_VR_RES1                  10'h000
1551 
`define OR1200_VR_CFG                   8'h00
1552 
`define OR1200_VR_VER                   8'h12
1553 
 
1554 
// UPR fields
1555 
`define OR1200_UPR_UP_BITS              0
1556 
`define OR1200_UPR_DCP_BITS             1
1557 
`define OR1200_UPR_ICP_BITS             2
1558 
`define OR1200_UPR_DMP_BITS             3
1559 
`define OR1200_UPR_IMP_BITS             4
1560 
`define OR1200_UPR_MP_BITS              5
1561 
`define OR1200_UPR_DUP_BITS             6
1562 
`define OR1200_UPR_PCUP_BITS            7
1563 
`define OR1200_UPR_PMP_BITS             8
1564 
`define OR1200_UPR_PICP_BITS            9
1565 
`define OR1200_UPR_TTP_BITS             10
1566 
`define OR1200_UPR_RES1_BITS            23:11
1567 
`define OR1200_UPR_CUP_BITS             31:24
1568 
 
1569 
// UPR values
1570 
`define OR1200_UPR_UP                   1'b1
1571 
`ifdef OR1200_NO_DC
1572 
`define OR1200_UPR_DCP                  1'b0
1573 
`else
1574 
`define OR1200_UPR_DCP                  1'b1
1575 
`endif
1576 
`ifdef OR1200_NO_IC
1577 
`define OR1200_UPR_ICP                  1'b0
1578 
`else
1579 
`define OR1200_UPR_ICP                  1'b1
1580 
`endif
1581 
`ifdef OR1200_NO_DMMU
1582 
`define OR1200_UPR_DMP                  1'b0
1583 
`else
1584 
`define OR1200_UPR_DMP                  1'b1
1585 
`endif
1586 
`ifdef OR1200_NO_IMMU
1587 
`define OR1200_UPR_IMP                  1'b0
1588 
`else
1589 
`define OR1200_UPR_IMP                  1'b1
1590 
`endif
1591 
`define OR1200_UPR_MP                   1'b1    // MAC always present
1592 
`ifdef OR1200_DU_IMPLEMENTED
1593 
`define OR1200_UPR_DUP                  1'b1
1594 
`else
1595 
`define OR1200_UPR_DUP                  1'b0
1596 
`endif
1597 
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1598 141 marcus.erl 
`ifdef OR1200_PM_IMPLEMENTED
1599 10 unneback 
`define OR1200_UPR_PMP                  1'b1
1600 
`else
1601 
`define OR1200_UPR_PMP                  1'b0
1602 
`endif
1603 141 marcus.erl 
`ifdef OR1200_PIC_IMPLEMENTED
1604 10 unneback 
`define OR1200_UPR_PICP                 1'b1
1605 
`else
1606 
`define OR1200_UPR_PICP                 1'b0
1607 
`endif
1608 141 marcus.erl 
`ifdef OR1200_TT_IMPLEMENTED
1609 10 unneback 
`define OR1200_UPR_TTP                  1'b1
1610 
`else
1611 
`define OR1200_UPR_TTP                  1'b0
1612 
`endif
1613 
`define OR1200_UPR_RES1                 13'h0000
1614 
`define OR1200_UPR_CUP                  8'h00
1615 
 
1616 
// CPUCFGR fields
1617 
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1618 141 marcus.erl 
`define OR1200_CPUCFGR_HGF_BITS     4
1619 10 unneback 
`define OR1200_CPUCFGR_OB32S_BITS       5
1620 
`define OR1200_CPUCFGR_OB64S_BITS       6
1621 
`define OR1200_CPUCFGR_OF32S_BITS       7
1622 
`define OR1200_CPUCFGR_OF64S_BITS       8
1623 
`define OR1200_CPUCFGR_OV64S_BITS       9
1624 
`define OR1200_CPUCFGR_RES1_BITS        31:10
1625 
 
1626 
// CPUCFGR values
1627 141 marcus.erl 
`define OR1200_CPUCFGR_NSGF                 4'h0
1628 
`ifdef OR1200_RFRAM_16REG
1629 
    `define OR1200_CPUCFGR_HGF                  1'b1
1630 
`else
1631 
    `define OR1200_CPUCFGR_HGF                  1'b0
1632 
`endif
1633 10 unneback 
`define OR1200_CPUCFGR_OB32S            1'b1
1634 
`define OR1200_CPUCFGR_OB64S            1'b0
1635 
`define OR1200_CPUCFGR_OF32S            1'b0
1636 
`define OR1200_CPUCFGR_OF64S            1'b0
1637 
`define OR1200_CPUCFGR_OV64S            1'b0
1638 
`define OR1200_CPUCFGR_RES1             22'h000000
1639 
 
1640 
// DMMUCFGR fields
1641 
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1642 
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1643 
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1644 
`define OR1200_DMMUCFGR_CRI_BITS        8
1645 
`define OR1200_DMMUCFGR_PRI_BITS        9
1646 
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1647 
`define OR1200_DMMUCFGR_HTR_BITS        11
1648 
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1649 
 
1650 
// DMMUCFGR values
1651 
`ifdef OR1200_NO_DMMU
1652 
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1653 
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1654 
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1655 
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1656 
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1657 
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1658 
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1659 
`define OR1200_DMMUCFGR_RES1            20'h00000
1660 
`else
1661 
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1662 
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1663 
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1664 
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1665 
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1666 
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1667 
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1668 
`define OR1200_DMMUCFGR_RES1            20'h00000
1669 
`endif
1670 
 
1671 
// IMMUCFGR fields
1672 
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1673 
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1674 
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1675 
`define OR1200_IMMUCFGR_CRI_BITS        8
1676 
`define OR1200_IMMUCFGR_PRI_BITS        9
1677 
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1678 
`define OR1200_IMMUCFGR_HTR_BITS        11
1679 
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1680 
 
1681 
// IMMUCFGR values
1682 
`ifdef OR1200_NO_IMMU
1683 
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1684 
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1685 
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1686 
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1687 
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1688 
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1689 
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1690 
`define OR1200_IMMUCFGR_RES1            20'h00000
1691 
`else
1692 
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1693 
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1694 
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1695 
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1696 
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1697 
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1698 
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1699 
`define OR1200_IMMUCFGR_RES1            20'h00000
1700 
`endif
1701 
 
1702 
// DCCFGR fields
1703 
`define OR1200_DCCFGR_NCW_BITS          2:0
1704 
`define OR1200_DCCFGR_NCS_BITS          6:3
1705 
`define OR1200_DCCFGR_CBS_BITS          7
1706 
`define OR1200_DCCFGR_CWS_BITS          8
1707 
`define OR1200_DCCFGR_CCRI_BITS         9
1708 
`define OR1200_DCCFGR_CBIRI_BITS        10
1709 
`define OR1200_DCCFGR_CBPRI_BITS        11
1710 
`define OR1200_DCCFGR_CBLRI_BITS        12
1711 
`define OR1200_DCCFGR_CBFRI_BITS        13
1712 
`define OR1200_DCCFGR_CBWBRI_BITS       14
1713 
`define OR1200_DCCFGR_RES1_BITS 31:15
1714 
 
1715 
// DCCFGR values
1716 
`ifdef OR1200_NO_DC
1717 
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1718 
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1719 
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1720 
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1721 141 marcus.erl 
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1722 
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1723 10 unneback 
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1724 
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1725 141 marcus.erl 
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1726 10 unneback 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1727 
`define OR1200_DCCFGR_RES1              17'h00000
1728 
`else
1729 
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1730 
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1731 
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1732 
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1733 
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1734 
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1735 
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1736 
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1737 
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1738 
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1739 
`define OR1200_DCCFGR_RES1              17'h00000
1740 
`endif
1741 
 
1742 
// ICCFGR fields
1743 
`define OR1200_ICCFGR_NCW_BITS          2:0
1744 
`define OR1200_ICCFGR_NCS_BITS          6:3
1745 
`define OR1200_ICCFGR_CBS_BITS          7
1746 
`define OR1200_ICCFGR_CWS_BITS          8
1747 
`define OR1200_ICCFGR_CCRI_BITS         9
1748 
`define OR1200_ICCFGR_CBIRI_BITS        10
1749 
`define OR1200_ICCFGR_CBPRI_BITS        11
1750 
`define OR1200_ICCFGR_CBLRI_BITS        12
1751 
`define OR1200_ICCFGR_CBFRI_BITS        13
1752 
`define OR1200_ICCFGR_CBWBRI_BITS       14
1753 
`define OR1200_ICCFGR_RES1_BITS 31:15
1754 
 
1755 
// ICCFGR values
1756 
`ifdef OR1200_NO_IC
1757 
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1758 
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1759 
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1760 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1761 
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1762 
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1763 
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1764 
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1765 
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1766 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1767 
`define OR1200_ICCFGR_RES1              17'h00000
1768 
`else
1769 
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1770 
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1771 
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1772 
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1773 
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1774 
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1775 
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1776 
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1777 
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1778 
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1779 
`define OR1200_ICCFGR_RES1              17'h00000
1780 
`endif
1781 
 
1782 
// DCFGR fields
1783 141 marcus.erl 
`define OR1200_DCFGR_NDP_BITS           3:0
1784 
`define OR1200_DCFGR_WPCI_BITS          4
1785 
`define OR1200_DCFGR_RES1_BITS          31:5
1786 10 unneback 
 
1787 
// DCFGR values
1788 
`ifdef OR1200_DU_HWBKPTS
1789 141 marcus.erl 
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1790 10 unneback 
`ifdef OR1200_DU_DWCR0
1791 
`define OR1200_DCFGR_WPCI               1'b1
1792 
`else
1793 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1794 
`endif
1795 
`else
1796 141 marcus.erl 
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1797 10 unneback 
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1798 
`endif
1799 
`define OR1200_DCFGR_RES1               28'h0000000
1800 141 marcus.erl 
 
1801 
///////////////////////////////////////////////////////////////////////////////
1802 
// Boot Address Selection                                                    //
1803 
///////////////////////////////////////////////////////////////////////////////
1804 
 // Boot from ROM at 0xf0000100
1805 
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1806 
`define OR1200_BOOT_ADR 32'hf0000100
1807 
// Boot from 0x100
1808 
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1809 
// `define OR1200_BOOT_ADR 32'h00000100

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