Subversion Repositories openrisc_2011-10-31

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's definitions                                        ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://opencores.org/project,or1k                           ////

////                                                              ////

////  Description                                                 ////

////  Defines for the OR1200 core                                 ////

////                                                              ////

////  To Do:                                                      ////

////   - add parameters that are missing                          ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// $Log: or1200_defines.v,v $

// Revision 2.0  2010/06/30 11:00:00  ORSoC

// Minor update: 

// Defines added, bugs fixed. 

//

// Dump VCD

//

//`define OR1200_VCD_DUMP

//

// Generate debug messages during simulation

//

//`define OR1200_VERBOSE

//  `define OR1200_ASIC

////////////////////////////////////////////////////////

//

// Typical configuration for an ASIC

//

`ifdef OR1200_ASIC

//

// Target ASIC memories

//

//`define OR1200_ARTISAN_SSP

//`define OR1200_ARTISAN_SDP

//`define OR1200_ARTISAN_STP

`define OR1200_VIRTUALSILICON_SSP

//`define OR1200_VIRTUALSILICON_STP_T1

//`define OR1200_VIRTUALSILICON_STP_T2

//

// Do not implement Data cache

//

//`define OR1200_NO_DC

//

// Do not implement Insn cache

//

//`define OR1200_NO_IC

//

// Do not implement Data MMU

//

//`define OR1200_NO_DMMU

//

// Do not implement Insn MMU

//

//`define OR1200_NO_IMMU

//

// Select between ASIC optimized and generic multiplier

//

//`define OR1200_ASIC_MULTP2_32X32

`define OR1200_GENERIC_MULTP2_32X32

//

// Size/type of insn/data cache if implemented

//

// `define OR1200_IC_1W_512B

// `define OR1200_IC_1W_4KB

`define OR1200_IC_1W_8KB

// `define OR1200_DC_1W_4KB

`define OR1200_DC_1W_8KB

`else

/////////////////////////////////////////////////////////

//

// Typical configuration for an FPGA

//

//

// Target FPGA memories

//

//`define OR1200_ALTERA_LPM

//`define OR1200_XILINX_RAMB16

//`define OR1200_XILINX_RAMB4

//`define OR1200_XILINX_RAM32X1D

//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D

// Generic models should infer RAM blocks at synthesis time (not only effects 

// single port ram.)

`define OR1200_GENERIC

//

// Do not implement Data cache

//

//`define OR1200_NO_DC

//

// Do not implement Insn cache

//

//`define OR1200_NO_IC

//

// Do not implement Data MMU

//

//`define OR1200_NO_DMMU

//

// Do not implement Insn MMU

//

//`define OR1200_NO_IMMU

//

// Select between ASIC and generic multiplier

//

// (Generic seems to trigger a bug in the Cadence Ncsim simulator)

//

//`define OR1200_ASIC_MULTP2_32X32

`define OR1200_GENERIC_MULTP2_32X32

//

// Size/type of insn/data cache if implemented

// (consider available FPGA memory resources)

//

//`define OR1200_IC_1W_512B

//`define OR1200_IC_1W_4KB

`define OR1200_IC_1W_8KB

//`define OR1200_DC_1W_4KB

`define OR1200_DC_1W_8KB

`endif

//////////////////////////////////////////////////////////

//

// Do not change below unless you know what you are doing

//

//

// Reset active low

//

//`define OR1200_RST_ACT_LOW

//

// Enable RAM BIST

//

// At the moment this only works for Virtual Silicon

// single port RAMs. For other RAMs it has not effect.

// Special wrapper for VS RAMs needs to be provided

// with scan flops to facilitate bist scan.

//

//`define OR1200_BIST

//

// Register OR1200 WISHBONE outputs

// (must be defined/enabled)

//

`define OR1200_REGISTERED_OUTPUTS

//

// Register OR1200 WISHBONE inputs

//

// (must be undefined/disabled)

//

//`define OR1200_REGISTERED_INPUTS

//

// Disable bursts if they are not supported by the

// memory subsystem (only affect cache line fill)

//

//`define OR1200_NO_BURSTS

//

//

// WISHBONE retry counter range

//

// 2^value range for retry counter. Retry counter

// is activated whenever *wb_rty_i is asserted and

// until retry counter expires, corresponding

// WISHBONE interface is deactivated.

//

// To disable retry counters and *wb_rty_i all together,

// undefine this macro.

//

//`define OR1200_WB_RETRY 7

//

// WISHBONE Consecutive Address Burst

//

// This was used prior to WISHBONE B3 specification

// to identify bursts. It is no longer needed but

// remains enabled for compatibility with old designs.

//

// To remove *wb_cab_o ports undefine this macro.

//

//`define OR1200_WB_CAB

//

// WISHBONE B3 compatible interface

//

// This follows the WISHBONE B3 specification.

// It is not enabled by default because most

// designs still don't use WB b3.

//

// To enable *wb_cti_o/*wb_bte_o ports,

// define this macro.

//

`define OR1200_WB_B3

//

// LOG all WISHBONE accesses

//

`define OR1200_LOG_WB_ACCESS

//

// Enable additional synthesis directives if using

// _Synopsys_ synthesis tool

//

//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES

//

// Enables default statement in some case blocks

// and disables Synopsys synthesis directive full_case

//

// By default it is enabled. When disabled it

// can increase clock frequency.

//

`define OR1200_CASE_DEFAULT

//

// Operand width / register file address width

//

// (DO NOT CHANGE)

//

`define OR1200_OPERAND_WIDTH            32

`define OR1200_REGFILE_ADDR_WIDTH       5

//

// l.add/l.addi/l.and and optional l.addc/l.addic

// also set (compare) flag when result of their

// operation equals zero

//

// At the time of writing this, default or32

// C/C++ compiler doesn't generate code that

// would benefit from this optimization.

//

// By default this optimization is disabled to

// save area.

//

//`define OR1200_ADDITIONAL_FLAG_MODIFIERS

//

// Implement l.addc/l.addic instructions

//

// By default implementation of l.addc/l.addic

// instructions is enabled in case you need them.

// If you don't use them, then disable implementation

// to save area.

//

//`define OR1200_IMPL_ADDC

//

// Implement l.sub instruction

//

// By default implementation of l.sub instructions

// is enabled to be compliant with the simulator.

// If you don't use carry bit, then disable

// implementation to save area.

//

`define OR1200_IMPL_SUB

//

// Implement carry bit SR[CY]

//

//

// By default implementation of SR[CY] is enabled

// to be compliant with the simulator. However SR[CY]

// is explicitly only used by l.addc/l.addic/l.sub

// instructions and if these three insns are not

// implemented there is not much point having SR[CY].

//

//`define OR1200_IMPL_CY

//

// Implement rotate in the ALU

//

// At the time of writing this, or32

// C/C++ compiler doesn't generate rotate

// instructions. However or32 assembler

// can assemble code that uses rotate insn.

// This means that rotate instructions

// must be used manually inserted.

//

// By default implementation of rotate

// is disabled to save area and increase

// clock frequency.

//

//`define OR1200_IMPL_ALU_ROTATE

//

// Type of ALU compare to implement

//

// Try either one to find what yields

// higher clock frequencyin your case.

//

//`define OR1200_IMPL_ALU_COMP1

`define OR1200_IMPL_ALU_COMP2

//

// Implement Find First/Last '1'

//

`define OR1200_IMPL_ALU_FFL1

//

// Implement multiplier

//

// By default multiplier is implemented

//

`define OR1200_MULT_IMPLEMENTED

//

// Implement multiply-and-accumulate

//

// By default MAC is implemented. To

// implement MAC, multiplier needs to be

// implemented.

//

`define OR1200_MAC_IMPLEMENTED

//

// Implement optional l.div/l.divu instructions

//

// By default divide instructions are not implemented

// to save area and increase clock frequency. or32 C/C++

// compiler can use soft library for division.

//

// To implement divide, both multiplier and MAC needs to be implemented.

//

`define OR1200_DIV_IMPLEMENTED

//

// Low power, slower multiplier

//

// Select between low-power (larger) multiplier

// and faster multiplier. The actual difference

// is only AND logic that prevents distribution

// of operands into the multiplier when instruction

// in execution is not multiply instruction

//

//`define OR1200_LOWPWR_MULT

//

// Implement HW Single Precision FPU

//

//`define OR1200_FPU_IMPLEMENTED

//

//

// Clock ratio RISC clock versus WB clock

//

// If you plan to run WB:RISC clock fixed to 1:1, disable

// both defines

//

// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED

// and use clmode to set ratio

//

// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use

// clmode to set ratio

//

//`define OR1200_CLKDIV_2_SUPPORTED

//`define OR1200_CLKDIV_4_SUPPORTED

//

// Type of register file RAM

//

// Memory macro w/ two ports (see or1200_tpram_32x32.v)

//`define OR1200_RFRAM_TWOPORT

//

// Memory macro dual port (see or1200_dpram.v)

`define OR1200_RFRAM_DUALPORT

//

// Generic (flip-flop based) register file (see or1200_rfram_generic.v)

//`define OR1200_RFRAM_GENERIC

//  Generic register file supports - 16 registers 

`ifdef OR1200_RFRAM_GENERIC

//    `define OR1200_RFRAM_16REG

`endif

//

// Type of mem2reg aligner to implement.

//

// Once OR1200_IMPL_MEM2REG2 yielded faster

// circuit, however with today tools it will

// most probably give you slower circuit.

//

`define OR1200_IMPL_MEM2REG1

//`define OR1200_IMPL_MEM2REG2

//

// Reset value and event

//

`ifdef OR1200_RST_ACT_LOW

  `define OR1200_RST_VALUE      (1'b0)

  `define OR1200_RST_EVENT      negedge

`else

  `define OR1200_RST_VALUE      (1'b1)

  `define OR1200_RST_EVENT      posedge

`endif

//

// ALUOPs

//

`define OR1200_ALUOP_WIDTH      4

`define OR1200_ALUOP_NOP        4'd4

/* Order defined by arith insns that have two source operands both in regs

   (see binutils/include/opcode/or32.h) */

`define OR1200_ALUOP_ADD        4'd0

`define OR1200_ALUOP_ADDC       4'd1

`define OR1200_ALUOP_SUB        4'd2

`define OR1200_ALUOP_AND        4'd3

`define OR1200_ALUOP_OR         4'd4

`define OR1200_ALUOP_XOR        4'd5

`define OR1200_ALUOP_MUL        4'd6

`define OR1200_ALUOP_CUST5      4'd7

`define OR1200_ALUOP_SHROT      4'd8

`define OR1200_ALUOP_DIV        4'd9

`define OR1200_ALUOP_DIVU       4'd10

/* Order not specifically defined. */

`define OR1200_ALUOP_IMM        4'd11

`define OR1200_ALUOP_MOVHI      4'd12

`define OR1200_ALUOP_COMP       4'd13

`define OR1200_ALUOP_MTSR       4'd14

`define OR1200_ALUOP_MFSR       4'd15

`define OR1200_ALUOP_CMOV       4'd14

`define OR1200_ALUOP_FFL1       4'd15

// ALU instructions second opcode field (previously multicycle field in 

// machine word)

`define OR1200_ALUOP2_POS               9:8

`define OR1200_ALUOP2_WIDTH     2

//

// MACOPs

//

`define OR1200_MACOP_WIDTH      3

`define OR1200_MACOP_NOP        3'b000

`define OR1200_MACOP_MAC        3'b001

`define OR1200_MACOP_MSB        3'b010

//

// Shift/rotate ops

//

`define OR1200_SHROTOP_WIDTH    2

`define OR1200_SHROTOP_NOP      2'd0

`define OR1200_SHROTOP_SLL      2'd0

`define OR1200_SHROTOP_SRL      2'd1

`define OR1200_SHROTOP_SRA      2'd2

`define OR1200_SHROTOP_ROR      2'd3

// Execution cycles per instruction

`define OR1200_MULTICYCLE_WIDTH 3

`define OR1200_ONE_CYCLE                3'd0

`define OR1200_TWO_CYCLES               3'd1

// Execution control which will "wait on" a module to finish

`define OR1200_WAIT_ON_WIDTH 2

`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1

`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2

// Operand MUX selects

`define OR1200_SEL_WIDTH                2

`define OR1200_SEL_RF                   2'd0

`define OR1200_SEL_IMM                  2'd1

`define OR1200_SEL_EX_FORW              2'd2

`define OR1200_SEL_WB_FORW              2'd3

//

// BRANCHOPs

//

`define OR1200_BRANCHOP_WIDTH           3

`define OR1200_BRANCHOP_NOP             3'd0

`define OR1200_BRANCHOP_J               3'd1

`define OR1200_BRANCHOP_JR              3'd2

`define OR1200_BRANCHOP_BAL             3'd3

`define OR1200_BRANCHOP_BF              3'd4

`define OR1200_BRANCHOP_BNF             3'd5

`define OR1200_BRANCHOP_RFE             3'd6

//

// LSUOPs

//

// Bit 0: sign extend

// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword

// Bit 3: 0 load, 1 store

`define OR1200_LSUOP_WIDTH              4

`define OR1200_LSUOP_NOP                4'b0000

`define OR1200_LSUOP_LBZ                4'b0010

`define OR1200_LSUOP_LBS                4'b0011

`define OR1200_LSUOP_LHZ                4'b0100

`define OR1200_LSUOP_LHS                4'b0101

`define OR1200_LSUOP_LWZ                4'b0110

`define OR1200_LSUOP_LWS                4'b0111

`define OR1200_LSUOP_LD                 4'b0001

`define OR1200_LSUOP_SD                 4'b1000

`define OR1200_LSUOP_SB                 4'b1010

`define OR1200_LSUOP_SH                 4'b1100

`define OR1200_LSUOP_SW                 4'b1110

// Number of bits of load/store EA precalculated in ID stage

// for balancing ID and EX stages.

//

// Valid range: 2,3,...,30,31

`define OR1200_LSUEA_PRECALC            2

// FETCHOPs

`define OR1200_FETCHOP_WIDTH            1

`define OR1200_FETCHOP_NOP              1'b0

`define OR1200_FETCHOP_LW               1'b1

//

// Register File Write-Back OPs

//

// Bit 0: register file write enable

// Bits 3-1: write-back mux selects

//

`define OR1200_RFWBOP_WIDTH             4

`define OR1200_RFWBOP_NOP               4'b0000

`define OR1200_RFWBOP_ALU               3'b000

`define OR1200_RFWBOP_LSU               3'b001

`define OR1200_RFWBOP_SPRS              3'b010

`define OR1200_RFWBOP_LR                3'b011

`define OR1200_RFWBOP_FPU               3'b100

// Compare instructions

`define OR1200_COP_SFEQ       3'b000

`define OR1200_COP_SFNE       3'b001

`define OR1200_COP_SFGT       3'b010

`define OR1200_COP_SFGE       3'b011

`define OR1200_COP_SFLT       3'b100

`define OR1200_COP_SFLE       3'b101

`define OR1200_COP_X          3'b111

`define OR1200_SIGNED_COMPARE 'd3

`define OR1200_COMPOP_WIDTH     4

//

// FP OPs

//

// MSbit indicates FPU operation valid

//

`define OR1200_FPUOP_WIDTH      8

// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles

`define OR1200_FPUOP_CYCLES 3'd4

// FP instruction is double precision if bit 4 is set. We're a 32-bit 

// implementation thus do not support double precision FP 

`define OR1200_FPUOP_DOUBLE_BIT 4

`define OR1200_FPUOP_ADD  8'b0000_0000

`define OR1200_FPUOP_SUB  8'b0000_0001

`define OR1200_FPUOP_MUL  8'b0000_0010

`define OR1200_FPUOP_DIV  8'b0000_0011

`define OR1200_FPUOP_ITOF 8'b0000_0100

`define OR1200_FPUOP_FTOI 8'b0000_0101

`define OR1200_FPUOP_REM  8'b0000_0110

`define OR1200_FPUOP_RESERVED  8'b0000_0111

// FP Compare instructions

`define OR1200_FPCOP_SFEQ 8'b0000_1000

`define OR1200_FPCOP_SFNE 8'b0000_1001

`define OR1200_FPCOP_SFGT 8'b0000_1010

`define OR1200_FPCOP_SFGE 8'b0000_1011

`define OR1200_FPCOP_SFLT 8'b0000_1100

`define OR1200_FPCOP_SFLE 8'b0000_1101

//

// TAGs for instruction bus

//

`define OR1200_ITAG_IDLE        4'h0    // idle bus

`define OR1200_ITAG_NI          4'h1    // normal insn

`define OR1200_ITAG_BE          4'hb    // Bus error exception

`define OR1200_ITAG_PE          4'hc    // Page fault exception

`define OR1200_ITAG_TE          4'hd    // TLB miss exception

//

// TAGs for data bus

//

`define OR1200_DTAG_IDLE        4'h0    // idle bus

`define OR1200_DTAG_ND          4'h1    // normal data

`define OR1200_DTAG_AE          4'ha    // Alignment exception

`define OR1200_DTAG_BE          4'hb    // Bus error exception

`define OR1200_DTAG_PE          4'hc    // Page fault exception

`define OR1200_DTAG_TE          4'hd    // TLB miss exception

//////////////////////////////////////////////

//

// ORBIS32 ISA specifics

//

// SHROT_OP position in machine word

`define OR1200_SHROTOP_POS              7:6

//

// Instruction opcode groups (basic)

//

`define OR1200_OR32_J                 6'b000000

`define OR1200_OR32_JAL               6'b000001

`define OR1200_OR32_BNF               6'b000011

`define OR1200_OR32_BF                6'b000100

`define OR1200_OR32_NOP               6'b000101

`define OR1200_OR32_MOVHI             6'b000110

`define OR1200_OR32_XSYNC             6'b001000

`define OR1200_OR32_RFE               6'b001001

/* */

`define OR1200_OR32_JR                6'b010001

`define OR1200_OR32_JALR              6'b010010

`define OR1200_OR32_MACI              6'b010011

/* */

`define OR1200_OR32_LWZ               6'b100001

`define OR1200_OR32_LBZ               6'b100011

`define OR1200_OR32_LBS               6'b100100

`define OR1200_OR32_LHZ               6'b100101

`define OR1200_OR32_LHS               6'b100110

`define OR1200_OR32_ADDI              6'b100111

`define OR1200_OR32_ADDIC             6'b101000

`define OR1200_OR32_ANDI              6'b101001

`define OR1200_OR32_ORI               6'b101010

`define OR1200_OR32_XORI              6'b101011

`define OR1200_OR32_MULI              6'b101100

`define OR1200_OR32_MFSPR             6'b101101

`define OR1200_OR32_SH_ROTI           6'b101110

`define OR1200_OR32_SFXXI             6'b101111

/* */

`define OR1200_OR32_MTSPR             6'b110000

`define OR1200_OR32_MACMSB            6'b110001

`define OR1200_OR32_FLOAT             6'b110010

/* */

`define OR1200_OR32_SW                6'b110101

`define OR1200_OR32_SB                6'b110110

`define OR1200_OR32_SH                6'b110111

`define OR1200_OR32_ALU               6'b111000

`define OR1200_OR32_SFXX              6'b111001

//`define OR1200_OR32_CUST5             6'b111100

/////////////////////////////////////////////////////

//

// Exceptions

//

//

// Exception vectors per OR1K architecture:

// 0xPPPPP100 - reset

// 0xPPPPP200 - bus error

// ... etc

// where P represents exception prefix.

//

// Exception vectors can be customized as per

// the following formula:

// 0xPPPPPNVV - exception N

//

// P represents exception prefix

// N represents exception N

// VV represents length of the individual vector space,

//   usually it is 8 bits wide and starts with all bits zero

//

//

// PPPPP and VV parts

//

// Sum of these two defines needs to be 28

//

`define OR1200_EXCEPT_EPH0_P    20'h00000

`define OR1200_EXCEPT_EPH1_P    20'hF0000

`define OR1200_EXCEPT_V             8'h00

//

// N part width

//

`define OR1200_EXCEPT_WIDTH 4

//

// Definition of exception vectors

//

// To avoid implementation of a certain exception,

// simply comment out corresponding line

//

`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf

`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he

`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd

`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc

`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb

`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha

`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9

`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8

`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7

`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6

`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5

`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4

`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3

`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2

`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1

`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0

/////////////////////////////////////////////////////

//

// SPR groups

//

// Bits that define the group

`define OR1200_SPR_GROUP_BITS   15:11

// Width of the group bits

`define OR1200_SPR_GROUP_WIDTH  5

// Bits that define offset inside the group

`define OR1200_SPR_OFS_BITS 10:0

// List of groups

`define OR1200_SPR_GROUP_SYS    5'd00

`define OR1200_SPR_GROUP_DMMU   5'd01

`define OR1200_SPR_GROUP_IMMU   5'd02

`define OR1200_SPR_GROUP_DC     5'd03

`define OR1200_SPR_GROUP_IC     5'd04

`define OR1200_SPR_GROUP_MAC    5'd05

`define OR1200_SPR_GROUP_DU     5'd06

`define OR1200_SPR_GROUP_PM     5'd08

`define OR1200_SPR_GROUP_PIC    5'd09

`define OR1200_SPR_GROUP_TT     5'd10

`define OR1200_SPR_GROUP_FPU    5'd11

/////////////////////////////////////////////////////

//

// System group

//

//

// System registers

//

`define OR1200_SPR_CFGR         7'd0

`define OR1200_SPR_RF           6'd32   // 1024 >> 5