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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Blame information for rev 10

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data MMU top level                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DMMU blocks.                           ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7.4.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.5  2002/02/14 15:34:02  simons
// Lapsus fixed.
//
// Revision 1.4  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/17 08:03:35  lampret
// *** empty log message ***
//
// Revision 1.2  2001/07/22 03:31:53  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Data MMU
//
 
module or1200_dmmu_top(
        // Rst and clk
        clk, rst,
 
        // CPU i/f
        dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
        dcpu_tag_o, dcpu_err_o,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // DC i/f
        qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// CPU I/F
//
input                           dc_en;
input                           dmmu_en;
input                           supv;
input   [aw-1:0]         dcpu_adr_i;
input                           dcpu_cycstb_i;
input                           dcpu_we_i;
output  [3:0]                    dcpu_tag_o;
output                          dcpu_err_o;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [aw-1:0]         spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// DC I/F
//
input                           qmemdmmu_err_i;
input   [3:0]                    qmemdmmu_tag_i;
output  [aw-1:0]         qmemdmmu_adr_o;
output                          qmemdmmu_cycstb_o;
output                          qmemdmmu_ci_o;
 
//
// Internal wires and regs
//
wire                            dtlb_spr_access;
wire    [31:`OR1200_DMMU_PS]    dtlb_ppn;
wire                            dtlb_hit;
wire                            dtlb_uwe;
wire                            dtlb_ure;
wire                            dtlb_swe;
wire                            dtlb_sre;
wire    [31:0]                   dtlb_dat_o;
wire                            dtlb_en;
wire                            dtlb_ci;
wire                            fault;
wire                            miss;
`ifdef OR1200_NO_DMMU
`else
reg                             dtlb_done;
reg     [31:`OR1200_DMMU_PS]    dcpu_vpn_r;
`endif
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-10  v 0
// dtlbwYtrX: ppn 31-10  swe 9  sre 8  uwe 7  ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
 
`ifdef OR1200_NO_DMMU
 
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = qmemdmmu_tag_i;
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// DTLB SPR access
//
// 0A00 - 0AFF  dtlbmr w0
// 0A00 - 0A3F  dtlbmr w0 [63:0]
//
// 0B00 - 0BFF  dtlbtr w0
// 0B00 - 0B3F  dtlbtr w0 [63:0]
//
assign dtlb_spr_access = spr_cs;
 
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
 
//
// dcpu_err_o
//
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
 
//
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
//
always @(posedge clk or posedge rst)
        if (rst)
                dtlb_done <= #1 1'b0;
        else if (dtlb_en)
                dtlb_done <= #1 dcpu_cycstb_i;
        else
                dtlb_done <= #1 1'b0;
 
//
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
//
assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
 
//
// Cache Inhibit
//
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
 
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
        if (rst)
                dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};
        else
                dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];
 
//
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
 
//
// Output to SPRS unit
//
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
 
//
// Page fault exception logic
//
assign fault = dtlb_done &
                        (  (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
                        || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
                        || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
                        || (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
 
//
// TLB Miss exception logic
//
assign miss = dtlb_done & !dtlb_hit;
 
//
// DTLB Enable
//
assign dtlb_en = dmmu_en & dcpu_cycstb_i;
 
//
// Instantiation of DTLB
//
or1200_dmmu_tlb or1200_dmmu_tlb(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // I/F for translation
        .tlb_en(dtlb_en),
        .vaddr(dcpu_adr_i),
        .hit(dtlb_hit),
        .ppn(dtlb_ppn),
        .uwe(dtlb_uwe),
        .ure(dtlb_ure),
        .swe(dtlb_swe),
        .sre(dtlb_sre),
        .ci(dtlb_ci),
 
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
 
        // SPR access
        .spr_cs(dtlb_spr_access),
        .spr_write(spr_write),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_i),
        .spr_dat_o(dtlb_dat_o)
);
 
`endif
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dmmu_top.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data MMU top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all DMMU blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.7.4.2 2003/12/09 11:46:48 simons`
48			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
49			`//`
50			`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
51			`// Added embedded memory QMEM.`
52			`//`
53			`// Revision 1.7 2002/10/17 20:04:40 lampret`
54			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
55			`//`
56			`// Revision 1.6 2002/03/29 15:16:55 lampret`
57			`// Some of the warnings fixed.`
58			`//`
59			`// Revision 1.5 2002/02/14 15:34:02 simons`
60			`// Lapsus fixed.`
61			`//`
62			`// Revision 1.4 2002/02/11 04:33:17 lampret`
63			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
64			`//`
65			`// Revision 1.3 2002/01/28 01:16:00 lampret`
66			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
67			`//`
68			`// Revision 1.2 2002/01/14 06:18:22 lampret`
69			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
70			`//`
71			`// Revision 1.1 2002/01/03 08:16:15 lampret`
72			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
73			`//`
74			`// Revision 1.6 2001/10/21 17:57:16 lampret`
75			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
76			`//`
77			`// Revision 1.5 2001/10/14 13:12:09 lampret`
78			`// MP3 version.`
79			`//`
80			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
81			`// no message`
82			`//`
83			`// Revision 1.1 2001/08/17 08:03:35 lampret`
84			`// * empty log message *`
85			`//`
86			`// Revision 1.2 2001/07/22 03:31:53 lampret`
87			`// Fixed RAM's oen bug. Cache bypass under development.`
88			`//`
89			`// Revision 1.1 2001/07/20 00:46:03 lampret`
90			`// Development version of RTL. Libraries are missing.`
91			`//`
92			`//`
93
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "or1200_defines.v"
98
99			`//`
100			`// Data MMU`
101			`//`
102
103			`module or1200_dmmu_top(`
104			`// Rst and clk`
105			`clk, rst,`
106
107			`// CPU i/f`
108			`dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,`
109			`dcpu_tag_o, dcpu_err_o,`
110
111			`// SPR access`
112			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
113
114			`ifdef OR1200_BIST
115			`// RAM BIST`
116			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
117			`endif
118
119			`// DC i/f`
120			`qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o`
121			`);`
122
123			parameter dw = `OR1200_OPERAND_WIDTH;
124			parameter aw = `OR1200_OPERAND_WIDTH;
125
126			`//`
127			`// I/O`
128			`//`
129
130			`//`
131			`// Clock and reset`
132			`//`
133			`input clk;`
134			`input rst;`
135
136			`//`
137			`// CPU I/F`
138			`//`
139			`input dc_en;`
140			`input dmmu_en;`
141			`input supv;`
142			`input [aw-1:0] dcpu_adr_i;`
143			`input dcpu_cycstb_i;`
144			`input dcpu_we_i;`
145			`output [3:0] dcpu_tag_o;`
146			`output dcpu_err_o;`
147
148			`//`
149			`// SPR access`
150			`//`
151			`input spr_cs;`
152			`input spr_write;`
153			`input [aw-1:0] spr_addr;`
154			`input [31:0] spr_dat_i;`
155			`output [31:0] spr_dat_o;`
156
157			`ifdef OR1200_BIST
158			`//`
159			`// RAM BIST`
160			`//`
161			`input mbist_si_i;`
162			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
163			`output mbist_so_o;`
164			`endif
165
166			`//`
167			`// DC I/F`
168			`//`
169			`input qmemdmmu_err_i;`
170			`input [3:0] qmemdmmu_tag_i;`
171			`output [aw-1:0] qmemdmmu_adr_o;`
172			`output qmemdmmu_cycstb_o;`
173			`output qmemdmmu_ci_o;`
174
175			`//`
176			`// Internal wires and regs`
177			`//`
178			`wire dtlb_spr_access;`
179			wire [31:`OR1200_DMMU_PS] dtlb_ppn;
180			`wire dtlb_hit;`
181			`wire dtlb_uwe;`
182			`wire dtlb_ure;`
183			`wire dtlb_swe;`
184			`wire dtlb_sre;`
185			`wire [31:0] dtlb_dat_o;`
186			`wire dtlb_en;`
187			`wire dtlb_ci;`
188			`wire fault;`
189			`wire miss;`
190			`ifdef OR1200_NO_DMMU
191			`else
192			`reg dtlb_done;`
193			reg [31:`OR1200_DMMU_PS] dcpu_vpn_r;
194			`endif
195
196			`//`
197			`// Implemented bits inside match and translate registers`
198			`//`
199			`// dtlbwYmrX: vpn 31-10 v 0`
200			`// dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6`
201			`//`
202			`// dtlb memory width:`
203			`// 19 bits for ppn`
204			`// 13 bits for vpn`
205			`// 1 bit for valid`
206			`// 4 bits for protection`
207			`// 1 bit for cache inhibit`
208
209			`ifdef OR1200_NO_DMMU
210
211			`//`
212			`// Put all outputs in inactive state`
213			`//`
214			`assign spr_dat_o = 32'h00000000;`
215			`assign qmemdmmu_adr_o = dcpu_adr_i;`
216			`assign dcpu_tag_o = qmemdmmu_tag_i;`
217			`assign qmemdmmu_cycstb_o = dcpu_cycstb_i;`
218			`assign dcpu_err_o = qmemdmmu_err_i;`
219			assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
220			`ifdef OR1200_BIST
221			`assign mbist_so_o = mbist_si_i;`
222			`endif
223
224			`else
225
226			`//`
227			`// DTLB SPR access`
228			`//`
229			`// 0A00 - 0AFF dtlbmr w0`
230			`// 0A00 - 0A3F dtlbmr w0 [63:0]`
231			`//`
232			`// 0B00 - 0BFF dtlbtr w0`
233			`// 0B00 - 0B3F dtlbtr w0 [63:0]`
234			`//`
235			`assign dtlb_spr_access = spr_cs;`
236
237			`//`
238			`// Tags:`
239			`//`
240			`// OR1200_DTAG_TE - TLB miss Exception`
241			`// OR1200_DTAG_PE - Page fault Exception`
242			`//`
243			assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
244
245			`//`
246			`// dcpu_err_o`
247			`//`
248			`assign dcpu_err_o = miss \| fault \| qmemdmmu_err_i;`
249
250			`//`
251			`// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.`
252			`//`
253			`always @(posedge clk or posedge rst)`
254			`if (rst)`
255			`dtlb_done <= #1 1'b0;`
256			`else if (dtlb_en)`
257			`dtlb_done <= #1 dcpu_cycstb_i;`
258			`else`
259			`dtlb_done <= #1 1'b0;`
260
261			`//`
262			`// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.`
263			`//`
264			`assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss \| fault) & dtlb_done & dcpu_cycstb_i : ~(miss \| fault) & dcpu_cycstb_i;`
265			`//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss \| fault) & dcpu_cycstb_i : (miss \| fault) ? 1'b0 : dcpu_cycstb_i;`
266
267			`//`
268			`// Cache Inhibit`
269			`//`
270			assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
271
272			`//`
273			`// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come`
274			`// one clock cycle after offset part.`
275			`//`
276			`always @(posedge clk or posedge rst)`
277			`if (rst)`
278			dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};
279			`else`
280			dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];
281
282			`//`
283			`// Physical address is either translated virtual address or`
284			`// simply equal when DMMU is disabled`
285			`//`
286			// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
287			assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
288
289			`//`
290			`// Output to SPRS unit`
291			`//`
292			`assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;`
293
294			`//`
295			`// Page fault exception logic`
296			`//`
297			`assign fault = dtlb_done &`
298			`( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled`
299			`\|\| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled`
300			`\|\| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled`
301			`\|\| (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled`
302
303			`//`
304			`// TLB Miss exception logic`
305			`//`
306			`assign miss = dtlb_done & !dtlb_hit;`
307
308			`//`
309			`// DTLB Enable`
310			`//`
311			`assign dtlb_en = dmmu_en & dcpu_cycstb_i;`
312
313			`//`
314			`// Instantiation of DTLB`
315			`//`
316			`or1200_dmmu_tlb or1200_dmmu_tlb(`
317			`// Rst and clk`
318			`.clk(clk),`
319			`.rst(rst),`
320
321			`// I/F for translation`
322			`.tlb_en(dtlb_en),`
323			`.vaddr(dcpu_adr_i),`
324			`.hit(dtlb_hit),`
325			`.ppn(dtlb_ppn),`
326			`.uwe(dtlb_uwe),`
327			`.ure(dtlb_ure),`
328			`.swe(dtlb_swe),`
329			`.sre(dtlb_sre),`
330			`.ci(dtlb_ci),`
331
332			`ifdef OR1200_BIST
333			`// RAM BIST`
334			`.mbist_si_i(mbist_si_i),`
335			`.mbist_so_o(mbist_so_o),`
336			`.mbist_ctrl_i(mbist_ctrl_i),`
337			`endif
338
339			`// SPR access`
340			`.spr_cs(dtlb_spr_access),`
341			`.spr_write(spr_write),`
342			`.spr_addr(spr_addr),`
343			`.spr_dat_i(spr_dat_i),`
344			`.spr_dat_o(dtlb_dat_o)`
345			`);`
346
347			`endif
348
349			`endmodule`