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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Generic Double-Port Synchronous RAM                         ////

////                                                              ////

////  This file is part of memory library available from          ////

////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////

////                                                              ////

////  Description                                                 ////

////  This block is a wrapper with common double-port             ////

////  synchronous memory interface for different                  ////

////  types of ASIC and FPGA RAMs. Beside universal memory        ////

////  interface it also provides behavioral model of generic      ////

////  double-port synchronous RAM.                                ////

////  It should be used in all OPENCORES designs that want to be  ////

////  portable accross different target technologies and          ////

////  independent of target memory.                               ////

////                                                              ////

////  Supported ASIC RAMs are:                                    ////

////                                                              ////

////  Supported FPGA RAMs are:                                    ////

////  - Xilinx Virtex RAMB16                                      ////

////  - Xilinx Virtex RAMB4                                       ////

////                                                              ////

////  To Do:                                                      ////

////   - add additional RAMs                                      ////

////   - xilinx rams need external tri-state logic                ////

////                                                              ////

////  Author(s):                                                  ////

////      - Nir  Mor, nirm@opencores.org                          ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2005 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "or1200_defines.v"

module or1200_dpram_256x32(

        // Generic synchronous double-port RAM interface

        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,

        clk_b, rst_b, ce_b, we_b, addr_b, di_b

);

//

// Default address and data buses width

//

parameter aw = 8;

parameter dw = 32;

//

// Generic synchronous double-port RAM interface

//

input                   clk_a;  // Clock

input                   rst_a;  // Reset

input                   ce_a;   // Chip enable input

input                   oe_a;   // Output enable input

input   [aw-1:0] addr_a; // address bus inputs

output  [dw-1:0] do_a;   // output data bus

input                   clk_b;  // Clock

input                   rst_b;  // Reset

input                   ce_b;   // Chip enable input

input                   we_b;   // Write enable input

input   [aw-1:0] addr_b; // address bus inputs

input   [dw-1:0] di_b;   // input data bus

`ifdef OR1200_XILINX_RAMB4

//

// Instantiation of FPGA memory:

//

// Virtex/Spartan2

//

//

// Block 0

//

RAMB4_S16_S16 ramb4_s16_0(

        .CLKA(clk_a),

        .RSTA(rst_a),

        .ADDRA(addr_a),

        .DIA(16'h0000),

        .ENA(ce_a),

        .WEA(1'b0),

        .DOA(do_a[15:0]),

        .CLKB(clk_b),

        .RSTB(rst_b),

        .ADDRB(addr_b),

        .DIB(di_b[15:0]),

        .ENB(ce_b),

        .WEB(we_b),

        .DOB()

);

//

// Block 1

//

RAMB4_S16_S16 ramb4_s16_1(

        .CLKA(clk_a),

        .RSTA(rst_a),

        .ADDRA(addr_a),

        .DIA(16'h0000),

        .ENA(ce_a),

        .WEA(1'b0),

        .DOA(do_a[31:16]),

        .CLKB(clk_b),

        .RSTB(rst_b),

        .ADDRB(addr_b),

        .DIB(di_b[31:16]),

        .ENB(ce_b),

        .WEB(we_b),

        .DOB()

);

`else

`ifdef OR1200_XILINX_RAMB16

//

// Instantiation of FPGA memory:

//

// Virtex4/Spartan3E

//

// Added By Nir Mor

//

RAMB16_S36_S36 ramb16_s36_s36(

        .CLKA(clk_a),

        .SSRA(rst_a),

        .ADDRA({1'b0, addr_a}),

        .DIA(32'h00000000),

        .DIPA(4'h0),

        .ENA(ce_a),

        .WEA(1'b0),

        .DOA(do_a),

        .DOPA(),

        .CLKB(clk_b),

        .SSRB(rst_b),

        .ADDRB({1'b0, addr_b}),

        .DIB(di_b),

        .DIPB(4'h0),

        .ENB(ce_b),

        .WEB(we_b),

        .DOB(),

        .DOPB()

);

`else

//

// Generic double-port synchronous RAM model

//

//

// Generic RAM's registers and wires

//

reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content

reg     [aw-1:0] addr_a_reg;             // RAM address registered

//

// Data output drivers

//

assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};

//

// RAM read

//

always @(posedge clk_a or posedge rst_a)

        if (rst_a)

                addr_a_reg <= #1 {aw{1'b0}};

        else if (ce_a)

                addr_a_reg <= #1 addr_a;

//

// RAM write

//

always @(posedge clk_b)

        if (ce_b && we_b)

                mem[addr_b] <= #1 di_b;

`endif  // !OR1200_XILINX_RAMB16

`endif  // !OR1200_XILINX_RAMB4

endmodule