OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Blame information for rev 45

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Generic Double-Port Synchronous RAM                         ////
4 
////                                                              ////
5 
////  This file is part of memory library available from          ////
6 
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  This block is a wrapper with common double-port             ////
10 
////  synchronous memory interface for different                  ////
11 
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12 
////  interface it also provides behavioral model of generic      ////
13 
////  double-port synchronous RAM.                                ////
14 
////  It should be used in all OPENCORES designs that want to be  ////
15 
////  portable accross different target technologies and          ////
16 
////  independent of target memory.                               ////
17 
////                                                              ////
18 
////  Supported ASIC RAMs are:                                    ////
19 
////  - Artisan Double-Port Sync RAM                              ////
20 
////  - Avant! Two-Port Sync RAM (*)                              ////
21 
////  - Virage 2-port Sync RAM                                    ////
22 
////                                                              ////
23 
////  Supported FPGA RAMs are:                                    ////
24 
////  - Xilinx Virtex RAMB16                                      ////
25 
////  - Xilinx Virtex RAMB4                                       ////
26 
////  - Altera LPM                                                ////
27 
////                                                              ////
28 
////  To Do:                                                      ////
29 
////   - fix Avant!                                               ////
30 
////   - xilinx rams need external tri-state logic                ////
31 
////   - add additional RAMs                                      ////
32 
////                                                              ////
33 
////  Author(s):                                                  ////
34 
////      - Damjan Lampret, lampret@opencores.org                 ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 
////                                                              ////
38 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
39 
////                                                              ////
40 
//// This source file may be used and distributed without         ////
41 
//// restriction provided that this copyright statement is not    ////
42 
//// removed from the file and that any derivative work contains  ////
43 
//// the original copyright notice and the associated disclaimer. ////
44 
////                                                              ////
45 
//// This source file is free software; you can redistribute it   ////
46 
//// and/or modify it under the terms of the GNU Lesser General   ////
47 
//// Public License as published by the Free Software Foundation; ////
48 
//// either version 2.1 of the License, or (at your option) any   ////
49 
//// later version.                                               ////
50 
////                                                              ////
51 
//// This source is distributed in the hope that it will be       ////
52 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55 
//// details.                                                     ////
56 
////                                                              ////
57 
//// You should have received a copy of the GNU Lesser General    ////
58 
//// Public License along with this source; if not, download it   ////
59 
//// from http://www.opencores.org/lgpl.shtml                     ////
60 
////                                                              ////
61 
//////////////////////////////////////////////////////////////////////
62 
//
63 
// CVS Revision History
64 
//
65 
// $Log: not supported by cvs2svn $
66 
// Revision 1.9  2004/06/08 18:15:48  lampret
67 
// Changed behavior of the simulation generic models
68 
//
69 
// Revision 1.8  2004/04/05 08:29:57  lampret
70 
// Merged branch_qmem into main tree.
71 
//
72 
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
73 
// Added embedded memory QMEM.
74 
//
75 
// Revision 1.7  2003/04/07 01:19:07  lampret
76 
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
77 
//
78 
// Revision 1.6  2002/03/28 19:25:42  lampret
79 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
80 
//
81 
// Revision 1.5  2002/02/01 19:56:54  lampret
82 
// Fixed combinational loops.
83 
//
84 
// Revision 1.4  2002/01/23 07:52:36  lampret
85 
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
86 
//
87 
// Revision 1.3  2002/01/19 14:10:22  lampret
88 
// Fixed OR1200_XILINX_RAM32X1D.
89 
//
90 
// Revision 1.2  2002/01/15 06:12:22  lampret
91 
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
92 
//
93 
// Revision 1.1  2002/01/03 08:16:15  lampret
94 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
95 
//
96 
// Revision 1.10  2001/11/05 14:48:00  lampret
97 
// Added missing endif
98 
//
99 
// Revision 1.9  2001/11/02 18:57:14  lampret
100 
// Modified virtual silicon instantiations.
101 
//
102 
// Revision 1.8  2001/10/22 19:39:56  lampret
103 
// Fixed parameters in generic sprams.
104 
//
105 
// Revision 1.7  2001/10/21 17:57:16  lampret
106 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
107 
//
108 
// Revision 1.6  2001/10/14 13:12:09  lampret
109 
// MP3 version.
110 
//
111 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
112 
// no message
113 
//
114 
// Revision 1.1  2001/08/09 13:39:33  lampret
115 
// Major clean-up.
116 
//
117 
// Revision 1.2  2001/07/30 05:38:02  lampret
118 
// Adding empty directories required by HDL coding guidelines
119 
//
120 
//
121 
 
122 
// synopsys translate_off
123 
`include "timescale.v"
124 
// synopsys translate_on
125 
`include "or1200_defines.v"
126 
 
127 
module or1200_dpram_32x32(
128 
        // Generic synchronous double-port RAM interface
129 
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
130 
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
131 
);
132 
 
133 
//
134 
// Default address and data buses width
135 
//
136 
parameter aw = 5;
137 
parameter dw = 32;
138 
 
139 
//
140 
// Generic synchronous double-port RAM interface
141 
//
142 
input                   clk_a;  // Clock
143 
input                   rst_a;  // Reset
144 
input                   ce_a;   // Chip enable input
145 
input                   oe_a;   // Output enable input
146 
input   [aw-1:0] addr_a; // address bus inputs
147 
output  [dw-1:0] do_a;   // output data bus
148 
input                   clk_b;  // Clock
149 
input                   rst_b;  // Reset
150 
input                   ce_b;   // Chip enable input
151 
input                   we_b;   // Write enable input
152 
input   [aw-1:0] addr_b; // address bus inputs
153 
input   [dw-1:0] di_b;   // input data bus
154 
 
155 
//
156 
// Internal wires and registers
157 
//
158 
 
159 
`ifdef OR1200_ARTISAN_SDP
160 
 
161 
//
162 
// Instantiation of ASIC memory:
163 
//
164 
// Artisan Synchronous Double-Port RAM (ra2sh)
165 
//
166 
`ifdef UNUSED
167 
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
168 
`else
169 
art_hsdp_32x32 artisan_sdp(
170 
`endif
171 
        .qa(do_a),
172 
        .clka(clk_a),
173 
        .cena(~ce_a),
174 
        .wena(1'b1),
175 
        .aa(addr_a),
176 
        .da(32'h00000000),
177 
        .oena(~oe_a),
178 
        .qb(),
179 
        .clkb(clk_b),
180 
        .cenb(~ce_b),
181 
        .wenb(~we_b),
182 
        .ab(addr_b),
183 
        .db(di_b),
184 
        .oenb(1'b1)
185 
);
186 
 
187 
`else
188 
 
189 
`ifdef OR1200_AVANT_ATP
190 
 
191 
//
192 
// Instantiation of ASIC memory:
193 
//
194 
// Avant! Asynchronous Two-Port RAM
195 
//
196 
avant_atp avant_atp(
197 
        .web(~we),
198 
        .reb(),
199 
        .oeb(~oe),
200 
        .rcsb(),
201 
        .wcsb(),
202 
        .ra(addr),
203 
        .wa(addr),
204 
        .di(di),
205 
        .doq(doq)
206 
);
207 
 
208 
`else
209 
 
210 
`ifdef OR1200_VIRAGE_STP
211 
 
212 
//
213 
// Instantiation of ASIC memory:
214 
//
215 
// Virage Synchronous 2-port R/W RAM
216 
//
217 
virage_stp virage_stp(
218 
        .QA(do_a),
219 
        .QB(),
220 
 
221 
        .ADRA(addr_a),
222 
        .DA(32'h00000000),
223 
        .WEA(1'b0),
224 
        .OEA(oe_a),
225 
        .MEA(ce_a),
226 
        .CLKA(clk_a),
227 
 
228 
        .ADRB(addr_b),
229 
        .DB(di_b),
230 
        .WEB(we_b),
231 
        .OEB(1'b1),
232 
        .MEB(ce_b),
233 
        .CLKB(clk_b)
234 
);
235 
 
236 
`else
237 
 
238 
`ifdef OR1200_VIRTUALSILICON_STP_T1
239 
 
240 
//
241 
// Instantiation of ASIC memory:
242 
//
243 
// Virtual Silicon Two-port R/W SRAM Type 1
244 
//
245 
`ifdef UNUSED
246 
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
247 
`else
248 
vs_hdtp_64x32 vs_ssp(
249 
`endif
250 
        .P1CK(clk_a),
251 
        .P1CEN(~ce_a),
252 
        .P1WEN(1'b1),
253 
        .P1OEN(~oe_a),
254 
        .P1ADR({1'b0, addr_a}),
255 
        .P1DI(32'h0000_0000),
256 
        .P1DOUT(do_a),
257 
 
258 
        .P2CK(clk_b),
259 
        .P2CEN(~ce_b),
260 
        .P2WEN(~ce_b),
261 
        .P2OEN(1'b1),
262 
        .P2ADR({1'b0, addr_b}),
263 
        .P2DI(di_b),
264 
        .P2DOUT()
265 
);
266 
 
267 
`else
268 
 
269 
`ifdef OR1200_VIRTUALSILICON_STP_T2
270 
 
271 
//
272 
// Instantiation of ASIC memory:
273 
//
274 
// Virtual Silicon Two-port R/W SRAM Type 2
275 
//
276 
`ifdef UNUSED
277 
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
278 
`else
279 
vs_hdtp_32x32 vs_ssp(
280 
`endif
281 
        .RCK(clk_a),
282 
        .REN(~ce_a),
283 
        .OEN(~oe_a),
284 
        .RADR(addr_a),
285 
        .DOUT(do_a),
286 
 
287 
        .WCK(clk_b),
288 
        .WEN(~ce_b),
289 
        .WADR(addr_b),
290 
        .DI(di_b)
291 
);
292 
 
293 
`else
294 
 
295 
`ifdef OR1200_XILINX_RAM32X1D
296 
 
297 
//
298 
// Instantiation of FPGA memory:
299 
//
300 
// Virtex/Spartan2
301 
//
302 
 
303 
reg     [4:0]    addr_a_r;
304 
 
305 
always @(posedge clk_a or posedge rst_a)
306 
        if (rst_a)
307 
                addr_a_r <= #1 5'b00000;
308 
        else if (ce_a)
309 
                addr_a_r <= #1 addr_a;
310 
 
311 
//
312 
// Block 0
313 
//
314 
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
315 
        .DPO(do_a[7:0]),
316 
        .SPO(),
317 
        .A(addr_b),
318 
        .D(di_b[7:0]),
319 
        .DPRA(addr_a_r),
320 
        .WCLK(clk_b),
321 
        .WE(we_b)
322 
);
323 
 
324 
//
325 
// Block 1
326 
//
327 
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
328 
        .DPO(do_a[15:8]),
329 
        .SPO(),
330 
        .A(addr_b),
331 
        .D(di_b[15:8]),
332 
        .DPRA(addr_a_r),
333 
        .WCLK(clk_b),
334 
        .WE(we_b)
335 
);
336 
 
337 
 
338 
//
339 
// Block 2
340 
//
341 
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
342 
        .DPO(do_a[23:16]),
343 
        .SPO(),
344 
        .A(addr_b),
345 
        .D(di_b[23:16]),
346 
        .DPRA(addr_a_r),
347 
        .WCLK(clk_b),
348 
        .WE(we_b)
349 
);
350 
 
351 
//
352 
// Block 3
353 
//
354 
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
355 
        .DPO(do_a[31:24]),
356 
        .SPO(),
357 
        .A(addr_b),
358 
        .D(di_b[31:24]),
359 
        .DPRA(addr_a_r),
360 
        .WCLK(clk_b),
361 
        .WE(we_b)
362 
);
363 
 
364 
`else
365 
 
366 
`ifdef OR1200_XILINX_RAMB4
367 
 
368 
//
369 
// Instantiation of FPGA memory:
370 
//
371 
// Virtex/Spartan2
372 
//
373 
 
374 
//
375 
// Block 0
376 
//
377 
RAMB4_S16_S16 ramb4_s16_0(
378 
        .CLKA(clk_a),
379 
        .RSTA(rst_a),
380 
        .ADDRA({3'b000, addr_a}),
381 
        .DIA(16'h0000),
382 
        .ENA(ce_a),
383 
        .WEA(1'b0),
384 
        .DOA(do_a[15:0]),
385 
 
386 
        .CLKB(clk_b),
387 
        .RSTB(rst_b),
388 
        .ADDRB({3'b000, addr_b}),
389 
        .DIB(di_b[15:0]),
390 
        .ENB(ce_b),
391 
        .WEB(we_b),
392 
        .DOB()
393 
);
394 
 
395 
//
396 
// Block 1
397 
//
398 
RAMB4_S16_S16 ramb4_s16_1(
399 
        .CLKA(clk_a),
400 
        .RSTA(rst_a),
401 
        .ADDRA({3'b000, addr_a}),
402 
        .DIA(16'h0000),
403 
        .ENA(ce_a),
404 
        .WEA(1'b0),
405 
        .DOA(do_a[31:16]),
406 
 
407 
        .CLKB(clk_b),
408 
        .RSTB(rst_b),
409 
        .ADDRB({3'b000, addr_b}),
410 
        .DIB(di_b[31:16]),
411 
        .ENB(ce_b),
412 
        .WEB(we_b),
413 
        .DOB()
414 
);
415 
 
416 
`else
417 
 
418 
`ifdef OR1200_XILINX_RAMB16
419 
 
420 
//
421 
// Instantiation of FPGA memory:
422 
//
423 
// Virtex4/Spartan3E
424 
//
425 
// Added By Nir Mor
426 
//
427 
 
428 
RAMB16_S36_S36 ramb16_s36_s36(
429 
        .CLKA(clk_a),
430 
        .SSRA(rst_a),
431 
        .ADDRA({4'b0000, addr_a}),
432 
        .DIA(32'h00000000),
433 
        .DIPA(4'h0),
434 
        .ENA(ce_a),
435 
        .WEA(1'b0),
436 
        .DOA(do_a),
437 
        .DOPA(),
438 
 
439 
        .CLKB(clk_b),
440 
        .SSRB(rst_b),
441 
        .ADDRB({4'b0000, addr_b}),
442 
        .DIB(di_b),
443 
        .DIPB(4'h0),
444 
        .ENB(ce_b),
445 
        .WEB(we_b),
446 
        .DOB(),
447 
        .DOPB()
448 
);
449 
 
450 
`else
451 
 
452 
`ifdef OR1200_ALTERA_LPM_XXX
453 
 
454 
//
455 
// Instantiation of FPGA memory:
456 
//
457 
// Altera LPM
458 
//
459 
// Added By Jamil Khatib
460 
//
461 
altqpram altqpram_component (
462 
        .wraddress_a (addr_a),
463 
        .inclocken_a (ce_a),
464 
        .wraddress_b (addr_b),
465 
        .wren_a (we_a),
466 
        .inclocken_b (ce_b),
467 
        .wren_b (we_b),
468 
        .inaclr_a (rst_a),
469 
        .inaclr_b (rst_b),
470 
        .inclock_a (clk_a),
471 
        .inclock_b (clk_b),
472 
        .data_a (di_a),
473 
        .data_b (di_b),
474 
        .q_a (do_a),
475 
        .q_b (do_b)
476 
);
477 
 
478 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
479 
        altqpram_component.width_write_a = dw,
480 
        altqpram_component.widthad_write_a = aw,
481 
        altqpram_component.numwords_write_a = dw,
482 
        altqpram_component.width_read_a = dw,
483 
        altqpram_component.widthad_read_a = aw,
484 
        altqpram_component.numwords_read_a = dw,
485 
        altqpram_component.width_write_b = dw,
486 
        altqpram_component.widthad_write_b = aw,
487 
        altqpram_component.numwords_write_b = dw,
488 
        altqpram_component.width_read_b = dw,
489 
        altqpram_component.widthad_read_b = aw,
490 
        altqpram_component.numwords_read_b = dw,
491 
        altqpram_component.indata_reg_a = "INCLOCK_A",
492 
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
493 
        altqpram_component.outdata_reg_a = "INCLOCK_A",
494 
        altqpram_component.indata_reg_b = "INCLOCK_B",
495 
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
496 
        altqpram_component.outdata_reg_b = "INCLOCK_B",
497 
        altqpram_component.indata_aclr_a = "INACLR_A",
498 
        altqpram_component.wraddress_aclr_a = "INACLR_A",
499 
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
500 
        altqpram_component.outdata_aclr_a = "INACLR_A",
501 
        altqpram_component.indata_aclr_b = "NONE",
502 
        altqpram_component.wraddress_aclr_b = "NONE",
503 
        altqpram_component.wrcontrol_aclr_b = "NONE",
504 
        altqpram_component.outdata_aclr_b = "INACLR_B",
505 
        altqpram_component.lpm_hint = "USE_ESB=ON";
506 
        //examplar attribute altqpram_component NOOPT TRUE
507 
 
508 
`else
509 
 
510 
//
511 
// Generic double-port synchronous RAM model
512 
//
513 
 
514 
//
515 
// Generic RAM's registers and wires
516 
//
517 
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
518 
reg     [aw-1:0] addr_a_reg;             // RAM address registered
519 
 
520 
//
521 
// Data output drivers
522 
//
523 
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
524 
 
525 
//
526 
// RAM read
527 
//
528 
always @(posedge clk_a or posedge rst_a)
529 
        if (rst_a)
530 
                addr_a_reg <= #1 {aw{1'b0}};
531 
        else if (ce_a)
532 
                addr_a_reg <= #1 addr_a;
533 
 
534 
//
535 
// RAM write
536 
//
537 
always @(posedge clk_b)
538 
        if (ce_b && we_b)
539 
                mem[addr_b] <= #1 di_b;
540 
 
541 
`endif  // !OR1200_ALTERA_LPM
542 
`endif  // !OR1200_XILINX_RAMB16
543 
`endif  // !OR1200_XILINX_RAMB4
544 
`endif  // !OR1200_XILINX_RAM32X1D
545 
`endif  // !OR1200_VIRTUALSILICON_SSP_T1
546 
`endif  // !OR1200_VIRTUALSILICON_SSP_T2
547 
`endif  // !OR1200_VIRAGE_STP
548 
`endif  // !OR1200_AVANT_ATP
549 
`endif  // !OR1200_ARTISAN_SDP
550 
 
551 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.