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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 358

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Debug Unit                                         ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Basic OR1200 debug unit.                                    ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
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////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45 141 marcus.erl
// $Log: or1200_du.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Minor update: 
48
// Bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
//
56
// Debug unit
57
//
58
 
59
module or1200_du(
60
        // RISC Internal Interface
61
        clk, rst,
62
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
63
        dcpu_dat_dc, icpu_cycstb_i,
64
        ex_freeze, branch_op, ex_insn, id_pc,
65
        spr_dat_npc, rf_dataw,
66 141 marcus.erl
        du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
67
        du_read, du_write, du_except_stop, du_hwbkpt,
68 10 unneback
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
69
 
70
        // External Debug Interface
71
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
72
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
73
);
74
 
75
parameter dw = `OR1200_OPERAND_WIDTH;
76
parameter aw = `OR1200_OPERAND_WIDTH;
77
 
78
//
79
// I/O
80
//
81
 
82
//
83
// RISC Internal Interface
84
//
85
input                           clk;            // Clock
86
input                           rst;            // Reset
87
input                           dcpu_cycstb_i;  // LSU status
88
input                           dcpu_we_i;      // LSU status
89
input   [31:0]                   dcpu_adr_i;     // LSU addr
90
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
91
input   [31:0]                   dcpu_dat_dc;    // LSU load data
92
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
93
input                           ex_freeze;      // EX stage freeze
94
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
95
input   [dw-1:0]         ex_insn;        // EX insn
96
input   [31:0]                   id_pc;          // insn fetch EA
97
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
98
input   [31:0]                   rf_dataw;       // ALU result (for trace)
99
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
100 141 marcus.erl
output  [24: 0]                  du_dmr1;
101 10 unneback
output                          du_stall;       // Debug Unit Stall
102
output  [aw-1:0]         du_addr;        // Debug Unit Address
103
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
104
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
105
output                          du_read;        // Debug Unit Read Enable
106
output                          du_write;       // Debug Unit Write Enable
107 185 julius
input   [13:0]                   du_except_stop; // Exception masked by DSR
108 10 unneback
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
109
input                           spr_cs;         // SPR Chip Select
110
input                           spr_write;      // SPR Read/Write
111
input   [aw-1:0]         spr_addr;       // SPR Address
112
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
113
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
114
 
115
//
116
// External Debug Interface
117
//
118
input                   dbg_stall_i;    // External Stall Input
119
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
120
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
121
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
122
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
123
output                  dbg_bp_o;       // Breakpoint Output
124
input                   dbg_stb_i;      // External Address/Data Strobe
125
input                   dbg_we_i;       // External Write Enable
126
input   [aw-1:0] dbg_adr_i;      // External Address Input
127
input   [dw-1:0] dbg_dat_i;      // External Data Input
128
output  [dw-1:0] dbg_dat_o;      // External Data Output
129
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
130 141 marcus.erl
reg     [dw-1:0] dbg_dat_o;      // External Data Output
131
reg                     dbg_ack_o;      // External Data Acknowledge (not WB compatible)
132 10 unneback
 
133
 
134
//
135
// Some connections go directly from the CPU through DU to Debug I/F
136
//
137
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
138
assign dbg_lss_o = 4'b0000;
139
 
140
reg     [1:0]                    dbg_is_o;
141
//
142
// Show insn activity (temp, must be removed)
143
//
144 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
145
        if (rst == `OR1200_RST_VALUE)
146 258 julius
                dbg_is_o <=  2'b00;
147 141 marcus.erl
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
148 258 julius
                dbg_is_o <=  ~dbg_is_o;
149 10 unneback
`ifdef UNUSED
150
assign dbg_is_o = 2'b00;
151
`endif
152
`else
153
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
154
assign dbg_is_o = {1'b0, icpu_cycstb_i};
155
`endif
156
assign dbg_wp_o = 11'b000_0000_0000;
157
 
158
//
159
// Some connections go directly from Debug I/F through DU to the CPU
160
//
161
assign du_stall = dbg_stall_i;
162
assign du_addr = dbg_adr_i;
163
assign du_dat_o = dbg_dat_i;
164
assign du_read = dbg_stb_i && !dbg_we_i;
165
assign du_write = dbg_stb_i && dbg_we_i;
166
 
167 141 marcus.erl
reg                             dbg_ack;
168 10 unneback
//
169
// Generate acknowledge -- just delay stb signal
170
//
171 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
172
        if (rst == `OR1200_RST_VALUE) begin
173 258 julius
                dbg_ack   <=  1'b0;
174
                dbg_ack_o <=  1'b0;
175 141 marcus.erl
        end
176
        else begin
177 258 julius
                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i 
178
                dbg_ack_o <=  dbg_ack & dbg_stb_i;      // valid when dbg_dat_o 
179 141 marcus.erl
        end
180
end
181 10 unneback
 
182 141 marcus.erl
// 
183
// Register data output
184
//
185
always @(posedge clk)
186 258 julius
    dbg_dat_o <=  du_dat_i;
187 141 marcus.erl
 
188 10 unneback
`ifdef OR1200_DU_IMPLEMENTED
189
 
190
//
191
// Debug Mode Register 1
192
//
193
`ifdef OR1200_DU_DMR1
194
reg     [24:0]                   dmr1;           // DMR1 implemented
195
`else
196
wire    [24:0]                   dmr1;           // DMR1 not implemented
197
`endif
198 141 marcus.erl
assign du_dmr1 = dmr1;
199 10 unneback
 
200
//
201
// Debug Mode Register 2
202
//
203
`ifdef OR1200_DU_DMR2
204
reg     [23:0]                   dmr2;           // DMR2 implemented
205
`else
206
wire    [23:0]                   dmr2;           // DMR2 not implemented
207
`endif
208
 
209
//
210
// Debug Stop Register
211
//
212
`ifdef OR1200_DU_DSR
213
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
214
`else
215
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
216
`endif
217
 
218
//
219
// Debug Reason Register
220
//
221
`ifdef OR1200_DU_DRR
222
reg     [13:0]                   drr;            // DRR implemented
223
`else
224
wire    [13:0]                   drr;            // DRR not implemented
225
`endif
226
 
227
//
228
// Debug Value Register N
229
//
230
`ifdef OR1200_DU_DVR0
231
reg     [31:0]                   dvr0;
232
`else
233
wire    [31:0]                   dvr0;
234
`endif
235
 
236
//
237
// Debug Value Register N
238
//
239
`ifdef OR1200_DU_DVR1
240
reg     [31:0]                   dvr1;
241
`else
242
wire    [31:0]                   dvr1;
243
`endif
244
 
245
//
246
// Debug Value Register N
247
//
248
`ifdef OR1200_DU_DVR2
249
reg     [31:0]                   dvr2;
250
`else
251
wire    [31:0]                   dvr2;
252
`endif
253
 
254
//
255
// Debug Value Register N
256
//
257
`ifdef OR1200_DU_DVR3
258
reg     [31:0]                   dvr3;
259
`else
260
wire    [31:0]                   dvr3;
261
`endif
262
 
263
//
264
// Debug Value Register N
265
//
266
`ifdef OR1200_DU_DVR4
267
reg     [31:0]                   dvr4;
268
`else
269
wire    [31:0]                   dvr4;
270
`endif
271
 
272
//
273
// Debug Value Register N
274
//
275
`ifdef OR1200_DU_DVR5
276
reg     [31:0]                   dvr5;
277
`else
278
wire    [31:0]                   dvr5;
279
`endif
280
 
281
//
282
// Debug Value Register N
283
//
284
`ifdef OR1200_DU_DVR6
285
reg     [31:0]                   dvr6;
286
`else
287
wire    [31:0]                   dvr6;
288
`endif
289
 
290
//
291
// Debug Value Register N
292
//
293
`ifdef OR1200_DU_DVR7
294
reg     [31:0]                   dvr7;
295
`else
296
wire    [31:0]                   dvr7;
297
`endif
298
 
299
//
300
// Debug Control Register N
301
//
302
`ifdef OR1200_DU_DCR0
303
reg     [7:0]                    dcr0;
304
`else
305
wire    [7:0]                    dcr0;
306
`endif
307
 
308
//
309
// Debug Control Register N
310
//
311
`ifdef OR1200_DU_DCR1
312
reg     [7:0]                    dcr1;
313
`else
314
wire    [7:0]                    dcr1;
315
`endif
316
 
317
//
318
// Debug Control Register N
319
//
320
`ifdef OR1200_DU_DCR2
321
reg     [7:0]                    dcr2;
322
`else
323
wire    [7:0]                    dcr2;
324
`endif
325
 
326
//
327
// Debug Control Register N
328
//
329
`ifdef OR1200_DU_DCR3
330
reg     [7:0]                    dcr3;
331
`else
332
wire    [7:0]                    dcr3;
333
`endif
334
 
335
//
336
// Debug Control Register N
337
//
338
`ifdef OR1200_DU_DCR4
339
reg     [7:0]                    dcr4;
340
`else
341
wire    [7:0]                    dcr4;
342
`endif
343
 
344
//
345
// Debug Control Register N
346
//
347
`ifdef OR1200_DU_DCR5
348
reg     [7:0]                    dcr5;
349
`else
350
wire    [7:0]                    dcr5;
351
`endif
352
 
353
//
354
// Debug Control Register N
355
//
356
`ifdef OR1200_DU_DCR6
357
reg     [7:0]                    dcr6;
358
`else
359
wire    [7:0]                    dcr6;
360
`endif
361
 
362
//
363
// Debug Control Register N
364
//
365
`ifdef OR1200_DU_DCR7
366
reg     [7:0]                    dcr7;
367
`else
368
wire    [7:0]                    dcr7;
369
`endif
370
 
371
//
372
// Debug Watchpoint Counter Register 0
373
//
374
`ifdef OR1200_DU_DWCR0
375
reg     [31:0]                   dwcr0;
376
`else
377
wire    [31:0]                   dwcr0;
378
`endif
379
 
380
//
381
// Debug Watchpoint Counter Register 1
382
//
383
`ifdef OR1200_DU_DWCR1
384
reg     [31:0]                   dwcr1;
385
`else
386
wire    [31:0]                   dwcr1;
387
`endif
388
 
389
//
390
// Internal wires
391
//
392
wire                            dmr1_sel;       // DMR1 select
393
wire                            dmr2_sel;       // DMR2 select
394
wire                            dsr_sel;        // DSR select
395
wire                            drr_sel;        // DRR select
396
wire                            dvr0_sel,
397
                                dvr1_sel,
398
                                dvr2_sel,
399
                                dvr3_sel,
400
                                dvr4_sel,
401
                                dvr5_sel,
402
                                dvr6_sel,
403
                                dvr7_sel;       // DVR selects
404
wire                            dcr0_sel,
405
                                dcr1_sel,
406
                                dcr2_sel,
407
                                dcr3_sel,
408
                                dcr4_sel,
409
                                dcr5_sel,
410
                                dcr6_sel,
411
                                dcr7_sel;       // DCR selects
412
wire                            dwcr0_sel,
413
                                dwcr1_sel;      // DWCR selects
414
reg                             dbg_bp_r;
415
`ifdef OR1200_DU_HWBKPTS
416
reg     [31:0]                   match_cond0_ct;
417
reg     [31:0]                   match_cond1_ct;
418
reg     [31:0]                   match_cond2_ct;
419
reg     [31:0]                   match_cond3_ct;
420
reg     [31:0]                   match_cond4_ct;
421
reg     [31:0]                   match_cond5_ct;
422
reg     [31:0]                   match_cond6_ct;
423
reg     [31:0]                   match_cond7_ct;
424
reg                             match_cond0_stb;
425
reg                             match_cond1_stb;
426
reg                             match_cond2_stb;
427
reg                             match_cond3_stb;
428
reg                             match_cond4_stb;
429
reg                             match_cond5_stb;
430
reg                             match_cond6_stb;
431
reg                             match_cond7_stb;
432
reg                             match0;
433
reg                             match1;
434
reg                             match2;
435
reg                             match3;
436
reg                             match4;
437
reg                             match5;
438
reg                             match6;
439
reg                             match7;
440
reg                             wpcntr0_match;
441
reg                             wpcntr1_match;
442
reg                             incr_wpcntr0;
443
reg                             incr_wpcntr1;
444
reg     [10:0]                   wp;
445
`endif
446
wire                            du_hwbkpt;
447 141 marcus.erl
reg                             du_hwbkpt_hold;
448 10 unneback
`ifdef OR1200_DU_READREGS
449
reg     [31:0]                   spr_dat_o;
450
`endif
451
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
452
`ifdef OR1200_DU_TB_IMPLEMENTED
453
wire                            tb_enw;
454
reg     [7:0]                    tb_wadr;
455
reg [31:0]                       tb_timstmp;
456
`endif
457
wire    [31:0]                   tbia_dat_o;
458
wire    [31:0]                   tbim_dat_o;
459
wire    [31:0]                   tbar_dat_o;
460
wire    [31:0]                   tbts_dat_o;
461
 
462
//
463
// DU registers address decoder
464
//
465
`ifdef OR1200_DU_DMR1
466
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
467
`endif
468
`ifdef OR1200_DU_DMR2
469
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
470
`endif
471
`ifdef OR1200_DU_DSR
472
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
473
`endif
474
`ifdef OR1200_DU_DRR
475
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
476
`endif
477
`ifdef OR1200_DU_DVR0
478
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
479
`endif
480
`ifdef OR1200_DU_DVR1
481
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
482
`endif
483
`ifdef OR1200_DU_DVR2
484
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
485
`endif
486
`ifdef OR1200_DU_DVR3
487
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
488
`endif
489
`ifdef OR1200_DU_DVR4
490
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
491
`endif
492
`ifdef OR1200_DU_DVR5
493
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
494
`endif
495
`ifdef OR1200_DU_DVR6
496
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
497
`endif
498
`ifdef OR1200_DU_DVR7
499
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
500
`endif
501
`ifdef OR1200_DU_DCR0
502
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
503
`endif
504
`ifdef OR1200_DU_DCR1
505
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
506
`endif
507
`ifdef OR1200_DU_DCR2
508
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
509
`endif
510
`ifdef OR1200_DU_DCR3
511
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
512
`endif
513
`ifdef OR1200_DU_DCR4
514
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
515
`endif
516
`ifdef OR1200_DU_DCR5
517
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
518
`endif
519
`ifdef OR1200_DU_DCR6
520
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
521
`endif
522
`ifdef OR1200_DU_DCR7
523
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
524
`endif
525
`ifdef OR1200_DU_DWCR0
526
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
527
`endif
528
`ifdef OR1200_DU_DWCR1
529
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
530
`endif
531
 
532
//
533
// Decode started exception
534
//
535 185 julius
// du_except_stop comes from or1200_except
536
//   
537 141 marcus.erl
always @(du_except_stop) begin
538 185 julius
        except_stop = 14'b00_0000_0000_0000;
539 141 marcus.erl
        casex (du_except_stop)
540 185 julius
                14'b1x_xxxx_xxxx_xxxx:
541 10 unneback
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
542 185 julius
                14'b01_xxxx_xxxx_xxxx: begin
543 10 unneback
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
544
                end
545 185 julius
                14'b00_1xxx_xxxx_xxxx: begin
546 10 unneback
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
547
                end
548 185 julius
                14'b00_01xx_xxxx_xxxx:
549 10 unneback
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
550 185 julius
                14'b00_001x_xxxx_xxxx: begin
551 10 unneback
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
552
                end
553 185 julius
                14'b00_0001_xxxx_xxxx:
554 10 unneback
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
555 185 julius
                14'b00_0000_1xxx_xxxx: begin
556 10 unneback
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
557
                end
558 185 julius
                14'b00_0000_01xx_xxxx: begin
559 10 unneback
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
560
                end
561 185 julius
                14'b00_0000_001x_xxxx:
562 10 unneback
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
563 185 julius
                14'b00_0000_0001_xxxx:
564 10 unneback
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
565 185 julius
                14'b00_0000_0000_1xxx: begin
566 10 unneback
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
567
                end
568 185 julius
                14'b00_0000_0000_01xx: begin
569 10 unneback
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
570
                end
571 185 julius
                14'b00_0000_0000_001x: begin
572
                        except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
573
                end
574
                14'b00_0000_0000_0001:
575 10 unneback
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
576
                default:
577 185 julius
                        except_stop = 14'b00_0000_0000_0000;
578 10 unneback
        endcase
579
end
580
 
581
//
582
// dbg_bp_o is registered
583
//
584
assign dbg_bp_o = dbg_bp_r;
585
 
586
//
587
// Breakpoint activation register
588
//
589 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
590
        if (rst == `OR1200_RST_VALUE)
591 258 julius
                dbg_bp_r <=  1'b0;
592 10 unneback
        else if (!ex_freeze)
593 258 julius
                dbg_bp_r <=  |except_stop
594 10 unneback
`ifdef OR1200_DU_DMR1_ST
595
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
596
`endif
597
`ifdef OR1200_DU_DMR1_BT
598 141 marcus.erl
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
599 10 unneback
`endif
600
                        ;
601
        else
602 258 julius
                dbg_bp_r <=  |except_stop;
603 10 unneback
 
604
//
605
// Write to DMR1
606
//
607
`ifdef OR1200_DU_DMR1
608 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
609
        if (rst == `OR1200_RST_VALUE)
610 10 unneback
                dmr1 <= 25'h000_0000;
611
        else if (dmr1_sel && spr_write)
612
`ifdef OR1200_DU_HWBKPTS
613 258 julius
                dmr1 <=  spr_dat_i[24:0];
614 10 unneback
`else
615 258 julius
                dmr1 <=  {1'b0, spr_dat_i[23:22], 22'h00_0000};
616 10 unneback
`endif
617
`else
618
assign dmr1 = 25'h000_0000;
619
`endif
620
 
621
//
622
// Write to DMR2
623
//
624
`ifdef OR1200_DU_DMR2
625 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
626
        if (rst == `OR1200_RST_VALUE)
627 10 unneback
                dmr2 <= 24'h00_0000;
628
        else if (dmr2_sel && spr_write)
629 258 julius
                dmr2 <=  spr_dat_i[23:0];
630 10 unneback
`else
631
assign dmr2 = 24'h00_0000;
632
`endif
633
 
634
//
635
// Write to DSR
636
//
637
`ifdef OR1200_DU_DSR
638 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
639
        if (rst == `OR1200_RST_VALUE)
640 10 unneback
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
641
        else if (dsr_sel && spr_write)
642 258 julius
                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
643 10 unneback
`else
644
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
645
`endif
646
 
647
//
648
// Write to DRR
649
//
650
`ifdef OR1200_DU_DRR
651 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
652
        if (rst == `OR1200_RST_VALUE)
653 10 unneback
                drr <= 14'b0;
654
        else if (drr_sel && spr_write)
655 258 julius
                drr <=  spr_dat_i[13:0];
656 10 unneback
        else
657 258 julius
                drr <=  drr | except_stop;
658 10 unneback
`else
659
assign drr = 14'b0;
660
`endif
661
 
662
//
663
// Write to DVR0
664
//
665
`ifdef OR1200_DU_DVR0
666 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
667
        if (rst == `OR1200_RST_VALUE)
668 10 unneback
                dvr0 <= 32'h0000_0000;
669
        else if (dvr0_sel && spr_write)
670 258 julius
                dvr0 <=  spr_dat_i[31:0];
671 10 unneback
`else
672
assign dvr0 = 32'h0000_0000;
673
`endif
674
 
675
//
676
// Write to DVR1
677
//
678
`ifdef OR1200_DU_DVR1
679 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
680
        if (rst == `OR1200_RST_VALUE)
681 10 unneback
                dvr1 <= 32'h0000_0000;
682
        else if (dvr1_sel && spr_write)
683 258 julius
                dvr1 <=  spr_dat_i[31:0];
684 10 unneback
`else
685
assign dvr1 = 32'h0000_0000;
686
`endif
687
 
688
//
689
// Write to DVR2
690
//
691
`ifdef OR1200_DU_DVR2
692 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
693
        if (rst == `OR1200_RST_VALUE)
694 10 unneback
                dvr2 <= 32'h0000_0000;
695
        else if (dvr2_sel && spr_write)
696 258 julius
                dvr2 <=  spr_dat_i[31:0];
697 10 unneback
`else
698
assign dvr2 = 32'h0000_0000;
699
`endif
700
 
701
//
702
// Write to DVR3
703
//
704
`ifdef OR1200_DU_DVR3
705 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
706
        if (rst == `OR1200_RST_VALUE)
707 10 unneback
                dvr3 <= 32'h0000_0000;
708
        else if (dvr3_sel && spr_write)
709 258 julius
                dvr3 <=  spr_dat_i[31:0];
710 10 unneback
`else
711
assign dvr3 = 32'h0000_0000;
712
`endif
713
 
714
//
715
// Write to DVR4
716
//
717
`ifdef OR1200_DU_DVR4
718 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
719
        if (rst == `OR1200_RST_VALUE)
720 10 unneback
                dvr4 <= 32'h0000_0000;
721
        else if (dvr4_sel && spr_write)
722 258 julius
                dvr4 <=  spr_dat_i[31:0];
723 10 unneback
`else
724
assign dvr4 = 32'h0000_0000;
725
`endif
726
 
727
//
728
// Write to DVR5
729
//
730
`ifdef OR1200_DU_DVR5
731 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
732
        if (rst == `OR1200_RST_VALUE)
733 10 unneback
                dvr5 <= 32'h0000_0000;
734
        else if (dvr5_sel && spr_write)
735 258 julius
                dvr5 <=  spr_dat_i[31:0];
736 10 unneback
`else
737
assign dvr5 = 32'h0000_0000;
738
`endif
739
 
740
//
741
// Write to DVR6
742
//
743
`ifdef OR1200_DU_DVR6
744 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
745
        if (rst == `OR1200_RST_VALUE)
746 10 unneback
                dvr6 <= 32'h0000_0000;
747
        else if (dvr6_sel && spr_write)
748 258 julius
                dvr6 <=  spr_dat_i[31:0];
749 10 unneback
`else
750
assign dvr6 = 32'h0000_0000;
751
`endif
752
 
753
//
754
// Write to DVR7
755
//
756
`ifdef OR1200_DU_DVR7
757 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
758
        if (rst == `OR1200_RST_VALUE)
759 10 unneback
                dvr7 <= 32'h0000_0000;
760
        else if (dvr7_sel && spr_write)
761 258 julius
                dvr7 <=  spr_dat_i[31:0];
762 10 unneback
`else
763
assign dvr7 = 32'h0000_0000;
764
`endif
765
 
766
//
767
// Write to DCR0
768
//
769
`ifdef OR1200_DU_DCR0
770 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
771
        if (rst == `OR1200_RST_VALUE)
772 10 unneback
                dcr0 <= 8'h00;
773
        else if (dcr0_sel && spr_write)
774 258 julius
                dcr0 <=  spr_dat_i[7:0];
775 10 unneback
`else
776
assign dcr0 = 8'h00;
777
`endif
778
 
779
//
780
// Write to DCR1
781
//
782
`ifdef OR1200_DU_DCR1
783 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
784
        if (rst == `OR1200_RST_VALUE)
785 10 unneback
                dcr1 <= 8'h00;
786
        else if (dcr1_sel && spr_write)
787 258 julius
                dcr1 <=  spr_dat_i[7:0];
788 10 unneback
`else
789
assign dcr1 = 8'h00;
790
`endif
791
 
792
//
793
// Write to DCR2
794
//
795
`ifdef OR1200_DU_DCR2
796 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
797
        if (rst == `OR1200_RST_VALUE)
798 10 unneback
                dcr2 <= 8'h00;
799
        else if (dcr2_sel && spr_write)
800 258 julius
                dcr2 <=  spr_dat_i[7:0];
801 10 unneback
`else
802
assign dcr2 = 8'h00;
803
`endif
804
 
805
//
806
// Write to DCR3
807
//
808
`ifdef OR1200_DU_DCR3
809 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
810
        if (rst == `OR1200_RST_VALUE)
811 10 unneback
                dcr3 <= 8'h00;
812
        else if (dcr3_sel && spr_write)
813 258 julius
                dcr3 <=  spr_dat_i[7:0];
814 10 unneback
`else
815
assign dcr3 = 8'h00;
816
`endif
817
 
818
//
819
// Write to DCR4
820
//
821
`ifdef OR1200_DU_DCR4
822 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
823
        if (rst == `OR1200_RST_VALUE)
824 10 unneback
                dcr4 <= 8'h00;
825
        else if (dcr4_sel && spr_write)
826 258 julius
                dcr4 <=  spr_dat_i[7:0];
827 10 unneback
`else
828
assign dcr4 = 8'h00;
829
`endif
830
 
831
//
832
// Write to DCR5
833
//
834
`ifdef OR1200_DU_DCR5
835 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
836
        if (rst == `OR1200_RST_VALUE)
837 10 unneback
                dcr5 <= 8'h00;
838
        else if (dcr5_sel && spr_write)
839 258 julius
                dcr5 <=  spr_dat_i[7:0];
840 10 unneback
`else
841
assign dcr5 = 8'h00;
842
`endif
843
 
844
//
845
// Write to DCR6
846
//
847
`ifdef OR1200_DU_DCR6
848 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
849
        if (rst == `OR1200_RST_VALUE)
850 10 unneback
                dcr6 <= 8'h00;
851
        else if (dcr6_sel && spr_write)
852 258 julius
                dcr6 <=  spr_dat_i[7:0];
853 10 unneback
`else
854
assign dcr6 = 8'h00;
855
`endif
856
 
857
//
858
// Write to DCR7
859
//
860
`ifdef OR1200_DU_DCR7
861 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
862
        if (rst == `OR1200_RST_VALUE)
863 10 unneback
                dcr7 <= 8'h00;
864
        else if (dcr7_sel && spr_write)
865 258 julius
                dcr7 <=  spr_dat_i[7:0];
866 10 unneback
`else
867
assign dcr7 = 8'h00;
868
`endif
869
 
870
//
871
// Write to DWCR0
872
//
873
`ifdef OR1200_DU_DWCR0
874 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
875
        if (rst == `OR1200_RST_VALUE)
876 10 unneback
                dwcr0 <= 32'h0000_0000;
877
        else if (dwcr0_sel && spr_write)
878 258 julius
                dwcr0 <=  spr_dat_i[31:0];
879 10 unneback
        else if (incr_wpcntr0)
880 258 julius
                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
881 10 unneback
`else
882
assign dwcr0 = 32'h0000_0000;
883
`endif
884
 
885
//
886
// Write to DWCR1
887
//
888
`ifdef OR1200_DU_DWCR1
889 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
890
        if (rst == `OR1200_RST_VALUE)
891 10 unneback
                dwcr1 <= 32'h0000_0000;
892
        else if (dwcr1_sel && spr_write)
893 258 julius
                dwcr1 <=  spr_dat_i[31:0];
894 10 unneback
        else if (incr_wpcntr1)
895 258 julius
                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
896 10 unneback
`else
897
assign dwcr1 = 32'h0000_0000;
898
`endif
899
 
900
//
901
// Read DU registers
902
//
903
`ifdef OR1200_DU_READREGS
904
always @(spr_addr or dsr or drr or dmr1 or dmr2
905
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
906
        or dvr5 or dvr6 or dvr7
907
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
908
        or dcr5 or dcr6 or dcr7
909
        or dwcr0 or dwcr1
910
`ifdef OR1200_DU_TB_IMPLEMENTED
911
        or tb_wadr or tbia_dat_o or tbim_dat_o
912
        or tbar_dat_o or tbts_dat_o
913
`endif
914
        )
915
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
916
`ifdef OR1200_DU_DVR0
917
                `OR1200_DU_DVR0:
918
                        spr_dat_o = dvr0;
919
`endif
920
`ifdef OR1200_DU_DVR1
921
                `OR1200_DU_DVR1:
922
                        spr_dat_o = dvr1;
923
`endif
924
`ifdef OR1200_DU_DVR2
925
                `OR1200_DU_DVR2:
926
                        spr_dat_o = dvr2;
927
`endif
928
`ifdef OR1200_DU_DVR3
929
                `OR1200_DU_DVR3:
930
                        spr_dat_o = dvr3;
931
`endif
932
`ifdef OR1200_DU_DVR4
933
                `OR1200_DU_DVR4:
934
                        spr_dat_o = dvr4;
935
`endif
936
`ifdef OR1200_DU_DVR5
937
                `OR1200_DU_DVR5:
938
                        spr_dat_o = dvr5;
939
`endif
940
`ifdef OR1200_DU_DVR6
941
                `OR1200_DU_DVR6:
942
                        spr_dat_o = dvr6;
943
`endif
944
`ifdef OR1200_DU_DVR7
945
                `OR1200_DU_DVR7:
946
                        spr_dat_o = dvr7;
947
`endif
948
`ifdef OR1200_DU_DCR0
949
                `OR1200_DU_DCR0:
950
                        spr_dat_o = {24'h00_0000, dcr0};
951
`endif
952
`ifdef OR1200_DU_DCR1
953
                `OR1200_DU_DCR1:
954
                        spr_dat_o = {24'h00_0000, dcr1};
955
`endif
956
`ifdef OR1200_DU_DCR2
957
                `OR1200_DU_DCR2:
958
                        spr_dat_o = {24'h00_0000, dcr2};
959
`endif
960
`ifdef OR1200_DU_DCR3
961
                `OR1200_DU_DCR3:
962
                        spr_dat_o = {24'h00_0000, dcr3};
963
`endif
964
`ifdef OR1200_DU_DCR4
965
                `OR1200_DU_DCR4:
966
                        spr_dat_o = {24'h00_0000, dcr4};
967
`endif
968
`ifdef OR1200_DU_DCR5
969
                `OR1200_DU_DCR5:
970
                        spr_dat_o = {24'h00_0000, dcr5};
971
`endif
972
`ifdef OR1200_DU_DCR6
973
                `OR1200_DU_DCR6:
974
                        spr_dat_o = {24'h00_0000, dcr6};
975
`endif
976
`ifdef OR1200_DU_DCR7
977
                `OR1200_DU_DCR7:
978
                        spr_dat_o = {24'h00_0000, dcr7};
979
`endif
980
`ifdef OR1200_DU_DMR1
981
                `OR1200_DU_DMR1:
982
                        spr_dat_o = {7'h00, dmr1};
983
`endif
984
`ifdef OR1200_DU_DMR2
985
                `OR1200_DU_DMR2:
986
                        spr_dat_o = {8'h00, dmr2};
987
`endif
988
`ifdef OR1200_DU_DWCR0
989
                `OR1200_DU_DWCR0:
990
                        spr_dat_o = dwcr0;
991
`endif
992
`ifdef OR1200_DU_DWCR1
993
                `OR1200_DU_DWCR1:
994
                        spr_dat_o = dwcr1;
995
`endif
996
`ifdef OR1200_DU_DSR
997
                `OR1200_DU_DSR:
998
                        spr_dat_o = {18'b0, dsr};
999
`endif
1000
`ifdef OR1200_DU_DRR
1001
                `OR1200_DU_DRR:
1002
                        spr_dat_o = {18'b0, drr};
1003
`endif
1004
`ifdef OR1200_DU_TB_IMPLEMENTED
1005
                `OR1200_DU_TBADR:
1006
                        spr_dat_o = {24'h000000, tb_wadr};
1007
                `OR1200_DU_TBIA:
1008
                        spr_dat_o = tbia_dat_o;
1009
                `OR1200_DU_TBIM:
1010
                        spr_dat_o = tbim_dat_o;
1011
                `OR1200_DU_TBAR:
1012
                        spr_dat_o = tbar_dat_o;
1013
                `OR1200_DU_TBTS:
1014
                        spr_dat_o = tbts_dat_o;
1015
`endif
1016
                default:
1017
                        spr_dat_o = 32'h0000_0000;
1018
        endcase
1019
`endif
1020
 
1021
//
1022
// DSR alias
1023
//
1024
assign du_dsr = dsr;
1025
 
1026
`ifdef OR1200_DU_HWBKPTS
1027
 
1028
//
1029
// Compare To What (Match Condition 0)
1030
//
1031
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1032
        or dcpu_dat_lsu or dcpu_we_i)
1033
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1034
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1035
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1036
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1037
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1038
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1039
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1040
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1041
        endcase
1042
 
1043
//
1044
// When To Compare (Match Condition 0)
1045
//
1046
always @(dcr0 or dcpu_cycstb_i)
1047
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1048
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1049
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1050
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1051
        endcase
1052
 
1053
//
1054
// Match Condition 0
1055
//
1056
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1057
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1058
                4'b0_xxx,
1059
                4'b1_000,
1060
                4'b1_111: match0 = 1'b0;
1061
                4'b1_001: match0 =
1062 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
1063
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1064 10 unneback
                4'b1_010: match0 =
1065 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
1066
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1067 10 unneback
                4'b1_011: match0 =
1068 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
1069
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1070 10 unneback
                4'b1_100: match0 =
1071 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
1072
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1073 10 unneback
                4'b1_101: match0 =
1074 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
1075
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1076 10 unneback
                4'b1_110: match0 =
1077 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
1078
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1079 10 unneback
        endcase
1080
 
1081
//
1082
// Watchpoint 0
1083
//
1084
always @(dmr1 or match0)
1085
        case (dmr1[`OR1200_DU_DMR1_CW0])
1086
                2'b00: wp[0] = match0;
1087
                2'b01: wp[0] = match0;
1088
                2'b10: wp[0] = match0;
1089
                2'b11: wp[0] = 1'b0;
1090
        endcase
1091
 
1092
//
1093
// Compare To What (Match Condition 1)
1094
//
1095
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1096
        or dcpu_dat_lsu or dcpu_we_i)
1097
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1098
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1099
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1100
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1101
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1102
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1103
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1104
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1105
        endcase
1106
 
1107
//
1108
// When To Compare (Match Condition 1)
1109
//
1110
always @(dcr1 or dcpu_cycstb_i)
1111
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1112
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1113
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1114
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1115
        endcase
1116
 
1117
//
1118
// Match Condition 1
1119
//
1120
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1121
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1122
                4'b0_xxx,
1123
                4'b1_000,
1124
                4'b1_111: match1 = 1'b0;
1125
                4'b1_001: match1 =
1126 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
1127
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1128 10 unneback
                4'b1_010: match1 =
1129 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
1130
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1131 10 unneback
                4'b1_011: match1 =
1132 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
1133
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1134 10 unneback
                4'b1_100: match1 =
1135 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
1136
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1137 10 unneback
                4'b1_101: match1 =
1138 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
1139
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1140 10 unneback
                4'b1_110: match1 =
1141 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
1142
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1143 10 unneback
        endcase
1144
 
1145
//
1146
// Watchpoint 1
1147
//
1148
always @(dmr1 or match1 or wp)
1149
        case (dmr1[`OR1200_DU_DMR1_CW1])
1150
                2'b00: wp[1] = match1;
1151
                2'b01: wp[1] = match1 & wp[0];
1152
                2'b10: wp[1] = match1 | wp[0];
1153
                2'b11: wp[1] = 1'b0;
1154
        endcase
1155
 
1156
//
1157
// Compare To What (Match Condition 2)
1158
//
1159
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1160
        or dcpu_dat_lsu or dcpu_we_i)
1161
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1162
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1163
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1164
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1165
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1166
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1167
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1168
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1169
        endcase
1170
 
1171
//
1172
// When To Compare (Match Condition 2)
1173
//
1174
always @(dcr2 or dcpu_cycstb_i)
1175
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1176
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1177
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1178
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1179
        endcase
1180
 
1181
//
1182
// Match Condition 2
1183
//
1184
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1185
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1186
                4'b0_xxx,
1187
                4'b1_000,
1188
                4'b1_111: match2 = 1'b0;
1189
                4'b1_001: match2 =
1190 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
1191
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1192 10 unneback
                4'b1_010: match2 =
1193 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
1194
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1195 10 unneback
                4'b1_011: match2 =
1196 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
1197
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1198 10 unneback
                4'b1_100: match2 =
1199 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
1200
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1201 10 unneback
                4'b1_101: match2 =
1202 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
1203
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1204 10 unneback
                4'b1_110: match2 =
1205 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
1206
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1207 10 unneback
        endcase
1208
 
1209
//
1210
// Watchpoint 2
1211
//
1212
always @(dmr1 or match2 or wp)
1213
        case (dmr1[`OR1200_DU_DMR1_CW2])
1214
                2'b00: wp[2] = match2;
1215
                2'b01: wp[2] = match2 & wp[1];
1216
                2'b10: wp[2] = match2 | wp[1];
1217
                2'b11: wp[2] = 1'b0;
1218
        endcase
1219
 
1220
//
1221
// Compare To What (Match Condition 3)
1222
//
1223
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1224
        or dcpu_dat_lsu or dcpu_we_i)
1225
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1226
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1227
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1228
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1229
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1230
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1231
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1232
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1233
        endcase
1234
 
1235
//
1236
// When To Compare (Match Condition 3)
1237
//
1238
always @(dcr3 or dcpu_cycstb_i)
1239
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1240
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1241
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1242
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1243
        endcase
1244
 
1245
//
1246
// Match Condition 3
1247
//
1248
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1249
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1250
                4'b0_xxx,
1251
                4'b1_000,
1252
                4'b1_111: match3 = 1'b0;
1253
                4'b1_001: match3 =
1254 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
1255
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1256 10 unneback
                4'b1_010: match3 =
1257 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
1258
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1259 10 unneback
                4'b1_011: match3 =
1260 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
1261
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1262 10 unneback
                4'b1_100: match3 =
1263 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
1264
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1265 10 unneback
                4'b1_101: match3 =
1266 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
1267
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1268 10 unneback
                4'b1_110: match3 =
1269 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
1270
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1271 10 unneback
        endcase
1272
 
1273
//
1274
// Watchpoint 3
1275
//
1276
always @(dmr1 or match3 or wp)
1277
        case (dmr1[`OR1200_DU_DMR1_CW3])
1278
                2'b00: wp[3] = match3;
1279
                2'b01: wp[3] = match3 & wp[2];
1280
                2'b10: wp[3] = match3 | wp[2];
1281
                2'b11: wp[3] = 1'b0;
1282
        endcase
1283
 
1284
//
1285
// Compare To What (Match Condition 4)
1286
//
1287
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1288
        or dcpu_dat_lsu or dcpu_we_i)
1289
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1290
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1291
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1292
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1293
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1294
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1295
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1296
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1297
        endcase
1298
 
1299
//
1300
// When To Compare (Match Condition 4)
1301
//
1302
always @(dcr4 or dcpu_cycstb_i)
1303
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1304
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1305
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1306
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1307
        endcase
1308
 
1309
//
1310
// Match Condition 4
1311
//
1312
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1313
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1314
                4'b0_xxx,
1315
                4'b1_000,
1316
                4'b1_111: match4 = 1'b0;
1317
                4'b1_001: match4 =
1318 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
1319
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1320 10 unneback
                4'b1_010: match4 =
1321 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
1322
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1323 10 unneback
                4'b1_011: match4 =
1324 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
1325
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1326 10 unneback
                4'b1_100: match4 =
1327 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
1328
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1329 10 unneback
                4'b1_101: match4 =
1330 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
1331
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1332 10 unneback
                4'b1_110: match4 =
1333 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
1334
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1335 10 unneback
        endcase
1336
 
1337
//
1338
// Watchpoint 4
1339
//
1340
always @(dmr1 or match4 or wp)
1341
        case (dmr1[`OR1200_DU_DMR1_CW4])
1342
                2'b00: wp[4] = match4;
1343
                2'b01: wp[4] = match4 & wp[3];
1344
                2'b10: wp[4] = match4 | wp[3];
1345
                2'b11: wp[4] = 1'b0;
1346
        endcase
1347
 
1348
//
1349
// Compare To What (Match Condition 5)
1350
//
1351
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1352
        or dcpu_dat_lsu or dcpu_we_i)
1353
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1354
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1355
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1356
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1357
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1358
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1359
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1360
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1361
        endcase
1362
 
1363
//
1364
// When To Compare (Match Condition 5)
1365
//
1366
always @(dcr5 or dcpu_cycstb_i)
1367
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1368
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1369
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1370
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1371
        endcase
1372
 
1373
//
1374
// Match Condition 5
1375
//
1376
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1377
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1378
                4'b0_xxx,
1379
                4'b1_000,
1380
                4'b1_111: match5 = 1'b0;
1381
                4'b1_001: match5 =
1382 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
1383
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1384 10 unneback
                4'b1_010: match5 =
1385 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
1386
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1387 10 unneback
                4'b1_011: match5 =
1388 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
1389
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1390 10 unneback
                4'b1_100: match5 =
1391 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
1392
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1393 10 unneback
                4'b1_101: match5 =
1394 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
1395
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1396 10 unneback
                4'b1_110: match5 =
1397 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
1398
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1399 10 unneback
        endcase
1400
 
1401
//
1402
// Watchpoint 5
1403
//
1404
always @(dmr1 or match5 or wp)
1405
        case (dmr1[`OR1200_DU_DMR1_CW5])
1406
                2'b00: wp[5] = match5;
1407
                2'b01: wp[5] = match5 & wp[4];
1408
                2'b10: wp[5] = match5 | wp[4];
1409
                2'b11: wp[5] = 1'b0;
1410
        endcase
1411
 
1412
//
1413
// Compare To What (Match Condition 6)
1414
//
1415
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1416
        or dcpu_dat_lsu or dcpu_we_i)
1417
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1418
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1419
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1420
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1421
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1422
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1423
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1424
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1425
        endcase
1426
 
1427
//
1428
// When To Compare (Match Condition 6)
1429
//
1430
always @(dcr6 or dcpu_cycstb_i)
1431
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1432
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1433
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1434
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1435
        endcase
1436
 
1437
//
1438
// Match Condition 6
1439
//
1440
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1441
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1442
                4'b0_xxx,
1443
                4'b1_000,
1444
                4'b1_111: match6 = 1'b0;
1445
                4'b1_001: match6 =
1446 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
1447
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1448 10 unneback
                4'b1_010: match6 =
1449 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
1450
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1451 10 unneback
                4'b1_011: match6 =
1452 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
1453
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1454 10 unneback
                4'b1_100: match6 =
1455 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
1456
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1457 10 unneback
                4'b1_101: match6 =
1458 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
1459
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1460 10 unneback
                4'b1_110: match6 =
1461 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
1462
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1463 10 unneback
        endcase
1464
 
1465
//
1466
// Watchpoint 6
1467
//
1468
always @(dmr1 or match6 or wp)
1469
        case (dmr1[`OR1200_DU_DMR1_CW6])
1470
                2'b00: wp[6] = match6;
1471
                2'b01: wp[6] = match6 & wp[5];
1472
                2'b10: wp[6] = match6 | wp[5];
1473
                2'b11: wp[6] = 1'b0;
1474
        endcase
1475
 
1476
//
1477
// Compare To What (Match Condition 7)
1478
//
1479
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1480
        or dcpu_dat_lsu or dcpu_we_i)
1481
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1482
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1483
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1484
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1485
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1486
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1487
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1488
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1489
        endcase
1490
 
1491
//
1492
// When To Compare (Match Condition 7)
1493
//
1494
always @(dcr7 or dcpu_cycstb_i)
1495
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1496
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1497
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1498
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1499
        endcase
1500
 
1501
//
1502
// Match Condition 7
1503
//
1504
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1505
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1506
                4'b0_xxx,
1507
                4'b1_000,
1508
                4'b1_111: match7 = 1'b0;
1509
                4'b1_001: match7 =
1510 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
1511
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1512 10 unneback
                4'b1_010: match7 =
1513 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
1514
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1515 10 unneback
                4'b1_011: match7 =
1516 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
1517
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1518 10 unneback
                4'b1_100: match7 =
1519 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
1520
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1521 10 unneback
                4'b1_101: match7 =
1522 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
1523
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1524 10 unneback
                4'b1_110: match7 =
1525 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
1526
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1527 10 unneback
        endcase
1528
 
1529
//
1530
// Watchpoint 7
1531
//
1532
always @(dmr1 or match7 or wp)
1533
        case (dmr1[`OR1200_DU_DMR1_CW7])
1534
                2'b00: wp[7] = match7;
1535
                2'b01: wp[7] = match7 & wp[6];
1536
                2'b10: wp[7] = match7 | wp[6];
1537
                2'b11: wp[7] = 1'b0;
1538
        endcase
1539
 
1540
//
1541
// Increment Watchpoint Counter 0
1542
//
1543
always @(wp or dmr2)
1544
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1545
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1546
        else
1547
                incr_wpcntr0 = 1'b0;
1548
 
1549
//
1550
// Match Condition Watchpoint Counter 0
1551
//
1552
always @(dwcr0)
1553
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1554
                wpcntr0_match = 1'b1;
1555
        else
1556
                wpcntr0_match = 1'b0;
1557
 
1558
 
1559
//
1560
// Watchpoint 8
1561
//
1562
always @(dmr1 or wpcntr0_match or wp)
1563
        case (dmr1[`OR1200_DU_DMR1_CW8])
1564
                2'b00: wp[8] = wpcntr0_match;
1565
                2'b01: wp[8] = wpcntr0_match & wp[7];
1566
                2'b10: wp[8] = wpcntr0_match | wp[7];
1567
                2'b11: wp[8] = 1'b0;
1568
        endcase
1569
 
1570
 
1571
//
1572
// Increment Watchpoint Counter 1
1573
//
1574
always @(wp or dmr2)
1575
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1576
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1577
        else
1578
                incr_wpcntr1 = 1'b0;
1579
 
1580
//
1581
// Match Condition Watchpoint Counter 1
1582
//
1583
always @(dwcr1)
1584
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1585
                wpcntr1_match = 1'b1;
1586
        else
1587
                wpcntr1_match = 1'b0;
1588
 
1589
//
1590
// Watchpoint 9
1591
//
1592
always @(dmr1 or wpcntr1_match or wp)
1593
        case (dmr1[`OR1200_DU_DMR1_CW9])
1594
                2'b00: wp[9] = wpcntr1_match;
1595
                2'b01: wp[9] = wpcntr1_match & wp[8];
1596
                2'b10: wp[9] = wpcntr1_match | wp[8];
1597
                2'b11: wp[9] = 1'b0;
1598
        endcase
1599
 
1600
//
1601
// Watchpoint 10
1602
//
1603
always @(dmr1 or dbg_ewt_i or wp)
1604
        case (dmr1[`OR1200_DU_DMR1_CW10])
1605
                2'b00: wp[10] = dbg_ewt_i;
1606
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1607
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1608
                2'b11: wp[10] = 1'b0;
1609
        endcase
1610
 
1611
`endif
1612
 
1613
//
1614
// Watchpoints can cause trap exception
1615
//
1616
`ifdef OR1200_DU_HWBKPTS
1617 141 marcus.erl
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
1618 10 unneback
`else
1619
assign du_hwbkpt = 1'b0;
1620
`endif
1621
 
1622 141 marcus.erl
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception 
1623 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
1624
        if (rst == `OR1200_RST_VALUE)
1625 258 julius
                du_hwbkpt_hold <=  1'b0;
1626 141 marcus.erl
        else if (du_hwbkpt & ex_freeze)
1627 258 julius
                du_hwbkpt_hold <=  1'b1;
1628 141 marcus.erl
        else if (!ex_freeze)
1629 258 julius
                du_hwbkpt_hold <=  1'b0;
1630 141 marcus.erl
 
1631 10 unneback
`ifdef OR1200_DU_TB_IMPLEMENTED
1632
//
1633
// Simple trace buffer
1634
// (right now hardcoded for Xilinx Virtex FPGAs)
1635
//
1636
// Stores last 256 instruction addresses, instruction
1637
// machine words and ALU results
1638
//
1639
 
1640
//
1641
// Trace buffer write enable
1642
//
1643
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1644
 
1645
//
1646
// Trace buffer write address pointer
1647
//
1648 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
1649
        if (rst == `OR1200_RST_VALUE)
1650 258 julius
                tb_wadr <=  8'h00;
1651 10 unneback
        else if (tb_enw)
1652 258 julius
                tb_wadr <=  tb_wadr + 8'd1;
1653 10 unneback
 
1654
//
1655
// Free running counter (time stamp)
1656
//
1657 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
1658
        if (rst == `OR1200_RST_VALUE)
1659 258 julius
                tb_timstmp <=  32'h00000000;
1660 10 unneback
        else if (!dbg_bp_r)
1661 258 julius
                tb_timstmp <=  tb_timstmp + 32'd1;
1662 10 unneback
 
1663
//
1664
// Trace buffer RAMs
1665
//
1666
 
1667
or1200_dpram_256x32 tbia_ram(
1668
        .clk_a(clk),
1669 141 marcus.erl
        .rst_a(1'b0),
1670 10 unneback
        .addr_a(spr_addr[7:0]),
1671
        .ce_a(1'b1),
1672
        .oe_a(1'b1),
1673
        .do_a(tbia_dat_o),
1674
 
1675
        .clk_b(clk),
1676 141 marcus.erl
        .rst_b(1'b0),
1677 10 unneback
        .addr_b(tb_wadr),
1678
        .di_b(spr_dat_npc),
1679
        .ce_b(1'b1),
1680
        .we_b(tb_enw)
1681
 
1682
);
1683
 
1684
or1200_dpram_256x32 tbim_ram(
1685
        .clk_a(clk),
1686 141 marcus.erl
        .rst_a(1'b0),
1687 10 unneback
        .addr_a(spr_addr[7:0]),
1688
        .ce_a(1'b1),
1689
        .oe_a(1'b1),
1690
        .do_a(tbim_dat_o),
1691
 
1692
        .clk_b(clk),
1693 141 marcus.erl
        .rst_b(1'b0),
1694 10 unneback
        .addr_b(tb_wadr),
1695
        .di_b(ex_insn),
1696
        .ce_b(1'b1),
1697
        .we_b(tb_enw)
1698
);
1699
 
1700
or1200_dpram_256x32 tbar_ram(
1701
        .clk_a(clk),
1702 141 marcus.erl
        .rst_a(1'b0),
1703 10 unneback
        .addr_a(spr_addr[7:0]),
1704
        .ce_a(1'b1),
1705
        .oe_a(1'b1),
1706
        .do_a(tbar_dat_o),
1707
 
1708
        .clk_b(clk),
1709 141 marcus.erl
        .rst_b(1'b0),
1710 10 unneback
        .addr_b(tb_wadr),
1711
        .di_b(rf_dataw),
1712
        .ce_b(1'b1),
1713
        .we_b(tb_enw)
1714
);
1715
 
1716
or1200_dpram_256x32 tbts_ram(
1717
        .clk_a(clk),
1718 141 marcus.erl
        .rst_a(1'b0),
1719 10 unneback
        .addr_a(spr_addr[7:0]),
1720
        .ce_a(1'b1),
1721
        .oe_a(1'b1),
1722
        .do_a(tbts_dat_o),
1723
 
1724
        .clk_b(clk),
1725 141 marcus.erl
        .rst_b(1'b0),
1726 10 unneback
        .addr_b(tb_wadr),
1727
        .di_b(tb_timstmp),
1728
        .ce_b(1'b1),
1729
        .we_b(tb_enw)
1730
);
1731
 
1732
`else
1733
 
1734
assign tbia_dat_o = 32'h0000_0000;
1735
assign tbim_dat_o = 32'h0000_0000;
1736
assign tbar_dat_o = 32'h0000_0000;
1737
assign tbts_dat_o = 32'h0000_0000;
1738
 
1739
`endif  // OR1200_DU_TB_IMPLEMENTED
1740
 
1741
`else   // OR1200_DU_IMPLEMENTED
1742
 
1743
//
1744
// When DU is not implemented, drive all outputs as would when DU is disabled
1745
//
1746
assign dbg_bp_o = 1'b0;
1747
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1748 141 marcus.erl
assign du_dmr1 = {25{1'b0}};
1749 10 unneback
assign du_hwbkpt = 1'b0;
1750
 
1751
//
1752
// Read DU registers
1753
//
1754
`ifdef OR1200_DU_READREGS
1755
assign spr_dat_o = 32'h0000_0000;
1756
`ifdef OR1200_DU_UNUSED_ZERO
1757
`endif
1758
`endif
1759
 
1760
`endif
1761
 
1762
endmodule

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