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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 859

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1 10 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius 
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
//
45 141 marcus.erl 
// $Log: or1200_du.v,v $
46 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47 
// Minor update:
48 
// Bugs fixed.
49 10 unneback 
 
50 
// synopsys translate_off
51 
`include "timescale.v"
52 
// synopsys translate_on
53 
`include "or1200_defines.v"
54 
 
55 
//
56 
// Debug unit
57 
//
58 
 
59 
module or1200_du(
60 
        // RISC Internal Interface
61 
        clk, rst,
62 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
63 
        dcpu_dat_dc, icpu_cycstb_i,
64 
        ex_freeze, branch_op, ex_insn, id_pc,
65 
        spr_dat_npc, rf_dataw,
66 141 marcus.erl 
        du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
67 859 olof 
        du_read, du_write, du_except_stop, du_hwbkpt, du_flush_pipe,
68 10 unneback 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
69 
 
70 
        // External Debug Interface
71 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
72 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
73 
);
74 
 
75 
parameter dw = `OR1200_OPERAND_WIDTH;
76 
parameter aw = `OR1200_OPERAND_WIDTH;
77 
 
78 
//
79 
// I/O
80 
//
81 
 
82 
//
83 
// RISC Internal Interface
84 
//
85 
input                           clk;            // Clock
86 
input                           rst;            // Reset
87 
input                           dcpu_cycstb_i;  // LSU status
88 
input                           dcpu_we_i;      // LSU status
89 
input   [31:0]                   dcpu_adr_i;     // LSU addr
90 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
91 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
92 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
93 
input                           ex_freeze;      // EX stage freeze
94 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
95 
input   [dw-1:0]         ex_insn;        // EX insn
96 
input   [31:0]                   id_pc;          // insn fetch EA
97 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
98 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
99 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
100 141 marcus.erl 
output  [24: 0]                  du_dmr1;
101 10 unneback 
output                          du_stall;       // Debug Unit Stall
102 
output  [aw-1:0]         du_addr;        // Debug Unit Address
103 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
104 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
105 
output                          du_read;        // Debug Unit Read Enable
106 
output                          du_write;       // Debug Unit Write Enable
107 185 julius 
input   [13:0]                   du_except_stop; // Exception masked by DSR
108 10 unneback 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
109 859 olof 
output                          du_flush_pipe;  // Cause pipeline flush and pc<-npc
110 10 unneback 
input                           spr_cs;         // SPR Chip Select
111 
input                           spr_write;      // SPR Read/Write
112 
input   [aw-1:0]         spr_addr;       // SPR Address
113 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
114 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
115 
 
116 
//
117 
// External Debug Interface
118 
//
119 
input                   dbg_stall_i;    // External Stall Input
120 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
121 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
122 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
123 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
124 
output                  dbg_bp_o;       // Breakpoint Output
125 
input                   dbg_stb_i;      // External Address/Data Strobe
126 
input                   dbg_we_i;       // External Write Enable
127 
input   [aw-1:0] dbg_adr_i;      // External Address Input
128 
input   [dw-1:0] dbg_dat_i;      // External Data Input
129 
output  [dw-1:0] dbg_dat_o;      // External Data Output
130 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
131 141 marcus.erl 
reg     [dw-1:0] dbg_dat_o;      // External Data Output
132 
reg                     dbg_ack_o;      // External Data Acknowledge (not WB compatible)
133 10 unneback 
 
134 
 
135 
//
136 
// Some connections go directly from the CPU through DU to Debug I/F
137 
//
138 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
139 
assign dbg_lss_o = 4'b0000;
140 
 
141 
reg     [1:0]                    dbg_is_o;
142 
//
143 
// Show insn activity (temp, must be removed)
144 
//
145 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
146 
        if (rst == `OR1200_RST_VALUE)
147 258 julius 
                dbg_is_o <=  2'b00;
148 141 marcus.erl 
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
149 258 julius 
                dbg_is_o <=  ~dbg_is_o;
150 10 unneback 
`ifdef UNUSED
151 
assign dbg_is_o = 2'b00;
152 
`endif
153 
`else
154 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
155 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
156 
`endif
157 
assign dbg_wp_o = 11'b000_0000_0000;
158 
 
159 
//
160 
// Some connections go directly from Debug I/F through DU to the CPU
161 
//
162 
assign du_stall = dbg_stall_i;
163 
assign du_addr = dbg_adr_i;
164 
assign du_dat_o = dbg_dat_i;
165 
assign du_read = dbg_stb_i && !dbg_we_i;
166 
assign du_write = dbg_stb_i && dbg_we_i;
167 
 
168 859 olof 
//
169 
// After a sw breakpoint, the replaced instruction need to be executed.
170 
// We flush the entire pipeline and set the pc to the current address
171 
// to execute the restored address.
172 
//
173 
 
174 
reg du_flush_pipe_r;
175 
reg dbg_stall_i_r;
176 
 
177 
assign du_flush_pipe = du_flush_pipe_r;
178 
 
179 
//
180 
// Register du_flush_pipe
181 
//
182 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
183 
        if (rst == `OR1200_RST_VALUE) begin
184 
                du_flush_pipe_r   <=  1'b0;
185 
        end
186 
        else begin
187 
                du_flush_pipe_r   <=  (dbg_stall_i_r && !dbg_stall_i && |du_except_stop);
188 
        end
189 
end
190 
 
191 
//
192 
// Detect dbg_stall falling edge
193 
//
194 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
195 
        if (rst == `OR1200_RST_VALUE) begin
196 
                dbg_stall_i_r   <=  1'b0;
197 
        end
198 
        else begin
199 
                dbg_stall_i_r   <=  dbg_stall_i;
200 
        end
201 
end
202 
 
203 141 marcus.erl 
reg                             dbg_ack;
204 10 unneback 
//
205 
// Generate acknowledge -- just delay stb signal
206 
//
207 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
208 
        if (rst == `OR1200_RST_VALUE) begin
209 258 julius 
                dbg_ack   <=  1'b0;
210 
                dbg_ack_o <=  1'b0;
211 141 marcus.erl 
        end
212 
        else begin
213 258 julius 
                dbg_ack   <=  dbg_stb_i;                // valid when du_dat_i
214 
                dbg_ack_o <=  dbg_ack & dbg_stb_i;      // valid when dbg_dat_o
215 141 marcus.erl 
        end
216 
end
217 10 unneback 
 
218 141 marcus.erl 
//
219 
// Register data output
220 
//
221 
always @(posedge clk)
222 258 julius 
    dbg_dat_o <=  du_dat_i;
223 141 marcus.erl 
 
224 10 unneback 
`ifdef OR1200_DU_IMPLEMENTED
225 
 
226 
//
227 
// Debug Mode Register 1
228 
//
229 
`ifdef OR1200_DU_DMR1
230 
reg     [24:0]                   dmr1;           // DMR1 implemented
231 
`else
232 
wire    [24:0]                   dmr1;           // DMR1 not implemented
233 
`endif
234 141 marcus.erl 
assign du_dmr1 = dmr1;
235 10 unneback 
 
236 
//
237 
// Debug Mode Register 2
238 
//
239 
`ifdef OR1200_DU_DMR2
240 
reg     [23:0]                   dmr2;           // DMR2 implemented
241 
`else
242 
wire    [23:0]                   dmr2;           // DMR2 not implemented
243 
`endif
244 
 
245 
//
246 
// Debug Stop Register
247 
//
248 
`ifdef OR1200_DU_DSR
249 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
250 
`else
251 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
252 
`endif
253 
 
254 
//
255 
// Debug Reason Register
256 
//
257 
`ifdef OR1200_DU_DRR
258 
reg     [13:0]                   drr;            // DRR implemented
259 
`else
260 
wire    [13:0]                   drr;            // DRR not implemented
261 
`endif
262 
 
263 
//
264 
// Debug Value Register N
265 
//
266 
`ifdef OR1200_DU_DVR0
267 
reg     [31:0]                   dvr0;
268 
`else
269 
wire    [31:0]                   dvr0;
270 
`endif
271 
 
272 
//
273 
// Debug Value Register N
274 
//
275 
`ifdef OR1200_DU_DVR1
276 
reg     [31:0]                   dvr1;
277 
`else
278 
wire    [31:0]                   dvr1;
279 
`endif
280 
 
281 
//
282 
// Debug Value Register N
283 
//
284 
`ifdef OR1200_DU_DVR2
285 
reg     [31:0]                   dvr2;
286 
`else
287 
wire    [31:0]                   dvr2;
288 
`endif
289 
 
290 
//
291 
// Debug Value Register N
292 
//
293 
`ifdef OR1200_DU_DVR3
294 
reg     [31:0]                   dvr3;
295 
`else
296 
wire    [31:0]                   dvr3;
297 
`endif
298 
 
299 
//
300 
// Debug Value Register N
301 
//
302 
`ifdef OR1200_DU_DVR4
303 
reg     [31:0]                   dvr4;
304 
`else
305 
wire    [31:0]                   dvr4;
306 
`endif
307 
 
308 
//
309 
// Debug Value Register N
310 
//
311 
`ifdef OR1200_DU_DVR5
312 
reg     [31:0]                   dvr5;
313 
`else
314 
wire    [31:0]                   dvr5;
315 
`endif
316 
 
317 
//
318 
// Debug Value Register N
319 
//
320 
`ifdef OR1200_DU_DVR6
321 
reg     [31:0]                   dvr6;
322 
`else
323 
wire    [31:0]                   dvr6;
324 
`endif
325 
 
326 
//
327 
// Debug Value Register N
328 
//
329 
`ifdef OR1200_DU_DVR7
330 
reg     [31:0]                   dvr7;
331 
`else
332 
wire    [31:0]                   dvr7;
333 
`endif
334 
 
335 
//
336 
// Debug Control Register N
337 
//
338 
`ifdef OR1200_DU_DCR0
339 
reg     [7:0]                    dcr0;
340 
`else
341 
wire    [7:0]                    dcr0;
342 
`endif
343 
 
344 
//
345 
// Debug Control Register N
346 
//
347 
`ifdef OR1200_DU_DCR1
348 
reg     [7:0]                    dcr1;
349 
`else
350 
wire    [7:0]                    dcr1;
351 
`endif
352 
 
353 
//
354 
// Debug Control Register N
355 
//
356 
`ifdef OR1200_DU_DCR2
357 
reg     [7:0]                    dcr2;
358 
`else
359 
wire    [7:0]                    dcr2;
360 
`endif
361 
 
362 
//
363 
// Debug Control Register N
364 
//
365 
`ifdef OR1200_DU_DCR3
366 
reg     [7:0]                    dcr3;
367 
`else
368 
wire    [7:0]                    dcr3;
369 
`endif
370 
 
371 
//
372 
// Debug Control Register N
373 
//
374 
`ifdef OR1200_DU_DCR4
375 
reg     [7:0]                    dcr4;
376 
`else
377 
wire    [7:0]                    dcr4;
378 
`endif
379 
 
380 
//
381 
// Debug Control Register N
382 
//
383 
`ifdef OR1200_DU_DCR5
384 
reg     [7:0]                    dcr5;
385 
`else
386 
wire    [7:0]                    dcr5;
387 
`endif
388 
 
389 
//
390 
// Debug Control Register N
391 
//
392 
`ifdef OR1200_DU_DCR6
393 
reg     [7:0]                    dcr6;
394 
`else
395 
wire    [7:0]                    dcr6;
396 
`endif
397 
 
398 
//
399 
// Debug Control Register N
400 
//
401 
`ifdef OR1200_DU_DCR7
402 
reg     [7:0]                    dcr7;
403 
`else
404 
wire    [7:0]                    dcr7;
405 
`endif
406 
 
407 
//
408 
// Debug Watchpoint Counter Register 0
409 
//
410 
`ifdef OR1200_DU_DWCR0
411 
reg     [31:0]                   dwcr0;
412 
`else
413 
wire    [31:0]                   dwcr0;
414 
`endif
415 
 
416 
//
417 
// Debug Watchpoint Counter Register 1
418 
//
419 
`ifdef OR1200_DU_DWCR1
420 
reg     [31:0]                   dwcr1;
421 
`else
422 
wire    [31:0]                   dwcr1;
423 
`endif
424 
 
425 
//
426 
// Internal wires
427 
//
428 
wire                            dmr1_sel;       // DMR1 select
429 
wire                            dmr2_sel;       // DMR2 select
430 
wire                            dsr_sel;        // DSR select
431 
wire                            drr_sel;        // DRR select
432 
wire                            dvr0_sel,
433 
                                dvr1_sel,
434 
                                dvr2_sel,
435 
                                dvr3_sel,
436 
                                dvr4_sel,
437 
                                dvr5_sel,
438 
                                dvr6_sel,
439 
                                dvr7_sel;       // DVR selects
440 
wire                            dcr0_sel,
441 
                                dcr1_sel,
442 
                                dcr2_sel,
443 
                                dcr3_sel,
444 
                                dcr4_sel,
445 
                                dcr5_sel,
446 
                                dcr6_sel,
447 
                                dcr7_sel;       // DCR selects
448 
wire                            dwcr0_sel,
449 
                                dwcr1_sel;      // DWCR selects
450 
reg                             dbg_bp_r;
451 815 yannv 
reg                             ex_freeze_q;
452 10 unneback 
`ifdef OR1200_DU_HWBKPTS
453 
reg     [31:0]                   match_cond0_ct;
454 
reg     [31:0]                   match_cond1_ct;
455 
reg     [31:0]                   match_cond2_ct;
456 
reg     [31:0]                   match_cond3_ct;
457 
reg     [31:0]                   match_cond4_ct;
458 
reg     [31:0]                   match_cond5_ct;
459 
reg     [31:0]                   match_cond6_ct;
460 
reg     [31:0]                   match_cond7_ct;
461 
reg                             match_cond0_stb;
462 
reg                             match_cond1_stb;
463 
reg                             match_cond2_stb;
464 
reg                             match_cond3_stb;
465 
reg                             match_cond4_stb;
466 
reg                             match_cond5_stb;
467 
reg                             match_cond6_stb;
468 
reg                             match_cond7_stb;
469 
reg                             match0;
470 
reg                             match1;
471 
reg                             match2;
472 
reg                             match3;
473 
reg                             match4;
474 
reg                             match5;
475 
reg                             match6;
476 
reg                             match7;
477 
reg                             wpcntr0_match;
478 
reg                             wpcntr1_match;
479 
reg                             incr_wpcntr0;
480 
reg                             incr_wpcntr1;
481 
reg     [10:0]                   wp;
482 
`endif
483 
wire                            du_hwbkpt;
484 141 marcus.erl 
reg                             du_hwbkpt_hold;
485 10 unneback 
`ifdef OR1200_DU_READREGS
486 
reg     [31:0]                   spr_dat_o;
487 
`endif
488 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
489 
`ifdef OR1200_DU_TB_IMPLEMENTED
490 
wire                            tb_enw;
491 
reg     [7:0]                    tb_wadr;
492 
reg [31:0]                       tb_timstmp;
493 
`endif
494 
wire    [31:0]                   tbia_dat_o;
495 
wire    [31:0]                   tbim_dat_o;
496 
wire    [31:0]                   tbar_dat_o;
497 
wire    [31:0]                   tbts_dat_o;
498 
 
499 
//
500 
// DU registers address decoder
501 
//
502 
`ifdef OR1200_DU_DMR1
503 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
504 
`endif
505 
`ifdef OR1200_DU_DMR2
506 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
507 
`endif
508 
`ifdef OR1200_DU_DSR
509 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
510 
`endif
511 
`ifdef OR1200_DU_DRR
512 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
513 
`endif
514 
`ifdef OR1200_DU_DVR0
515 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
516 
`endif
517 
`ifdef OR1200_DU_DVR1
518 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
519 
`endif
520 
`ifdef OR1200_DU_DVR2
521 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
522 
`endif
523 
`ifdef OR1200_DU_DVR3
524 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
525 
`endif
526 
`ifdef OR1200_DU_DVR4
527 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
528 
`endif
529 
`ifdef OR1200_DU_DVR5
530 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
531 
`endif
532 
`ifdef OR1200_DU_DVR6
533 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
534 
`endif
535 
`ifdef OR1200_DU_DVR7
536 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
537 
`endif
538 
`ifdef OR1200_DU_DCR0
539 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
540 
`endif
541 
`ifdef OR1200_DU_DCR1
542 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
543 
`endif
544 
`ifdef OR1200_DU_DCR2
545 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
546 
`endif
547 
`ifdef OR1200_DU_DCR3
548 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
549 
`endif
550 
`ifdef OR1200_DU_DCR4
551 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
552 
`endif
553 
`ifdef OR1200_DU_DCR5
554 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
555 
`endif
556 
`ifdef OR1200_DU_DCR6
557 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
558 
`endif
559 
`ifdef OR1200_DU_DCR7
560 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
561 
`endif
562 
`ifdef OR1200_DU_DWCR0
563 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
564 
`endif
565 
`ifdef OR1200_DU_DWCR1
566 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
567 
`endif
568 
 
569 815 yannv 
// Track previous ex_freeze to detect when signals are updated
570 
always @(posedge clk)
571 
  ex_freeze_q <= ex_freeze;
572 
 
573 10 unneback 
//
574 
// Decode started exception
575 
//
576 185 julius 
// du_except_stop comes from or1200_except
577 
//
578 815 yannv 
always @(du_except_stop or ex_freeze_q) begin
579 185 julius 
        except_stop = 14'b00_0000_0000_0000;
580 364 julius 
        casez (du_except_stop)
581 
                14'b1?_????_????_????:
582 10 unneback 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
583 364 julius 
                14'b01_????_????_????: begin
584 10 unneback 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
585 
                end
586 364 julius 
                14'b00_1???_????_????: begin
587 10 unneback 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
588 
                end
589 364 julius 
                14'b00_01??_????_????:
590 10 unneback 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
591 364 julius 
                14'b00_001?_????_????: begin
592 10 unneback 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
593 
                end
594 364 julius 
                14'b00_0001_????_????:
595 10 unneback 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
596 364 julius 
                14'b00_0000_1???_????: begin
597 10 unneback 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
598 
                end
599 364 julius 
                14'b00_0000_01??_????: begin
600 10 unneback 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
601 
                end
602 364 julius 
                14'b00_0000_001?_????:
603 10 unneback 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
604 364 julius 
                14'b00_0000_0001_????:
605 10 unneback 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
606 364 julius 
                14'b00_0000_0000_1???: begin
607 10 unneback 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
608 
                end
609 364 julius 
                14'b00_0000_0000_01??: begin
610 815 yannv 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1 & ~ex_freeze_q;
611 10 unneback 
                end
612 364 julius 
                14'b00_0000_0000_001?: begin
613 185 julius 
                        except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
614 
                end
615 
                14'b00_0000_0000_0001:
616 815 yannv 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1 & ~ex_freeze_q;
617 10 unneback 
                default:
618 185 julius 
                        except_stop = 14'b00_0000_0000_0000;
619 815 yannv 
        endcase // casez (du_except_stop)
620 10 unneback 
end
621 
 
622 
//
623 
// dbg_bp_o is registered
624 
//
625 
assign dbg_bp_o = dbg_bp_r;
626 
 
627 
//
628 
// Breakpoint activation register
629 
//
630 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
631 
        if (rst == `OR1200_RST_VALUE)
632 258 julius 
                dbg_bp_r <=  1'b0;
633 10 unneback 
        else if (!ex_freeze)
634 258 julius 
                dbg_bp_r <=  |except_stop
635 10 unneback 
`ifdef OR1200_DU_DMR1_ST
636 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
637 
`endif
638 
`ifdef OR1200_DU_DMR1_BT
639 141 marcus.erl 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
640 10 unneback 
`endif
641 
                        ;
642 
        else
643 258 julius 
                dbg_bp_r <=  |except_stop;
644 10 unneback 
 
645 
//
646 
// Write to DMR1
647 
//
648 
`ifdef OR1200_DU_DMR1
649 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
650 
        if (rst == `OR1200_RST_VALUE)
651 10 unneback 
                dmr1 <= 25'h000_0000;
652 
        else if (dmr1_sel && spr_write)
653 
`ifdef OR1200_DU_HWBKPTS
654 258 julius 
                dmr1 <=  spr_dat_i[24:0];
655 10 unneback 
`else
656 258 julius 
                dmr1 <=  {1'b0, spr_dat_i[23:22], 22'h00_0000};
657 10 unneback 
`endif
658 
`else
659 
assign dmr1 = 25'h000_0000;
660 
`endif
661 
 
662 
//
663 
// Write to DMR2
664 
//
665 
`ifdef OR1200_DU_DMR2
666 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
667 
        if (rst == `OR1200_RST_VALUE)
668 10 unneback 
                dmr2 <= 24'h00_0000;
669 
        else if (dmr2_sel && spr_write)
670 258 julius 
                dmr2 <=  spr_dat_i[23:0];
671 10 unneback 
`else
672 
assign dmr2 = 24'h00_0000;
673 
`endif
674 
 
675 
//
676 
// Write to DSR
677 
//
678 
`ifdef OR1200_DU_DSR
679 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
680 
        if (rst == `OR1200_RST_VALUE)
681 10 unneback 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
682 
        else if (dsr_sel && spr_write)
683 258 julius 
                dsr <=  spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
684 10 unneback 
`else
685 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
686 
`endif
687 
 
688 
//
689 
// Write to DRR
690 
//
691 
`ifdef OR1200_DU_DRR
692 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
693 
        if (rst == `OR1200_RST_VALUE)
694 10 unneback 
                drr <= 14'b0;
695 
        else if (drr_sel && spr_write)
696 258 julius 
                drr <=  spr_dat_i[13:0];
697 10 unneback 
        else
698 258 julius 
                drr <=  drr | except_stop;
699 10 unneback 
`else
700 
assign drr = 14'b0;
701 
`endif
702 
 
703 
//
704 
// Write to DVR0
705 
//
706 
`ifdef OR1200_DU_DVR0
707 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
708 
        if (rst == `OR1200_RST_VALUE)
709 10 unneback 
                dvr0 <= 32'h0000_0000;
710 
        else if (dvr0_sel && spr_write)
711 258 julius 
                dvr0 <=  spr_dat_i[31:0];
712 10 unneback 
`else
713 
assign dvr0 = 32'h0000_0000;
714 
`endif
715 
 
716 
//
717 
// Write to DVR1
718 
//
719 
`ifdef OR1200_DU_DVR1
720 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
721 
        if (rst == `OR1200_RST_VALUE)
722 10 unneback 
                dvr1 <= 32'h0000_0000;
723 
        else if (dvr1_sel && spr_write)
724 258 julius 
                dvr1 <=  spr_dat_i[31:0];
725 10 unneback 
`else
726 
assign dvr1 = 32'h0000_0000;
727 
`endif
728 
 
729 
//
730 
// Write to DVR2
731 
//
732 
`ifdef OR1200_DU_DVR2
733 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
734 
        if (rst == `OR1200_RST_VALUE)
735 10 unneback 
                dvr2 <= 32'h0000_0000;
736 
        else if (dvr2_sel && spr_write)
737 258 julius 
                dvr2 <=  spr_dat_i[31:0];
738 10 unneback 
`else
739 
assign dvr2 = 32'h0000_0000;
740 
`endif
741 
 
742 
//
743 
// Write to DVR3
744 
//
745 
`ifdef OR1200_DU_DVR3
746 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
747 
        if (rst == `OR1200_RST_VALUE)
748 10 unneback 
                dvr3 <= 32'h0000_0000;
749 
        else if (dvr3_sel && spr_write)
750 258 julius 
                dvr3 <=  spr_dat_i[31:0];
751 10 unneback 
`else
752 
assign dvr3 = 32'h0000_0000;
753 
`endif
754 
 
755 
//
756 
// Write to DVR4
757 
//
758 
`ifdef OR1200_DU_DVR4
759 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
760 
        if (rst == `OR1200_RST_VALUE)
761 10 unneback 
                dvr4 <= 32'h0000_0000;
762 
        else if (dvr4_sel && spr_write)
763 258 julius 
                dvr4 <=  spr_dat_i[31:0];
764 10 unneback 
`else
765 
assign dvr4 = 32'h0000_0000;
766 
`endif
767 
 
768 
//
769 
// Write to DVR5
770 
//
771 
`ifdef OR1200_DU_DVR5
772 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
773 
        if (rst == `OR1200_RST_VALUE)
774 10 unneback 
                dvr5 <= 32'h0000_0000;
775 
        else if (dvr5_sel && spr_write)
776 258 julius 
                dvr5 <=  spr_dat_i[31:0];
777 10 unneback 
`else
778 
assign dvr5 = 32'h0000_0000;
779 
`endif
780 
 
781 
//
782 
// Write to DVR6
783 
//
784 
`ifdef OR1200_DU_DVR6
785 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
786 
        if (rst == `OR1200_RST_VALUE)
787 10 unneback 
                dvr6 <= 32'h0000_0000;
788 
        else if (dvr6_sel && spr_write)
789 258 julius 
                dvr6 <=  spr_dat_i[31:0];
790 10 unneback 
`else
791 
assign dvr6 = 32'h0000_0000;
792 
`endif
793 
 
794 
//
795 
// Write to DVR7
796 
//
797 
`ifdef OR1200_DU_DVR7
798 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
799 
        if (rst == `OR1200_RST_VALUE)
800 10 unneback 
                dvr7 <= 32'h0000_0000;
801 
        else if (dvr7_sel && spr_write)
802 258 julius 
                dvr7 <=  spr_dat_i[31:0];
803 10 unneback 
`else
804 
assign dvr7 = 32'h0000_0000;
805 
`endif
806 
 
807 
//
808 
// Write to DCR0
809 
//
810 
`ifdef OR1200_DU_DCR0
811 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
812 
        if (rst == `OR1200_RST_VALUE)
813 10 unneback 
                dcr0 <= 8'h00;
814 
        else if (dcr0_sel && spr_write)
815 258 julius 
                dcr0 <=  spr_dat_i[7:0];
816 10 unneback 
`else
817 
assign dcr0 = 8'h00;
818 
`endif
819 
 
820 
//
821 
// Write to DCR1
822 
//
823 
`ifdef OR1200_DU_DCR1
824 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
825 
        if (rst == `OR1200_RST_VALUE)
826 10 unneback 
                dcr1 <= 8'h00;
827 
        else if (dcr1_sel && spr_write)
828 258 julius 
                dcr1 <=  spr_dat_i[7:0];
829 10 unneback 
`else
830 
assign dcr1 = 8'h00;
831 
`endif
832 
 
833 
//
834 
// Write to DCR2
835 
//
836 
`ifdef OR1200_DU_DCR2
837 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
838 
        if (rst == `OR1200_RST_VALUE)
839 10 unneback 
                dcr2 <= 8'h00;
840 
        else if (dcr2_sel && spr_write)
841 258 julius 
                dcr2 <=  spr_dat_i[7:0];
842 10 unneback 
`else
843 
assign dcr2 = 8'h00;
844 
`endif
845 
 
846 
//
847 
// Write to DCR3
848 
//
849 
`ifdef OR1200_DU_DCR3
850 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
851 
        if (rst == `OR1200_RST_VALUE)
852 10 unneback 
                dcr3 <= 8'h00;
853 
        else if (dcr3_sel && spr_write)
854 258 julius 
                dcr3 <=  spr_dat_i[7:0];
855 10 unneback 
`else
856 
assign dcr3 = 8'h00;
857 
`endif
858 
 
859 
//
860 
// Write to DCR4
861 
//
862 
`ifdef OR1200_DU_DCR4
863 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
864 
        if (rst == `OR1200_RST_VALUE)
865 10 unneback 
                dcr4 <= 8'h00;
866 
        else if (dcr4_sel && spr_write)
867 258 julius 
                dcr4 <=  spr_dat_i[7:0];
868 10 unneback 
`else
869 
assign dcr4 = 8'h00;
870 
`endif
871 
 
872 
//
873 
// Write to DCR5
874 
//
875 
`ifdef OR1200_DU_DCR5
876 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
877 
        if (rst == `OR1200_RST_VALUE)
878 10 unneback 
                dcr5 <= 8'h00;
879 
        else if (dcr5_sel && spr_write)
880 258 julius 
                dcr5 <=  spr_dat_i[7:0];
881 10 unneback 
`else
882 
assign dcr5 = 8'h00;
883 
`endif
884 
 
885 
//
886 
// Write to DCR6
887 
//
888 
`ifdef OR1200_DU_DCR6
889 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
890 
        if (rst == `OR1200_RST_VALUE)
891 10 unneback 
                dcr6 <= 8'h00;
892 
        else if (dcr6_sel && spr_write)
893 258 julius 
                dcr6 <=  spr_dat_i[7:0];
894 10 unneback 
`else
895 
assign dcr6 = 8'h00;
896 
`endif
897 
 
898 
//
899 
// Write to DCR7
900 
//
901 
`ifdef OR1200_DU_DCR7
902 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
903 
        if (rst == `OR1200_RST_VALUE)
904 10 unneback 
                dcr7 <= 8'h00;
905 
        else if (dcr7_sel && spr_write)
906 258 julius 
                dcr7 <=  spr_dat_i[7:0];
907 10 unneback 
`else
908 
assign dcr7 = 8'h00;
909 
`endif
910 
 
911 
//
912 
// Write to DWCR0
913 
//
914 
`ifdef OR1200_DU_DWCR0
915 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
916 
        if (rst == `OR1200_RST_VALUE)
917 10 unneback 
                dwcr0 <= 32'h0000_0000;
918 
        else if (dwcr0_sel && spr_write)
919 258 julius 
                dwcr0 <=  spr_dat_i[31:0];
920 10 unneback 
        else if (incr_wpcntr0)
921 258 julius 
                dwcr0[`OR1200_DU_DWCR_COUNT] <=  dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
922 10 unneback 
`else
923 
assign dwcr0 = 32'h0000_0000;
924 
`endif
925 
 
926 
//
927 
// Write to DWCR1
928 
//
929 
`ifdef OR1200_DU_DWCR1
930 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
931 
        if (rst == `OR1200_RST_VALUE)
932 10 unneback 
                dwcr1 <= 32'h0000_0000;
933 
        else if (dwcr1_sel && spr_write)
934 258 julius 
                dwcr1 <=  spr_dat_i[31:0];
935 10 unneback 
        else if (incr_wpcntr1)
936 258 julius 
                dwcr1[`OR1200_DU_DWCR_COUNT] <=  dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
937 10 unneback 
`else
938 
assign dwcr1 = 32'h0000_0000;
939 
`endif
940 
 
941 
//
942 
// Read DU registers
943 
//
944 
`ifdef OR1200_DU_READREGS
945 
always @(spr_addr or dsr or drr or dmr1 or dmr2
946 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
947 
        or dvr5 or dvr6 or dvr7
948 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
949 
        or dcr5 or dcr6 or dcr7
950 
        or dwcr0 or dwcr1
951 
`ifdef OR1200_DU_TB_IMPLEMENTED
952 
        or tb_wadr or tbia_dat_o or tbim_dat_o
953 
        or tbar_dat_o or tbts_dat_o
954 
`endif
955 
        )
956 364 julius 
        casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
957 10 unneback 
`ifdef OR1200_DU_DVR0
958 
                `OR1200_DU_DVR0:
959 
                        spr_dat_o = dvr0;
960 
`endif
961 
`ifdef OR1200_DU_DVR1
962 
                `OR1200_DU_DVR1:
963 
                        spr_dat_o = dvr1;
964 
`endif
965 
`ifdef OR1200_DU_DVR2
966 
                `OR1200_DU_DVR2:
967 
                        spr_dat_o = dvr2;
968 
`endif
969 
`ifdef OR1200_DU_DVR3
970 
                `OR1200_DU_DVR3:
971 
                        spr_dat_o = dvr3;
972 
`endif
973 
`ifdef OR1200_DU_DVR4
974 
                `OR1200_DU_DVR4:
975 
                        spr_dat_o = dvr4;
976 
`endif
977 
`ifdef OR1200_DU_DVR5
978 
                `OR1200_DU_DVR5:
979 
                        spr_dat_o = dvr5;
980 
`endif
981 
`ifdef OR1200_DU_DVR6
982 
                `OR1200_DU_DVR6:
983 
                        spr_dat_o = dvr6;
984 
`endif
985 
`ifdef OR1200_DU_DVR7
986 
                `OR1200_DU_DVR7:
987 
                        spr_dat_o = dvr7;
988 
`endif
989 
`ifdef OR1200_DU_DCR0
990 
                `OR1200_DU_DCR0:
991 
                        spr_dat_o = {24'h00_0000, dcr0};
992 
`endif
993 
`ifdef OR1200_DU_DCR1
994 
                `OR1200_DU_DCR1:
995 
                        spr_dat_o = {24'h00_0000, dcr1};
996 
`endif
997 
`ifdef OR1200_DU_DCR2
998 
                `OR1200_DU_DCR2:
999 
                        spr_dat_o = {24'h00_0000, dcr2};
1000 
`endif
1001 
`ifdef OR1200_DU_DCR3
1002 
                `OR1200_DU_DCR3:
1003 
                        spr_dat_o = {24'h00_0000, dcr3};
1004 
`endif
1005 
`ifdef OR1200_DU_DCR4
1006 
                `OR1200_DU_DCR4:
1007 
                        spr_dat_o = {24'h00_0000, dcr4};
1008 
`endif
1009 
`ifdef OR1200_DU_DCR5
1010 
                `OR1200_DU_DCR5:
1011 
                        spr_dat_o = {24'h00_0000, dcr5};
1012 
`endif
1013 
`ifdef OR1200_DU_DCR6
1014 
                `OR1200_DU_DCR6:
1015 
                        spr_dat_o = {24'h00_0000, dcr6};
1016 
`endif
1017 
`ifdef OR1200_DU_DCR7
1018 
                `OR1200_DU_DCR7:
1019 
                        spr_dat_o = {24'h00_0000, dcr7};
1020 
`endif
1021 
`ifdef OR1200_DU_DMR1
1022 
                `OR1200_DU_DMR1:
1023 
                        spr_dat_o = {7'h00, dmr1};
1024 
`endif
1025 
`ifdef OR1200_DU_DMR2
1026 
                `OR1200_DU_DMR2:
1027 
                        spr_dat_o = {8'h00, dmr2};
1028 
`endif
1029 
`ifdef OR1200_DU_DWCR0
1030 
                `OR1200_DU_DWCR0:
1031 
                        spr_dat_o = dwcr0;
1032 
`endif
1033 
`ifdef OR1200_DU_DWCR1
1034 
                `OR1200_DU_DWCR1:
1035 
                        spr_dat_o = dwcr1;
1036 
`endif
1037 
`ifdef OR1200_DU_DSR
1038 
                `OR1200_DU_DSR:
1039 
                        spr_dat_o = {18'b0, dsr};
1040 
`endif
1041 
`ifdef OR1200_DU_DRR
1042 
                `OR1200_DU_DRR:
1043 
                        spr_dat_o = {18'b0, drr};
1044 
`endif
1045 
`ifdef OR1200_DU_TB_IMPLEMENTED
1046 
                `OR1200_DU_TBADR:
1047 
                        spr_dat_o = {24'h000000, tb_wadr};
1048 
                `OR1200_DU_TBIA:
1049 
                        spr_dat_o = tbia_dat_o;
1050 
                `OR1200_DU_TBIM:
1051 
                        spr_dat_o = tbim_dat_o;
1052 
                `OR1200_DU_TBAR:
1053 
                        spr_dat_o = tbar_dat_o;
1054 
                `OR1200_DU_TBTS:
1055 
                        spr_dat_o = tbts_dat_o;
1056 
`endif
1057 
                default:
1058 
                        spr_dat_o = 32'h0000_0000;
1059 
        endcase
1060 
`endif
1061 
 
1062 
//
1063 
// DSR alias
1064 
//
1065 
assign du_dsr = dsr;
1066 
 
1067 
`ifdef OR1200_DU_HWBKPTS
1068 
 
1069 
//
1070 
// Compare To What (Match Condition 0)
1071 
//
1072 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1073 
        or dcpu_dat_lsu or dcpu_we_i)
1074 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1075 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1076 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1077 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1078 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1079 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1080 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1081 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1082 
        endcase
1083 
 
1084 
//
1085 
// When To Compare (Match Condition 0)
1086 
//
1087 
always @(dcr0 or dcpu_cycstb_i)
1088 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1089 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1090 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1091 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1092 
        endcase
1093 
 
1094 
//
1095 
// Match Condition 0
1096 
//
1097 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1098 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1099 
                4'b0_xxx,
1100 
                4'b1_000,
1101 
                4'b1_111: match0 = 1'b0;
1102 
                4'b1_001: match0 =
1103 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
1104 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1105 10 unneback 
                4'b1_010: match0 =
1106 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
1107 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1108 10 unneback 
                4'b1_011: match0 =
1109 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
1110 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1111 10 unneback 
                4'b1_100: match0 =
1112 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
1113 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1114 10 unneback 
                4'b1_101: match0 =
1115 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
1116 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1117 10 unneback 
                4'b1_110: match0 =
1118 141 marcus.erl 
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
1119 
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1120 10 unneback 
        endcase
1121 
 
1122 
//
1123 
// Watchpoint 0
1124 
//
1125 
always @(dmr1 or match0)
1126 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1127 
                2'b00: wp[0] = match0;
1128 
                2'b01: wp[0] = match0;
1129 
                2'b10: wp[0] = match0;
1130 
                2'b11: wp[0] = 1'b0;
1131 
        endcase
1132 
 
1133 
//
1134 
// Compare To What (Match Condition 1)
1135 
//
1136 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1137 
        or dcpu_dat_lsu or dcpu_we_i)
1138 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1139 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1140 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1141 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1142 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1143 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1144 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1145 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1146 
        endcase
1147 
 
1148 
//
1149 
// When To Compare (Match Condition 1)
1150 
//
1151 
always @(dcr1 or dcpu_cycstb_i)
1152 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1153 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1154 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1155 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1156 
        endcase
1157 
 
1158 
//
1159 
// Match Condition 1
1160 
//
1161 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1162 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1163 
                4'b0_xxx,
1164 
                4'b1_000,
1165 
                4'b1_111: match1 = 1'b0;
1166 
                4'b1_001: match1 =
1167 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
1168 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1169 10 unneback 
                4'b1_010: match1 =
1170 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
1171 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1172 10 unneback 
                4'b1_011: match1 =
1173 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
1174 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1175 10 unneback 
                4'b1_100: match1 =
1176 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
1177 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1178 10 unneback 
                4'b1_101: match1 =
1179 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
1180 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1181 10 unneback 
                4'b1_110: match1 =
1182 141 marcus.erl 
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
1183 
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1184 10 unneback 
        endcase
1185 
 
1186 
//
1187 
// Watchpoint 1
1188 
//
1189 
always @(dmr1 or match1 or wp)
1190 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1191 
                2'b00: wp[1] = match1;
1192 
                2'b01: wp[1] = match1 & wp[0];
1193 
                2'b10: wp[1] = match1 | wp[0];
1194 
                2'b11: wp[1] = 1'b0;
1195 
        endcase
1196 
 
1197 
//
1198 
// Compare To What (Match Condition 2)
1199 
//
1200 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1201 
        or dcpu_dat_lsu or dcpu_we_i)
1202 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1203 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1204 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1205 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1206 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1207 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1208 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1209 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1210 
        endcase
1211 
 
1212 
//
1213 
// When To Compare (Match Condition 2)
1214 
//
1215 
always @(dcr2 or dcpu_cycstb_i)
1216 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1217 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1218 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1219 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1220 
        endcase
1221 
 
1222 
//
1223 
// Match Condition 2
1224 
//
1225 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1226 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1227 
                4'b0_xxx,
1228 
                4'b1_000,
1229 
                4'b1_111: match2 = 1'b0;
1230 
                4'b1_001: match2 =
1231 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
1232 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1233 10 unneback 
                4'b1_010: match2 =
1234 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
1235 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1236 10 unneback 
                4'b1_011: match2 =
1237 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
1238 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1239 10 unneback 
                4'b1_100: match2 =
1240 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
1241 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1242 10 unneback 
                4'b1_101: match2 =
1243 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
1244 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1245 10 unneback 
                4'b1_110: match2 =
1246 141 marcus.erl 
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
1247 
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1248 10 unneback 
        endcase
1249 
 
1250 
//
1251 
// Watchpoint 2
1252 
//
1253 
always @(dmr1 or match2 or wp)
1254 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1255 
                2'b00: wp[2] = match2;
1256 
                2'b01: wp[2] = match2 & wp[1];
1257 
                2'b10: wp[2] = match2 | wp[1];
1258 
                2'b11: wp[2] = 1'b0;
1259 
        endcase
1260 
 
1261 
//
1262 
// Compare To What (Match Condition 3)
1263 
//
1264 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1265 
        or dcpu_dat_lsu or dcpu_we_i)
1266 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1267 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1268 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1269 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1270 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1271 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1272 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1273 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1274 
        endcase
1275 
 
1276 
//
1277 
// When To Compare (Match Condition 3)
1278 
//
1279 
always @(dcr3 or dcpu_cycstb_i)
1280 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1281 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1282 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1283 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1284 
        endcase
1285 
 
1286 
//
1287 
// Match Condition 3
1288 
//
1289 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1290 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1291 
                4'b0_xxx,
1292 
                4'b1_000,
1293 
                4'b1_111: match3 = 1'b0;
1294 
                4'b1_001: match3 =
1295 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
1296 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1297 10 unneback 
                4'b1_010: match3 =
1298 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
1299 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1300 10 unneback 
                4'b1_011: match3 =
1301 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
1302 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1303 10 unneback 
                4'b1_100: match3 =
1304 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
1305 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1306 10 unneback 
                4'b1_101: match3 =
1307 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
1308 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1309 10 unneback 
                4'b1_110: match3 =
1310 141 marcus.erl 
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
1311 
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1312 10 unneback 
        endcase
1313 
 
1314 
//
1315 
// Watchpoint 3
1316 
//
1317 
always @(dmr1 or match3 or wp)
1318 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1319 
                2'b00: wp[3] = match3;
1320 
                2'b01: wp[3] = match3 & wp[2];
1321 
                2'b10: wp[3] = match3 | wp[2];
1322 
                2'b11: wp[3] = 1'b0;
1323 
        endcase
1324 
 
1325 
//
1326 
// Compare To What (Match Condition 4)
1327 
//
1328 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1329 
        or dcpu_dat_lsu or dcpu_we_i)
1330 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1331 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1332 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1333 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1334 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1335 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1336 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1337 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1338 
        endcase
1339 
 
1340 
//
1341 
// When To Compare (Match Condition 4)
1342 
//
1343 
always @(dcr4 or dcpu_cycstb_i)
1344 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1345 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1346 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1347 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1348 
        endcase
1349 
 
1350 
//
1351 
// Match Condition 4
1352 
//
1353 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1354 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1355 
                4'b0_xxx,
1356 
                4'b1_000,
1357 
                4'b1_111: match4 = 1'b0;
1358 
                4'b1_001: match4 =
1359 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
1360 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1361 10 unneback 
                4'b1_010: match4 =
1362 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
1363 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1364 10 unneback 
                4'b1_011: match4 =
1365 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
1366 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1367 10 unneback 
                4'b1_100: match4 =
1368 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
1369 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1370 10 unneback 
                4'b1_101: match4 =
1371 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
1372 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1373 10 unneback 
                4'b1_110: match4 =
1374 141 marcus.erl 
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
1375 
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1376 10 unneback 
        endcase
1377 
 
1378 
//
1379 
// Watchpoint 4
1380 
//
1381 
always @(dmr1 or match4 or wp)
1382 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1383 
                2'b00: wp[4] = match4;
1384 
                2'b01: wp[4] = match4 & wp[3];
1385 
                2'b10: wp[4] = match4 | wp[3];
1386 
                2'b11: wp[4] = 1'b0;
1387 
        endcase
1388 
 
1389 
//
1390 
// Compare To What (Match Condition 5)
1391 
//
1392 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1393 
        or dcpu_dat_lsu or dcpu_we_i)
1394 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1395 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1396 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1397 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1398 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1399 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1400 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1401 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1402 
        endcase
1403 
 
1404 
//
1405 
// When To Compare (Match Condition 5)
1406 
//
1407 
always @(dcr5 or dcpu_cycstb_i)
1408 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1409 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1410 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1411 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1412 
        endcase
1413 
 
1414 
//
1415 
// Match Condition 5
1416 
//
1417 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1418 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1419 
                4'b0_xxx,
1420 
                4'b1_000,
1421 
                4'b1_111: match5 = 1'b0;
1422 
                4'b1_001: match5 =
1423 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
1424 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1425 10 unneback 
                4'b1_010: match5 =
1426 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
1427 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1428 10 unneback 
                4'b1_011: match5 =
1429 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
1430 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1431 10 unneback 
                4'b1_100: match5 =
1432 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
1433 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1434 10 unneback 
                4'b1_101: match5 =
1435 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
1436 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1437 10 unneback 
                4'b1_110: match5 =
1438 141 marcus.erl 
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
1439 
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1440 10 unneback 
        endcase
1441 
 
1442 
//
1443 
// Watchpoint 5
1444 
//
1445 
always @(dmr1 or match5 or wp)
1446 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1447 
                2'b00: wp[5] = match5;
1448 
                2'b01: wp[5] = match5 & wp[4];
1449 
                2'b10: wp[5] = match5 | wp[4];
1450 
                2'b11: wp[5] = 1'b0;
1451 
        endcase
1452 
 
1453 
//
1454 
// Compare To What (Match Condition 6)
1455 
//
1456 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1457 
        or dcpu_dat_lsu or dcpu_we_i)
1458 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1459 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1460 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1461 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1462 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1463 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1464 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1465 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1466 
        endcase
1467 
 
1468 
//
1469 
// When To Compare (Match Condition 6)
1470 
//
1471 
always @(dcr6 or dcpu_cycstb_i)
1472 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1473 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1474 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1475 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1476 
        endcase
1477 
 
1478 
//
1479 
// Match Condition 6
1480 
//
1481 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1482 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1483 
                4'b0_xxx,
1484 
                4'b1_000,
1485 
                4'b1_111: match6 = 1'b0;
1486 
                4'b1_001: match6 =
1487 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
1488 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1489 10 unneback 
                4'b1_010: match6 =
1490 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
1491 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1492 10 unneback 
                4'b1_011: match6 =
1493 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
1494 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1495 10 unneback 
                4'b1_100: match6 =
1496 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
1497 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1498 10 unneback 
                4'b1_101: match6 =
1499 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
1500 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1501 10 unneback 
                4'b1_110: match6 =
1502 141 marcus.erl 
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
1503 
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1504 10 unneback 
        endcase
1505 
 
1506 
//
1507 
// Watchpoint 6
1508 
//
1509 
always @(dmr1 or match6 or wp)
1510 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1511 
                2'b00: wp[6] = match6;
1512 
                2'b01: wp[6] = match6 & wp[5];
1513 
                2'b10: wp[6] = match6 | wp[5];
1514 
                2'b11: wp[6] = 1'b0;
1515 
        endcase
1516 
 
1517 
//
1518 
// Compare To What (Match Condition 7)
1519 
//
1520 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1521 
        or dcpu_dat_lsu or dcpu_we_i)
1522 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1523 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1524 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1525 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1526 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1527 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1528 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1529 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1530 
        endcase
1531 
 
1532 
//
1533 
// When To Compare (Match Condition 7)
1534 
//
1535 
always @(dcr7 or dcpu_cycstb_i)
1536 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1537 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1538 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1539 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1540 
        endcase
1541 
 
1542 
//
1543 
// Match Condition 7
1544 
//
1545 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1546 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1547 
                4'b0_xxx,
1548 
                4'b1_000,
1549 
                4'b1_111: match7 = 1'b0;
1550 
                4'b1_001: match7 =
1551 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
1552 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1553 10 unneback 
                4'b1_010: match7 =
1554 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
1555 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1556 10 unneback 
                4'b1_011: match7 =
1557 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
1558 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1559 10 unneback 
                4'b1_100: match7 =
1560 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
1561 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1562 10 unneback 
                4'b1_101: match7 =
1563 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
1564 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1565 10 unneback 
                4'b1_110: match7 =
1566 141 marcus.erl 
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
1567 
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1568 10 unneback 
        endcase
1569 
 
1570 
//
1571 
// Watchpoint 7
1572 
//
1573 
always @(dmr1 or match7 or wp)
1574 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1575 
                2'b00: wp[7] = match7;
1576 
                2'b01: wp[7] = match7 & wp[6];
1577 
                2'b10: wp[7] = match7 | wp[6];
1578 
                2'b11: wp[7] = 1'b0;
1579 
        endcase
1580 
 
1581 
//
1582 
// Increment Watchpoint Counter 0
1583 
//
1584 
always @(wp or dmr2)
1585 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1586 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1587 
        else
1588 
                incr_wpcntr0 = 1'b0;
1589 
 
1590 
//
1591 
// Match Condition Watchpoint Counter 0
1592 
//
1593 
always @(dwcr0)
1594 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1595 
                wpcntr0_match = 1'b1;
1596 
        else
1597 
                wpcntr0_match = 1'b0;
1598 
 
1599 
 
1600 
//
1601 
// Watchpoint 8
1602 
//
1603 
always @(dmr1 or wpcntr0_match or wp)
1604 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1605 
                2'b00: wp[8] = wpcntr0_match;
1606 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1607 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1608 
                2'b11: wp[8] = 1'b0;
1609 
        endcase
1610 
 
1611 
 
1612 
//
1613 
// Increment Watchpoint Counter 1
1614 
//
1615 
always @(wp or dmr2)
1616 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1617 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1618 
        else
1619 
                incr_wpcntr1 = 1'b0;
1620 
 
1621 
//
1622 
// Match Condition Watchpoint Counter 1
1623 
//
1624 
always @(dwcr1)
1625 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1626 
                wpcntr1_match = 1'b1;
1627 
        else
1628 
                wpcntr1_match = 1'b0;
1629 
 
1630 
//
1631 
// Watchpoint 9
1632 
//
1633 
always @(dmr1 or wpcntr1_match or wp)
1634 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1635 
                2'b00: wp[9] = wpcntr1_match;
1636 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1637 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1638 
                2'b11: wp[9] = 1'b0;
1639 
        endcase
1640 
 
1641 
//
1642 
// Watchpoint 10
1643 
//
1644 
always @(dmr1 or dbg_ewt_i or wp)
1645 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1646 
                2'b00: wp[10] = dbg_ewt_i;
1647 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1648 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1649 
                2'b11: wp[10] = 1'b0;
1650 
        endcase
1651 
 
1652 
`endif
1653 
 
1654 
//
1655 
// Watchpoints can cause trap exception
1656 
//
1657 
`ifdef OR1200_DU_HWBKPTS
1658 141 marcus.erl 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
1659 10 unneback 
`else
1660 
assign du_hwbkpt = 1'b0;
1661 
`endif
1662 
 
1663 141 marcus.erl 
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception
1664 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1665 
        if (rst == `OR1200_RST_VALUE)
1666 258 julius 
                du_hwbkpt_hold <=  1'b0;
1667 141 marcus.erl 
        else if (du_hwbkpt & ex_freeze)
1668 258 julius 
                du_hwbkpt_hold <=  1'b1;
1669 141 marcus.erl 
        else if (!ex_freeze)
1670 258 julius 
                du_hwbkpt_hold <=  1'b0;
1671 141 marcus.erl 
 
1672 10 unneback 
`ifdef OR1200_DU_TB_IMPLEMENTED
1673 
//
1674 
// Simple trace buffer
1675 
// (right now hardcoded for Xilinx Virtex FPGAs)
1676 
//
1677 
// Stores last 256 instruction addresses, instruction
1678 
// machine words and ALU results
1679 
//
1680 
 
1681 
//
1682 
// Trace buffer write enable
1683 
//
1684 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1685 
 
1686 
//
1687 
// Trace buffer write address pointer
1688 
//
1689 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1690 
        if (rst == `OR1200_RST_VALUE)
1691 258 julius 
                tb_wadr <=  8'h00;
1692 10 unneback 
        else if (tb_enw)
1693 258 julius 
                tb_wadr <=  tb_wadr + 8'd1;
1694 10 unneback 
 
1695 
//
1696 
// Free running counter (time stamp)
1697 
//
1698 358 julius 
always @(posedge clk or `OR1200_RST_EVENT rst)
1699 
        if (rst == `OR1200_RST_VALUE)
1700 258 julius 
                tb_timstmp <=  32'h00000000;
1701 10 unneback 
        else if (!dbg_bp_r)
1702 258 julius 
                tb_timstmp <=  tb_timstmp + 32'd1;
1703 10 unneback 
 
1704 
//
1705 
// Trace buffer RAMs
1706 
//
1707 
 
1708 
or1200_dpram_256x32 tbia_ram(
1709 
        .clk_a(clk),
1710 141 marcus.erl 
        .rst_a(1'b0),
1711 10 unneback 
        .addr_a(spr_addr[7:0]),
1712 
        .ce_a(1'b1),
1713 
        .oe_a(1'b1),
1714 
        .do_a(tbia_dat_o),
1715 
 
1716 
        .clk_b(clk),
1717 141 marcus.erl 
        .rst_b(1'b0),
1718 10 unneback 
        .addr_b(tb_wadr),
1719 
        .di_b(spr_dat_npc),
1720 
        .ce_b(1'b1),
1721 
        .we_b(tb_enw)
1722 
 
1723 
);
1724 
 
1725 
or1200_dpram_256x32 tbim_ram(
1726 
        .clk_a(clk),
1727 141 marcus.erl 
        .rst_a(1'b0),
1728 10 unneback 
        .addr_a(spr_addr[7:0]),
1729 
        .ce_a(1'b1),
1730 
        .oe_a(1'b1),
1731 
        .do_a(tbim_dat_o),
1732 
 
1733 
        .clk_b(clk),
1734 141 marcus.erl 
        .rst_b(1'b0),
1735 10 unneback 
        .addr_b(tb_wadr),
1736 
        .di_b(ex_insn),
1737 
        .ce_b(1'b1),
1738 
        .we_b(tb_enw)
1739 
);
1740 
 
1741 
or1200_dpram_256x32 tbar_ram(
1742 
        .clk_a(clk),
1743 141 marcus.erl 
        .rst_a(1'b0),
1744 10 unneback 
        .addr_a(spr_addr[7:0]),
1745 
        .ce_a(1'b1),
1746 
        .oe_a(1'b1),
1747 
        .do_a(tbar_dat_o),
1748 
 
1749 
        .clk_b(clk),
1750 141 marcus.erl 
        .rst_b(1'b0),
1751 10 unneback 
        .addr_b(tb_wadr),
1752 
        .di_b(rf_dataw),
1753 
        .ce_b(1'b1),
1754 
        .we_b(tb_enw)
1755 
);
1756 
 
1757 
or1200_dpram_256x32 tbts_ram(
1758 
        .clk_a(clk),
1759 141 marcus.erl 
        .rst_a(1'b0),
1760 10 unneback 
        .addr_a(spr_addr[7:0]),
1761 
        .ce_a(1'b1),
1762 
        .oe_a(1'b1),
1763 
        .do_a(tbts_dat_o),
1764 
 
1765 
        .clk_b(clk),
1766 141 marcus.erl 
        .rst_b(1'b0),
1767 10 unneback 
        .addr_b(tb_wadr),
1768 
        .di_b(tb_timstmp),
1769 
        .ce_b(1'b1),
1770 
        .we_b(tb_enw)
1771 
);
1772 
 
1773 
`else
1774 
 
1775 
assign tbia_dat_o = 32'h0000_0000;
1776 
assign tbim_dat_o = 32'h0000_0000;
1777 
assign tbar_dat_o = 32'h0000_0000;
1778 
assign tbts_dat_o = 32'h0000_0000;
1779 
 
1780 
`endif  // OR1200_DU_TB_IMPLEMENTED
1781 
 
1782 
`else   // OR1200_DU_IMPLEMENTED
1783 
 
1784 
//
1785 
// When DU is not implemented, drive all outputs as would when DU is disabled
1786 
//
1787 
assign dbg_bp_o = 1'b0;
1788 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1789 141 marcus.erl 
assign du_dmr1 = {25{1'b0}};
1790 10 unneback 
assign du_hwbkpt = 1'b0;
1791 
 
1792 
//
1793 
// Read DU registers
1794 
//
1795 
`ifdef OR1200_DU_READREGS
1796 
assign spr_dat_o = 32'h0000_0000;
1797 
`ifdef OR1200_DU_UNUSED_ZERO
1798 
`endif
1799 
`endif
1800 
 
1801 
`endif
1802 
 
1803 
endmodule

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