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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Debug Unit                                         ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Basic OR1200 debug unit.                                    ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_du.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Bugs fixed. 
50
//
51
// Revision 1.12  2005/10/19 11:37:56  jcastillo
52
// Added support for RAMB16 Xilinx4/Spartan3 primitives
53
//
54 10 unneback
// Revision 1.11  2005/01/07 09:35:08  andreje
55
// du_hwbkpt disabled when debug unit not implemented
56
//
57
// Revision 1.10  2004/04/05 08:29:57  lampret
58
// Merged branch_qmem into main tree.
59
//
60
// Revision 1.9.4.4  2004/02/11 01:40:11  lampret
61
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
62
//
63
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
64
// Error fixed.
65
//
66
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
67
// Errors fixed.
68
//
69
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
70
// interface to debug changed; no more opselect; stb-ack protocol
71
//
72
// Revision 1.9  2003/01/22 03:23:47  lampret
73
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
74
//
75
// Revision 1.8  2002/09/08 19:31:52  lampret
76
// Fixed a typo, reported by Taylor Su.
77
//
78
// Revision 1.7  2002/07/14 22:17:17  lampret
79
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
80
//
81
// Revision 1.6  2002/03/14 00:30:24  lampret
82
// Added alternative for critical path in DU.
83
//
84
// Revision 1.5  2002/02/11 04:33:17  lampret
85
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
86
//
87
// Revision 1.4  2002/01/28 01:16:00  lampret
88
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
89
//
90
// Revision 1.3  2002/01/18 07:56:00  lampret
91
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
92
//
93
// Revision 1.2  2002/01/14 06:18:22  lampret
94
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
95
//
96
// Revision 1.1  2002/01/03 08:16:15  lampret
97
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
98
//
99
// Revision 1.12  2001/11/30 18:58:00  simons
100
// Trap insn couses break after exits ex_insn.
101
//
102
// Revision 1.11  2001/11/23 08:38:51  lampret
103
// Changed DSR/DRR behavior and exception detection.
104
//
105
// Revision 1.10  2001/11/20 21:25:44  lampret
106
// Fixed dbg_is_o assignment width.
107
//
108
// Revision 1.9  2001/11/20 18:46:14  simons
109
// Break point bug fixed
110
//
111
// Revision 1.8  2001/11/18 08:36:28  lampret
112
// For GDB changed single stepping and disabled trap exception.
113
//
114
// Revision 1.7  2001/10/21 18:09:53  lampret
115
// Fixed sensitivity list.
116
//
117
// Revision 1.6  2001/10/14 13:12:09  lampret
118
// MP3 version.
119
//
120
//
121
 
122
// synopsys translate_off
123
`include "timescale.v"
124
// synopsys translate_on
125
`include "or1200_defines.v"
126
 
127
//
128
// Debug unit
129
//
130
 
131
module or1200_du(
132
        // RISC Internal Interface
133
        clk, rst,
134
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
135
        dcpu_dat_dc, icpu_cycstb_i,
136
        ex_freeze, branch_op, ex_insn, id_pc,
137
        spr_dat_npc, rf_dataw,
138 141 marcus.erl
        du_dsr, du_dmr1, du_stall, du_addr, du_dat_i, du_dat_o,
139
        du_read, du_write, du_except_stop, du_hwbkpt,
140 10 unneback
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
141
 
142
        // External Debug Interface
143
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
144
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
145
);
146
 
147
parameter dw = `OR1200_OPERAND_WIDTH;
148
parameter aw = `OR1200_OPERAND_WIDTH;
149
 
150
//
151
// I/O
152
//
153
 
154
//
155
// RISC Internal Interface
156
//
157
input                           clk;            // Clock
158
input                           rst;            // Reset
159
input                           dcpu_cycstb_i;  // LSU status
160
input                           dcpu_we_i;      // LSU status
161
input   [31:0]                   dcpu_adr_i;     // LSU addr
162
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
163
input   [31:0]                   dcpu_dat_dc;    // LSU load data
164
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
165
input                           ex_freeze;      // EX stage freeze
166
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
167
input   [dw-1:0]         ex_insn;        // EX insn
168
input   [31:0]                   id_pc;          // insn fetch EA
169
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
170
input   [31:0]                   rf_dataw;       // ALU result (for trace)
171
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
172 141 marcus.erl
output  [24: 0]                  du_dmr1;
173 10 unneback
output                          du_stall;       // Debug Unit Stall
174
output  [aw-1:0]         du_addr;        // Debug Unit Address
175
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
176
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
177
output                          du_read;        // Debug Unit Read Enable
178
output                          du_write;       // Debug Unit Write Enable
179 141 marcus.erl
input   [12:0]                   du_except_stop; // Exception masked by DSR
180 10 unneback
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
181
input                           spr_cs;         // SPR Chip Select
182
input                           spr_write;      // SPR Read/Write
183
input   [aw-1:0]         spr_addr;       // SPR Address
184
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
185
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
186
 
187
//
188
// External Debug Interface
189
//
190
input                   dbg_stall_i;    // External Stall Input
191
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
192
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
193
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
194
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
195
output                  dbg_bp_o;       // Breakpoint Output
196
input                   dbg_stb_i;      // External Address/Data Strobe
197
input                   dbg_we_i;       // External Write Enable
198
input   [aw-1:0] dbg_adr_i;      // External Address Input
199
input   [dw-1:0] dbg_dat_i;      // External Data Input
200
output  [dw-1:0] dbg_dat_o;      // External Data Output
201
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
202 141 marcus.erl
reg     [dw-1:0] dbg_dat_o;      // External Data Output
203
reg                     dbg_ack_o;      // External Data Acknowledge (not WB compatible)
204 10 unneback
 
205
 
206
//
207
// Some connections go directly from the CPU through DU to Debug I/F
208
//
209
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
210
assign dbg_lss_o = 4'b0000;
211
 
212
reg     [1:0]                    dbg_is_o;
213
//
214
// Show insn activity (temp, must be removed)
215
//
216
always @(posedge clk or posedge rst)
217
        if (rst)
218
                dbg_is_o <= #1 2'b00;
219 141 marcus.erl
        else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
220 10 unneback
                dbg_is_o <= #1 ~dbg_is_o;
221
`ifdef UNUSED
222
assign dbg_is_o = 2'b00;
223
`endif
224
`else
225
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
226
assign dbg_is_o = {1'b0, icpu_cycstb_i};
227
`endif
228
assign dbg_wp_o = 11'b000_0000_0000;
229
 
230
//
231
// Some connections go directly from Debug I/F through DU to the CPU
232
//
233
assign du_stall = dbg_stall_i;
234
assign du_addr = dbg_adr_i;
235
assign du_dat_o = dbg_dat_i;
236
assign du_read = dbg_stb_i && !dbg_we_i;
237
assign du_write = dbg_stb_i && dbg_we_i;
238
 
239 141 marcus.erl
reg                             dbg_ack;
240 10 unneback
//
241
// Generate acknowledge -- just delay stb signal
242
//
243 141 marcus.erl
always @(posedge clk or posedge rst) begin
244
        if (rst) begin
245
                dbg_ack   <= #1 1'b0;
246 10 unneback
                dbg_ack_o <= #1 1'b0;
247 141 marcus.erl
        end
248
        else begin
249
                dbg_ack   <= #1 dbg_stb_i;              // valid when du_dat_i 
250
                dbg_ack_o <= #1 dbg_ack & dbg_stb_i;    // valid when dbg_dat_o 
251
        end
252
end
253 10 unneback
 
254 141 marcus.erl
// 
255
// Register data output
256
//
257
always @(posedge clk)
258
    dbg_dat_o <= #1 du_dat_i;
259
 
260 10 unneback
`ifdef OR1200_DU_IMPLEMENTED
261
 
262
//
263
// Debug Mode Register 1
264
//
265
`ifdef OR1200_DU_DMR1
266
reg     [24:0]                   dmr1;           // DMR1 implemented
267
`else
268
wire    [24:0]                   dmr1;           // DMR1 not implemented
269
`endif
270 141 marcus.erl
assign du_dmr1 = dmr1;
271 10 unneback
 
272
//
273
// Debug Mode Register 2
274
//
275
`ifdef OR1200_DU_DMR2
276
reg     [23:0]                   dmr2;           // DMR2 implemented
277
`else
278
wire    [23:0]                   dmr2;           // DMR2 not implemented
279
`endif
280
 
281
//
282
// Debug Stop Register
283
//
284
`ifdef OR1200_DU_DSR
285
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
286
`else
287
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
288
`endif
289
 
290
//
291
// Debug Reason Register
292
//
293
`ifdef OR1200_DU_DRR
294
reg     [13:0]                   drr;            // DRR implemented
295
`else
296
wire    [13:0]                   drr;            // DRR not implemented
297
`endif
298
 
299
//
300
// Debug Value Register N
301
//
302
`ifdef OR1200_DU_DVR0
303
reg     [31:0]                   dvr0;
304
`else
305
wire    [31:0]                   dvr0;
306
`endif
307
 
308
//
309
// Debug Value Register N
310
//
311
`ifdef OR1200_DU_DVR1
312
reg     [31:0]                   dvr1;
313
`else
314
wire    [31:0]                   dvr1;
315
`endif
316
 
317
//
318
// Debug Value Register N
319
//
320
`ifdef OR1200_DU_DVR2
321
reg     [31:0]                   dvr2;
322
`else
323
wire    [31:0]                   dvr2;
324
`endif
325
 
326
//
327
// Debug Value Register N
328
//
329
`ifdef OR1200_DU_DVR3
330
reg     [31:0]                   dvr3;
331
`else
332
wire    [31:0]                   dvr3;
333
`endif
334
 
335
//
336
// Debug Value Register N
337
//
338
`ifdef OR1200_DU_DVR4
339
reg     [31:0]                   dvr4;
340
`else
341
wire    [31:0]                   dvr4;
342
`endif
343
 
344
//
345
// Debug Value Register N
346
//
347
`ifdef OR1200_DU_DVR5
348
reg     [31:0]                   dvr5;
349
`else
350
wire    [31:0]                   dvr5;
351
`endif
352
 
353
//
354
// Debug Value Register N
355
//
356
`ifdef OR1200_DU_DVR6
357
reg     [31:0]                   dvr6;
358
`else
359
wire    [31:0]                   dvr6;
360
`endif
361
 
362
//
363
// Debug Value Register N
364
//
365
`ifdef OR1200_DU_DVR7
366
reg     [31:0]                   dvr7;
367
`else
368
wire    [31:0]                   dvr7;
369
`endif
370
 
371
//
372
// Debug Control Register N
373
//
374
`ifdef OR1200_DU_DCR0
375
reg     [7:0]                    dcr0;
376
`else
377
wire    [7:0]                    dcr0;
378
`endif
379
 
380
//
381
// Debug Control Register N
382
//
383
`ifdef OR1200_DU_DCR1
384
reg     [7:0]                    dcr1;
385
`else
386
wire    [7:0]                    dcr1;
387
`endif
388
 
389
//
390
// Debug Control Register N
391
//
392
`ifdef OR1200_DU_DCR2
393
reg     [7:0]                    dcr2;
394
`else
395
wire    [7:0]                    dcr2;
396
`endif
397
 
398
//
399
// Debug Control Register N
400
//
401
`ifdef OR1200_DU_DCR3
402
reg     [7:0]                    dcr3;
403
`else
404
wire    [7:0]                    dcr3;
405
`endif
406
 
407
//
408
// Debug Control Register N
409
//
410
`ifdef OR1200_DU_DCR4
411
reg     [7:0]                    dcr4;
412
`else
413
wire    [7:0]                    dcr4;
414
`endif
415
 
416
//
417
// Debug Control Register N
418
//
419
`ifdef OR1200_DU_DCR5
420
reg     [7:0]                    dcr5;
421
`else
422
wire    [7:0]                    dcr5;
423
`endif
424
 
425
//
426
// Debug Control Register N
427
//
428
`ifdef OR1200_DU_DCR6
429
reg     [7:0]                    dcr6;
430
`else
431
wire    [7:0]                    dcr6;
432
`endif
433
 
434
//
435
// Debug Control Register N
436
//
437
`ifdef OR1200_DU_DCR7
438
reg     [7:0]                    dcr7;
439
`else
440
wire    [7:0]                    dcr7;
441
`endif
442
 
443
//
444
// Debug Watchpoint Counter Register 0
445
//
446
`ifdef OR1200_DU_DWCR0
447
reg     [31:0]                   dwcr0;
448
`else
449
wire    [31:0]                   dwcr0;
450
`endif
451
 
452
//
453
// Debug Watchpoint Counter Register 1
454
//
455
`ifdef OR1200_DU_DWCR1
456
reg     [31:0]                   dwcr1;
457
`else
458
wire    [31:0]                   dwcr1;
459
`endif
460
 
461
//
462
// Internal wires
463
//
464
wire                            dmr1_sel;       // DMR1 select
465
wire                            dmr2_sel;       // DMR2 select
466
wire                            dsr_sel;        // DSR select
467
wire                            drr_sel;        // DRR select
468
wire                            dvr0_sel,
469
                                dvr1_sel,
470
                                dvr2_sel,
471
                                dvr3_sel,
472
                                dvr4_sel,
473
                                dvr5_sel,
474
                                dvr6_sel,
475
                                dvr7_sel;       // DVR selects
476
wire                            dcr0_sel,
477
                                dcr1_sel,
478
                                dcr2_sel,
479
                                dcr3_sel,
480
                                dcr4_sel,
481
                                dcr5_sel,
482
                                dcr6_sel,
483
                                dcr7_sel;       // DCR selects
484
wire                            dwcr0_sel,
485
                                dwcr1_sel;      // DWCR selects
486
reg                             dbg_bp_r;
487
`ifdef OR1200_DU_HWBKPTS
488
reg     [31:0]                   match_cond0_ct;
489
reg     [31:0]                   match_cond1_ct;
490
reg     [31:0]                   match_cond2_ct;
491
reg     [31:0]                   match_cond3_ct;
492
reg     [31:0]                   match_cond4_ct;
493
reg     [31:0]                   match_cond5_ct;
494
reg     [31:0]                   match_cond6_ct;
495
reg     [31:0]                   match_cond7_ct;
496
reg                             match_cond0_stb;
497
reg                             match_cond1_stb;
498
reg                             match_cond2_stb;
499
reg                             match_cond3_stb;
500
reg                             match_cond4_stb;
501
reg                             match_cond5_stb;
502
reg                             match_cond6_stb;
503
reg                             match_cond7_stb;
504
reg                             match0;
505
reg                             match1;
506
reg                             match2;
507
reg                             match3;
508
reg                             match4;
509
reg                             match5;
510
reg                             match6;
511
reg                             match7;
512
reg                             wpcntr0_match;
513
reg                             wpcntr1_match;
514
reg                             incr_wpcntr0;
515
reg                             incr_wpcntr1;
516
reg     [10:0]                   wp;
517
`endif
518
wire                            du_hwbkpt;
519 141 marcus.erl
reg                             du_hwbkpt_hold;
520 10 unneback
`ifdef OR1200_DU_READREGS
521
reg     [31:0]                   spr_dat_o;
522
`endif
523
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
524
`ifdef OR1200_DU_TB_IMPLEMENTED
525
wire                            tb_enw;
526
reg     [7:0]                    tb_wadr;
527
reg [31:0]                       tb_timstmp;
528
`endif
529
wire    [31:0]                   tbia_dat_o;
530
wire    [31:0]                   tbim_dat_o;
531
wire    [31:0]                   tbar_dat_o;
532
wire    [31:0]                   tbts_dat_o;
533
 
534
//
535
// DU registers address decoder
536
//
537
`ifdef OR1200_DU_DMR1
538
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
539
`endif
540
`ifdef OR1200_DU_DMR2
541
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
542
`endif
543
`ifdef OR1200_DU_DSR
544
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
545
`endif
546
`ifdef OR1200_DU_DRR
547
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
548
`endif
549
`ifdef OR1200_DU_DVR0
550
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
551
`endif
552
`ifdef OR1200_DU_DVR1
553
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
554
`endif
555
`ifdef OR1200_DU_DVR2
556
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
557
`endif
558
`ifdef OR1200_DU_DVR3
559
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
560
`endif
561
`ifdef OR1200_DU_DVR4
562
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
563
`endif
564
`ifdef OR1200_DU_DVR5
565
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
566
`endif
567
`ifdef OR1200_DU_DVR6
568
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
569
`endif
570
`ifdef OR1200_DU_DVR7
571
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
572
`endif
573
`ifdef OR1200_DU_DCR0
574
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
575
`endif
576
`ifdef OR1200_DU_DCR1
577
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
578
`endif
579
`ifdef OR1200_DU_DCR2
580
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
581
`endif
582
`ifdef OR1200_DU_DCR3
583
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
584
`endif
585
`ifdef OR1200_DU_DCR4
586
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
587
`endif
588
`ifdef OR1200_DU_DCR5
589
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
590
`endif
591
`ifdef OR1200_DU_DCR6
592
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
593
`endif
594
`ifdef OR1200_DU_DCR7
595
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
596
`endif
597
`ifdef OR1200_DU_DWCR0
598
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
599
`endif
600
`ifdef OR1200_DU_DWCR1
601
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
602
`endif
603
 
604
//
605
// Decode started exception
606
//
607 141 marcus.erl
always @(du_except_stop) begin
608 10 unneback
        except_stop = 14'b0000_0000_0000;
609 141 marcus.erl
        casex (du_except_stop)
610
                13'b1_xxxx_xxxx_xxxx: begin
611 10 unneback
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
612 141 marcus.erl
                end
613 10 unneback
                13'b0_1xxx_xxxx_xxxx: begin
614
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
615
                end
616
                13'b0_01xx_xxxx_xxxx: begin
617
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
618
                end
619 141 marcus.erl
                13'b0_001x_xxxx_xxxx: begin
620 10 unneback
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
621 141 marcus.erl
                end
622 10 unneback
                13'b0_0001_xxxx_xxxx: begin
623
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
624
                end
625 141 marcus.erl
                13'b0_0000_1xxx_xxxx: begin
626 10 unneback
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
627 141 marcus.erl
                end
628 10 unneback
                13'b0_0000_01xx_xxxx: begin
629
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
630
                end
631
                13'b0_0000_001x_xxxx: begin
632
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
633
                end
634 141 marcus.erl
                13'b0_0000_0001_xxxx: begin
635 10 unneback
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
636 141 marcus.erl
                end
637
                13'b0_0000_0000_1xxx: begin
638 10 unneback
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
639 141 marcus.erl
                end
640 10 unneback
                13'b0_0000_0000_01xx: begin
641
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
642
                end
643
                13'b0_0000_0000_001x: begin
644
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
645
                end
646 141 marcus.erl
                13'b0_0000_0000_0001: begin
647 10 unneback
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
648 141 marcus.erl
                end
649 10 unneback
                default:
650
                        except_stop = 14'b0000_0000_0000;
651
        endcase
652
end
653
 
654
//
655
// dbg_bp_o is registered
656
//
657
assign dbg_bp_o = dbg_bp_r;
658
 
659
//
660
// Breakpoint activation register
661
//
662
always @(posedge clk or posedge rst)
663
        if (rst)
664
                dbg_bp_r <= #1 1'b0;
665
        else if (!ex_freeze)
666
                dbg_bp_r <= #1 |except_stop
667
`ifdef OR1200_DU_DMR1_ST
668
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
669
`endif
670
`ifdef OR1200_DU_DMR1_BT
671 141 marcus.erl
                        | (branch_op != `OR1200_BRANCHOP_NOP) & (branch_op != `OR1200_BRANCHOP_RFE) & dmr1[`OR1200_DU_DMR1_BT]
672 10 unneback
`endif
673
                        ;
674
        else
675
                dbg_bp_r <= #1 |except_stop;
676
 
677
//
678
// Write to DMR1
679
//
680
`ifdef OR1200_DU_DMR1
681
always @(posedge clk or posedge rst)
682
        if (rst)
683
                dmr1 <= 25'h000_0000;
684
        else if (dmr1_sel && spr_write)
685
`ifdef OR1200_DU_HWBKPTS
686
                dmr1 <= #1 spr_dat_i[24:0];
687
`else
688
                dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
689
`endif
690
`else
691
assign dmr1 = 25'h000_0000;
692
`endif
693
 
694
//
695
// Write to DMR2
696
//
697
`ifdef OR1200_DU_DMR2
698
always @(posedge clk or posedge rst)
699
        if (rst)
700
                dmr2 <= 24'h00_0000;
701
        else if (dmr2_sel && spr_write)
702
                dmr2 <= #1 spr_dat_i[23:0];
703
`else
704
assign dmr2 = 24'h00_0000;
705
`endif
706
 
707
//
708
// Write to DSR
709
//
710
`ifdef OR1200_DU_DSR
711
always @(posedge clk or posedge rst)
712
        if (rst)
713
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
714
        else if (dsr_sel && spr_write)
715
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
716
`else
717
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
718
`endif
719
 
720
//
721
// Write to DRR
722
//
723
`ifdef OR1200_DU_DRR
724
always @(posedge clk or posedge rst)
725
        if (rst)
726
                drr <= 14'b0;
727
        else if (drr_sel && spr_write)
728
                drr <= #1 spr_dat_i[13:0];
729
        else
730
                drr <= #1 drr | except_stop;
731
`else
732
assign drr = 14'b0;
733
`endif
734
 
735
//
736
// Write to DVR0
737
//
738
`ifdef OR1200_DU_DVR0
739
always @(posedge clk or posedge rst)
740
        if (rst)
741
                dvr0 <= 32'h0000_0000;
742
        else if (dvr0_sel && spr_write)
743
                dvr0 <= #1 spr_dat_i[31:0];
744
`else
745
assign dvr0 = 32'h0000_0000;
746
`endif
747
 
748
//
749
// Write to DVR1
750
//
751
`ifdef OR1200_DU_DVR1
752
always @(posedge clk or posedge rst)
753
        if (rst)
754
                dvr1 <= 32'h0000_0000;
755
        else if (dvr1_sel && spr_write)
756
                dvr1 <= #1 spr_dat_i[31:0];
757
`else
758
assign dvr1 = 32'h0000_0000;
759
`endif
760
 
761
//
762
// Write to DVR2
763
//
764
`ifdef OR1200_DU_DVR2
765
always @(posedge clk or posedge rst)
766
        if (rst)
767
                dvr2 <= 32'h0000_0000;
768
        else if (dvr2_sel && spr_write)
769
                dvr2 <= #1 spr_dat_i[31:0];
770
`else
771
assign dvr2 = 32'h0000_0000;
772
`endif
773
 
774
//
775
// Write to DVR3
776
//
777
`ifdef OR1200_DU_DVR3
778
always @(posedge clk or posedge rst)
779
        if (rst)
780
                dvr3 <= 32'h0000_0000;
781
        else if (dvr3_sel && spr_write)
782
                dvr3 <= #1 spr_dat_i[31:0];
783
`else
784
assign dvr3 = 32'h0000_0000;
785
`endif
786
 
787
//
788
// Write to DVR4
789
//
790
`ifdef OR1200_DU_DVR4
791
always @(posedge clk or posedge rst)
792
        if (rst)
793
                dvr4 <= 32'h0000_0000;
794
        else if (dvr4_sel && spr_write)
795
                dvr4 <= #1 spr_dat_i[31:0];
796
`else
797
assign dvr4 = 32'h0000_0000;
798
`endif
799
 
800
//
801
// Write to DVR5
802
//
803
`ifdef OR1200_DU_DVR5
804
always @(posedge clk or posedge rst)
805
        if (rst)
806
                dvr5 <= 32'h0000_0000;
807
        else if (dvr5_sel && spr_write)
808
                dvr5 <= #1 spr_dat_i[31:0];
809
`else
810
assign dvr5 = 32'h0000_0000;
811
`endif
812
 
813
//
814
// Write to DVR6
815
//
816
`ifdef OR1200_DU_DVR6
817
always @(posedge clk or posedge rst)
818
        if (rst)
819
                dvr6 <= 32'h0000_0000;
820
        else if (dvr6_sel && spr_write)
821
                dvr6 <= #1 spr_dat_i[31:0];
822
`else
823
assign dvr6 = 32'h0000_0000;
824
`endif
825
 
826
//
827
// Write to DVR7
828
//
829
`ifdef OR1200_DU_DVR7
830
always @(posedge clk or posedge rst)
831
        if (rst)
832
                dvr7 <= 32'h0000_0000;
833
        else if (dvr7_sel && spr_write)
834
                dvr7 <= #1 spr_dat_i[31:0];
835
`else
836
assign dvr7 = 32'h0000_0000;
837
`endif
838
 
839
//
840
// Write to DCR0
841
//
842
`ifdef OR1200_DU_DCR0
843
always @(posedge clk or posedge rst)
844
        if (rst)
845
                dcr0 <= 8'h00;
846
        else if (dcr0_sel && spr_write)
847
                dcr0 <= #1 spr_dat_i[7:0];
848
`else
849
assign dcr0 = 8'h00;
850
`endif
851
 
852
//
853
// Write to DCR1
854
//
855
`ifdef OR1200_DU_DCR1
856
always @(posedge clk or posedge rst)
857
        if (rst)
858
                dcr1 <= 8'h00;
859
        else if (dcr1_sel && spr_write)
860
                dcr1 <= #1 spr_dat_i[7:0];
861
`else
862
assign dcr1 = 8'h00;
863
`endif
864
 
865
//
866
// Write to DCR2
867
//
868
`ifdef OR1200_DU_DCR2
869
always @(posedge clk or posedge rst)
870
        if (rst)
871
                dcr2 <= 8'h00;
872
        else if (dcr2_sel && spr_write)
873
                dcr2 <= #1 spr_dat_i[7:0];
874
`else
875
assign dcr2 = 8'h00;
876
`endif
877
 
878
//
879
// Write to DCR3
880
//
881
`ifdef OR1200_DU_DCR3
882
always @(posedge clk or posedge rst)
883
        if (rst)
884
                dcr3 <= 8'h00;
885
        else if (dcr3_sel && spr_write)
886
                dcr3 <= #1 spr_dat_i[7:0];
887
`else
888
assign dcr3 = 8'h00;
889
`endif
890
 
891
//
892
// Write to DCR4
893
//
894
`ifdef OR1200_DU_DCR4
895
always @(posedge clk or posedge rst)
896
        if (rst)
897
                dcr4 <= 8'h00;
898
        else if (dcr4_sel && spr_write)
899
                dcr4 <= #1 spr_dat_i[7:0];
900
`else
901
assign dcr4 = 8'h00;
902
`endif
903
 
904
//
905
// Write to DCR5
906
//
907
`ifdef OR1200_DU_DCR5
908
always @(posedge clk or posedge rst)
909
        if (rst)
910
                dcr5 <= 8'h00;
911
        else if (dcr5_sel && spr_write)
912
                dcr5 <= #1 spr_dat_i[7:0];
913
`else
914
assign dcr5 = 8'h00;
915
`endif
916
 
917
//
918
// Write to DCR6
919
//
920
`ifdef OR1200_DU_DCR6
921
always @(posedge clk or posedge rst)
922
        if (rst)
923
                dcr6 <= 8'h00;
924
        else if (dcr6_sel && spr_write)
925
                dcr6 <= #1 spr_dat_i[7:0];
926
`else
927
assign dcr6 = 8'h00;
928
`endif
929
 
930
//
931
// Write to DCR7
932
//
933
`ifdef OR1200_DU_DCR7
934
always @(posedge clk or posedge rst)
935
        if (rst)
936
                dcr7 <= 8'h00;
937
        else if (dcr7_sel && spr_write)
938
                dcr7 <= #1 spr_dat_i[7:0];
939
`else
940
assign dcr7 = 8'h00;
941
`endif
942
 
943
//
944
// Write to DWCR0
945
//
946
`ifdef OR1200_DU_DWCR0
947
always @(posedge clk or posedge rst)
948
        if (rst)
949
                dwcr0 <= 32'h0000_0000;
950
        else if (dwcr0_sel && spr_write)
951
                dwcr0 <= #1 spr_dat_i[31:0];
952
        else if (incr_wpcntr0)
953
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
954
`else
955
assign dwcr0 = 32'h0000_0000;
956
`endif
957
 
958
//
959
// Write to DWCR1
960
//
961
`ifdef OR1200_DU_DWCR1
962
always @(posedge clk or posedge rst)
963
        if (rst)
964
                dwcr1 <= 32'h0000_0000;
965
        else if (dwcr1_sel && spr_write)
966
                dwcr1 <= #1 spr_dat_i[31:0];
967
        else if (incr_wpcntr1)
968
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
969
`else
970
assign dwcr1 = 32'h0000_0000;
971
`endif
972
 
973
//
974
// Read DU registers
975
//
976
`ifdef OR1200_DU_READREGS
977
always @(spr_addr or dsr or drr or dmr1 or dmr2
978
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
979
        or dvr5 or dvr6 or dvr7
980
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
981
        or dcr5 or dcr6 or dcr7
982
        or dwcr0 or dwcr1
983
`ifdef OR1200_DU_TB_IMPLEMENTED
984
        or tb_wadr or tbia_dat_o or tbim_dat_o
985
        or tbar_dat_o or tbts_dat_o
986
`endif
987
        )
988
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
989
`ifdef OR1200_DU_DVR0
990
                `OR1200_DU_DVR0:
991
                        spr_dat_o = dvr0;
992
`endif
993
`ifdef OR1200_DU_DVR1
994
                `OR1200_DU_DVR1:
995
                        spr_dat_o = dvr1;
996
`endif
997
`ifdef OR1200_DU_DVR2
998
                `OR1200_DU_DVR2:
999
                        spr_dat_o = dvr2;
1000
`endif
1001
`ifdef OR1200_DU_DVR3
1002
                `OR1200_DU_DVR3:
1003
                        spr_dat_o = dvr3;
1004
`endif
1005
`ifdef OR1200_DU_DVR4
1006
                `OR1200_DU_DVR4:
1007
                        spr_dat_o = dvr4;
1008
`endif
1009
`ifdef OR1200_DU_DVR5
1010
                `OR1200_DU_DVR5:
1011
                        spr_dat_o = dvr5;
1012
`endif
1013
`ifdef OR1200_DU_DVR6
1014
                `OR1200_DU_DVR6:
1015
                        spr_dat_o = dvr6;
1016
`endif
1017
`ifdef OR1200_DU_DVR7
1018
                `OR1200_DU_DVR7:
1019
                        spr_dat_o = dvr7;
1020
`endif
1021
`ifdef OR1200_DU_DCR0
1022
                `OR1200_DU_DCR0:
1023
                        spr_dat_o = {24'h00_0000, dcr0};
1024
`endif
1025
`ifdef OR1200_DU_DCR1
1026
                `OR1200_DU_DCR1:
1027
                        spr_dat_o = {24'h00_0000, dcr1};
1028
`endif
1029
`ifdef OR1200_DU_DCR2
1030
                `OR1200_DU_DCR2:
1031
                        spr_dat_o = {24'h00_0000, dcr2};
1032
`endif
1033
`ifdef OR1200_DU_DCR3
1034
                `OR1200_DU_DCR3:
1035
                        spr_dat_o = {24'h00_0000, dcr3};
1036
`endif
1037
`ifdef OR1200_DU_DCR4
1038
                `OR1200_DU_DCR4:
1039
                        spr_dat_o = {24'h00_0000, dcr4};
1040
`endif
1041
`ifdef OR1200_DU_DCR5
1042
                `OR1200_DU_DCR5:
1043
                        spr_dat_o = {24'h00_0000, dcr5};
1044
`endif
1045
`ifdef OR1200_DU_DCR6
1046
                `OR1200_DU_DCR6:
1047
                        spr_dat_o = {24'h00_0000, dcr6};
1048
`endif
1049
`ifdef OR1200_DU_DCR7
1050
                `OR1200_DU_DCR7:
1051
                        spr_dat_o = {24'h00_0000, dcr7};
1052
`endif
1053
`ifdef OR1200_DU_DMR1
1054
                `OR1200_DU_DMR1:
1055
                        spr_dat_o = {7'h00, dmr1};
1056
`endif
1057
`ifdef OR1200_DU_DMR2
1058
                `OR1200_DU_DMR2:
1059
                        spr_dat_o = {8'h00, dmr2};
1060
`endif
1061
`ifdef OR1200_DU_DWCR0
1062
                `OR1200_DU_DWCR0:
1063
                        spr_dat_o = dwcr0;
1064
`endif
1065
`ifdef OR1200_DU_DWCR1
1066
                `OR1200_DU_DWCR1:
1067
                        spr_dat_o = dwcr1;
1068
`endif
1069
`ifdef OR1200_DU_DSR
1070
                `OR1200_DU_DSR:
1071
                        spr_dat_o = {18'b0, dsr};
1072
`endif
1073
`ifdef OR1200_DU_DRR
1074
                `OR1200_DU_DRR:
1075
                        spr_dat_o = {18'b0, drr};
1076
`endif
1077
`ifdef OR1200_DU_TB_IMPLEMENTED
1078
                `OR1200_DU_TBADR:
1079
                        spr_dat_o = {24'h000000, tb_wadr};
1080
                `OR1200_DU_TBIA:
1081
                        spr_dat_o = tbia_dat_o;
1082
                `OR1200_DU_TBIM:
1083
                        spr_dat_o = tbim_dat_o;
1084
                `OR1200_DU_TBAR:
1085
                        spr_dat_o = tbar_dat_o;
1086
                `OR1200_DU_TBTS:
1087
                        spr_dat_o = tbts_dat_o;
1088
`endif
1089
                default:
1090
                        spr_dat_o = 32'h0000_0000;
1091
        endcase
1092
`endif
1093
 
1094
//
1095
// DSR alias
1096
//
1097
assign du_dsr = dsr;
1098
 
1099
`ifdef OR1200_DU_HWBKPTS
1100
 
1101
//
1102
// Compare To What (Match Condition 0)
1103
//
1104
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1105
        or dcpu_dat_lsu or dcpu_we_i)
1106
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1107
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1108
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1109
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1110
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1111
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1112
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1113
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1114
        endcase
1115
 
1116
//
1117
// When To Compare (Match Condition 0)
1118
//
1119
always @(dcr0 or dcpu_cycstb_i)
1120
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1121
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1122
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1123
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1124
        endcase
1125
 
1126
//
1127
// Match Condition 0
1128
//
1129
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1130
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1131
                4'b0_xxx,
1132
                4'b1_000,
1133
                4'b1_111: match0 = 1'b0;
1134
                4'b1_001: match0 =
1135 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} ==
1136
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1137 10 unneback
                4'b1_010: match0 =
1138 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <
1139
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1140 10 unneback
                4'b1_011: match0 =
1141 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <=
1142
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1143 10 unneback
                4'b1_100: match0 =
1144 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >
1145
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1146 10 unneback
                4'b1_101: match0 =
1147 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >=
1148
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1149 10 unneback
                4'b1_110: match0 =
1150 141 marcus.erl
                        ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} !=
1151
                         {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]});
1152 10 unneback
        endcase
1153
 
1154
//
1155
// Watchpoint 0
1156
//
1157
always @(dmr1 or match0)
1158
        case (dmr1[`OR1200_DU_DMR1_CW0])
1159
                2'b00: wp[0] = match0;
1160
                2'b01: wp[0] = match0;
1161
                2'b10: wp[0] = match0;
1162
                2'b11: wp[0] = 1'b0;
1163
        endcase
1164
 
1165
//
1166
// Compare To What (Match Condition 1)
1167
//
1168
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1169
        or dcpu_dat_lsu or dcpu_we_i)
1170
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1171
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1172
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1173
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1174
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1175
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1176
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1177
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1178
        endcase
1179
 
1180
//
1181
// When To Compare (Match Condition 1)
1182
//
1183
always @(dcr1 or dcpu_cycstb_i)
1184
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1185
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1186
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1187
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1188
        endcase
1189
 
1190
//
1191
// Match Condition 1
1192
//
1193
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1194
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1195
                4'b0_xxx,
1196
                4'b1_000,
1197
                4'b1_111: match1 = 1'b0;
1198
                4'b1_001: match1 =
1199 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} ==
1200
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1201 10 unneback
                4'b1_010: match1 =
1202 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <
1203
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1204 10 unneback
                4'b1_011: match1 =
1205 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <=
1206
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1207 10 unneback
                4'b1_100: match1 =
1208 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >
1209
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1210 10 unneback
                4'b1_101: match1 =
1211 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >=
1212
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1213 10 unneback
                4'b1_110: match1 =
1214 141 marcus.erl
                        ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} !=
1215
                         {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]});
1216 10 unneback
        endcase
1217
 
1218
//
1219
// Watchpoint 1
1220
//
1221
always @(dmr1 or match1 or wp)
1222
        case (dmr1[`OR1200_DU_DMR1_CW1])
1223
                2'b00: wp[1] = match1;
1224
                2'b01: wp[1] = match1 & wp[0];
1225
                2'b10: wp[1] = match1 | wp[0];
1226
                2'b11: wp[1] = 1'b0;
1227
        endcase
1228
 
1229
//
1230
// Compare To What (Match Condition 2)
1231
//
1232
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1233
        or dcpu_dat_lsu or dcpu_we_i)
1234
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1235
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1236
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1237
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1238
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1239
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1240
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1241
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1242
        endcase
1243
 
1244
//
1245
// When To Compare (Match Condition 2)
1246
//
1247
always @(dcr2 or dcpu_cycstb_i)
1248
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1249
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1250
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1251
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1252
        endcase
1253
 
1254
//
1255
// Match Condition 2
1256
//
1257
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1258
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1259
                4'b0_xxx,
1260
                4'b1_000,
1261
                4'b1_111: match2 = 1'b0;
1262
                4'b1_001: match2 =
1263 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} ==
1264
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1265 10 unneback
                4'b1_010: match2 =
1266 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <
1267
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1268 10 unneback
                4'b1_011: match2 =
1269 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <=
1270
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1271 10 unneback
                4'b1_100: match2 =
1272 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >
1273
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1274 10 unneback
                4'b1_101: match2 =
1275 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >=
1276
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1277 10 unneback
                4'b1_110: match2 =
1278 141 marcus.erl
                        ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} !=
1279
                         {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]});
1280 10 unneback
        endcase
1281
 
1282
//
1283
// Watchpoint 2
1284
//
1285
always @(dmr1 or match2 or wp)
1286
        case (dmr1[`OR1200_DU_DMR1_CW2])
1287
                2'b00: wp[2] = match2;
1288
                2'b01: wp[2] = match2 & wp[1];
1289
                2'b10: wp[2] = match2 | wp[1];
1290
                2'b11: wp[2] = 1'b0;
1291
        endcase
1292
 
1293
//
1294
// Compare To What (Match Condition 3)
1295
//
1296
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1297
        or dcpu_dat_lsu or dcpu_we_i)
1298
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1299
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1300
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1301
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1302
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1303
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1304
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1305
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1306
        endcase
1307
 
1308
//
1309
// When To Compare (Match Condition 3)
1310
//
1311
always @(dcr3 or dcpu_cycstb_i)
1312
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1313
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1314
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1315
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1316
        endcase
1317
 
1318
//
1319
// Match Condition 3
1320
//
1321
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1322
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1323
                4'b0_xxx,
1324
                4'b1_000,
1325
                4'b1_111: match3 = 1'b0;
1326
                4'b1_001: match3 =
1327 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} ==
1328
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1329 10 unneback
                4'b1_010: match3 =
1330 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <
1331
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1332 10 unneback
                4'b1_011: match3 =
1333 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <=
1334
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1335 10 unneback
                4'b1_100: match3 =
1336 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >
1337
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1338 10 unneback
                4'b1_101: match3 =
1339 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >=
1340
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1341 10 unneback
                4'b1_110: match3 =
1342 141 marcus.erl
                        ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} !=
1343
                         {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]});
1344 10 unneback
        endcase
1345
 
1346
//
1347
// Watchpoint 3
1348
//
1349
always @(dmr1 or match3 or wp)
1350
        case (dmr1[`OR1200_DU_DMR1_CW3])
1351
                2'b00: wp[3] = match3;
1352
                2'b01: wp[3] = match3 & wp[2];
1353
                2'b10: wp[3] = match3 | wp[2];
1354
                2'b11: wp[3] = 1'b0;
1355
        endcase
1356
 
1357
//
1358
// Compare To What (Match Condition 4)
1359
//
1360
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1361
        or dcpu_dat_lsu or dcpu_we_i)
1362
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1363
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1364
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1365
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1366
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1367
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1368
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1369
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1370
        endcase
1371
 
1372
//
1373
// When To Compare (Match Condition 4)
1374
//
1375
always @(dcr4 or dcpu_cycstb_i)
1376
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1377
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1378
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1379
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1380
        endcase
1381
 
1382
//
1383
// Match Condition 4
1384
//
1385
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1386
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1387
                4'b0_xxx,
1388
                4'b1_000,
1389
                4'b1_111: match4 = 1'b0;
1390
                4'b1_001: match4 =
1391 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} ==
1392
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1393 10 unneback
                4'b1_010: match4 =
1394 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <
1395
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1396 10 unneback
                4'b1_011: match4 =
1397 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <=
1398
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1399 10 unneback
                4'b1_100: match4 =
1400 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >
1401
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1402 10 unneback
                4'b1_101: match4 =
1403 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >=
1404
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1405 10 unneback
                4'b1_110: match4 =
1406 141 marcus.erl
                        ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} !=
1407
                         {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]});
1408 10 unneback
        endcase
1409
 
1410
//
1411
// Watchpoint 4
1412
//
1413
always @(dmr1 or match4 or wp)
1414
        case (dmr1[`OR1200_DU_DMR1_CW4])
1415
                2'b00: wp[4] = match4;
1416
                2'b01: wp[4] = match4 & wp[3];
1417
                2'b10: wp[4] = match4 | wp[3];
1418
                2'b11: wp[4] = 1'b0;
1419
        endcase
1420
 
1421
//
1422
// Compare To What (Match Condition 5)
1423
//
1424
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1425
        or dcpu_dat_lsu or dcpu_we_i)
1426
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1427
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1428
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1429
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1430
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1431
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1432
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1433
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1434
        endcase
1435
 
1436
//
1437
// When To Compare (Match Condition 5)
1438
//
1439
always @(dcr5 or dcpu_cycstb_i)
1440
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1441
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1442
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1443
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1444
        endcase
1445
 
1446
//
1447
// Match Condition 5
1448
//
1449
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1450
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1451
                4'b0_xxx,
1452
                4'b1_000,
1453
                4'b1_111: match5 = 1'b0;
1454
                4'b1_001: match5 =
1455 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} ==
1456
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1457 10 unneback
                4'b1_010: match5 =
1458 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <
1459
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1460 10 unneback
                4'b1_011: match5 =
1461 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <=
1462
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1463 10 unneback
                4'b1_100: match5 =
1464 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >
1465
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1466 10 unneback
                4'b1_101: match5 =
1467 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >=
1468
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1469 10 unneback
                4'b1_110: match5 =
1470 141 marcus.erl
                        ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} !=
1471
                         {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]});
1472 10 unneback
        endcase
1473
 
1474
//
1475
// Watchpoint 5
1476
//
1477
always @(dmr1 or match5 or wp)
1478
        case (dmr1[`OR1200_DU_DMR1_CW5])
1479
                2'b00: wp[5] = match5;
1480
                2'b01: wp[5] = match5 & wp[4];
1481
                2'b10: wp[5] = match5 | wp[4];
1482
                2'b11: wp[5] = 1'b0;
1483
        endcase
1484
 
1485
//
1486
// Compare To What (Match Condition 6)
1487
//
1488
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1489
        or dcpu_dat_lsu or dcpu_we_i)
1490
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1491
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1492
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1493
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1494
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1495
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1496
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1497
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1498
        endcase
1499
 
1500
//
1501
// When To Compare (Match Condition 6)
1502
//
1503
always @(dcr6 or dcpu_cycstb_i)
1504
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1505
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1506
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1507
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1508
        endcase
1509
 
1510
//
1511
// Match Condition 6
1512
//
1513
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1514
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1515
                4'b0_xxx,
1516
                4'b1_000,
1517
                4'b1_111: match6 = 1'b0;
1518
                4'b1_001: match6 =
1519 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} ==
1520
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1521 10 unneback
                4'b1_010: match6 =
1522 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <
1523
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1524 10 unneback
                4'b1_011: match6 =
1525 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <=
1526
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1527 10 unneback
                4'b1_100: match6 =
1528 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >
1529
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1530 10 unneback
                4'b1_101: match6 =
1531 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >=
1532
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1533 10 unneback
                4'b1_110: match6 =
1534 141 marcus.erl
                        ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} !=
1535
                         {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]});
1536 10 unneback
        endcase
1537
 
1538
//
1539
// Watchpoint 6
1540
//
1541
always @(dmr1 or match6 or wp)
1542
        case (dmr1[`OR1200_DU_DMR1_CW6])
1543
                2'b00: wp[6] = match6;
1544
                2'b01: wp[6] = match6 & wp[5];
1545
                2'b10: wp[6] = match6 | wp[5];
1546
                2'b11: wp[6] = 1'b0;
1547
        endcase
1548
 
1549
//
1550
// Compare To What (Match Condition 7)
1551
//
1552
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1553
        or dcpu_dat_lsu or dcpu_we_i)
1554
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1555
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1556
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1557
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1558
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1559
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1560
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1561
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1562
        endcase
1563
 
1564
//
1565
// When To Compare (Match Condition 7)
1566
//
1567
always @(dcr7 or dcpu_cycstb_i)
1568
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1569
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1570
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1571
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1572
        endcase
1573
 
1574
//
1575
// Match Condition 7
1576
//
1577
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1578
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1579
                4'b0_xxx,
1580
                4'b1_000,
1581
                4'b1_111: match7 = 1'b0;
1582
                4'b1_001: match7 =
1583 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} ==
1584
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1585 10 unneback
                4'b1_010: match7 =
1586 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <
1587
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1588 10 unneback
                4'b1_011: match7 =
1589 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <=
1590
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1591 10 unneback
                4'b1_100: match7 =
1592 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >
1593
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1594 10 unneback
                4'b1_101: match7 =
1595 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >=
1596
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1597 10 unneback
                4'b1_110: match7 =
1598 141 marcus.erl
                        ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} !=
1599
                         {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]});
1600 10 unneback
        endcase
1601
 
1602
//
1603
// Watchpoint 7
1604
//
1605
always @(dmr1 or match7 or wp)
1606
        case (dmr1[`OR1200_DU_DMR1_CW7])
1607
                2'b00: wp[7] = match7;
1608
                2'b01: wp[7] = match7 & wp[6];
1609
                2'b10: wp[7] = match7 | wp[6];
1610
                2'b11: wp[7] = 1'b0;
1611
        endcase
1612
 
1613
//
1614
// Increment Watchpoint Counter 0
1615
//
1616
always @(wp or dmr2)
1617
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1618
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1619
        else
1620
                incr_wpcntr0 = 1'b0;
1621
 
1622
//
1623
// Match Condition Watchpoint Counter 0
1624
//
1625
always @(dwcr0)
1626
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1627
                wpcntr0_match = 1'b1;
1628
        else
1629
                wpcntr0_match = 1'b0;
1630
 
1631
 
1632
//
1633
// Watchpoint 8
1634
//
1635
always @(dmr1 or wpcntr0_match or wp)
1636
        case (dmr1[`OR1200_DU_DMR1_CW8])
1637
                2'b00: wp[8] = wpcntr0_match;
1638
                2'b01: wp[8] = wpcntr0_match & wp[7];
1639
                2'b10: wp[8] = wpcntr0_match | wp[7];
1640
                2'b11: wp[8] = 1'b0;
1641
        endcase
1642
 
1643
 
1644
//
1645
// Increment Watchpoint Counter 1
1646
//
1647
always @(wp or dmr2)
1648
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1649
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1650
        else
1651
                incr_wpcntr1 = 1'b0;
1652
 
1653
//
1654
// Match Condition Watchpoint Counter 1
1655
//
1656
always @(dwcr1)
1657
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1658
                wpcntr1_match = 1'b1;
1659
        else
1660
                wpcntr1_match = 1'b0;
1661
 
1662
//
1663
// Watchpoint 9
1664
//
1665
always @(dmr1 or wpcntr1_match or wp)
1666
        case (dmr1[`OR1200_DU_DMR1_CW9])
1667
                2'b00: wp[9] = wpcntr1_match;
1668
                2'b01: wp[9] = wpcntr1_match & wp[8];
1669
                2'b10: wp[9] = wpcntr1_match | wp[8];
1670
                2'b11: wp[9] = 1'b0;
1671
        endcase
1672
 
1673
//
1674
// Watchpoint 10
1675
//
1676
always @(dmr1 or dbg_ewt_i or wp)
1677
        case (dmr1[`OR1200_DU_DMR1_CW10])
1678
                2'b00: wp[10] = dbg_ewt_i;
1679
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1680
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1681
                2'b11: wp[10] = 1'b0;
1682
        endcase
1683
 
1684
`endif
1685
 
1686
//
1687
// Watchpoints can cause trap exception
1688
//
1689
`ifdef OR1200_DU_HWBKPTS
1690 141 marcus.erl
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]) | du_hwbkpt_hold | (dbg_bp_r & ~dsr[`OR1200_DU_DSR_TE]);
1691 10 unneback
`else
1692
assign du_hwbkpt = 1'b0;
1693
`endif
1694
 
1695 141 marcus.erl
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception 
1696
always @(posedge clk or posedge rst)
1697
        if (rst)
1698
                du_hwbkpt_hold <= #1 1'b0;
1699
        else if (du_hwbkpt & ex_freeze)
1700
                du_hwbkpt_hold <= #1 1'b1;
1701
        else if (!ex_freeze)
1702
                du_hwbkpt_hold <= #1 1'b0;
1703
 
1704 10 unneback
`ifdef OR1200_DU_TB_IMPLEMENTED
1705
//
1706
// Simple trace buffer
1707
// (right now hardcoded for Xilinx Virtex FPGAs)
1708
//
1709
// Stores last 256 instruction addresses, instruction
1710
// machine words and ALU results
1711
//
1712
 
1713
//
1714
// Trace buffer write enable
1715
//
1716
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1717
 
1718
//
1719
// Trace buffer write address pointer
1720
//
1721
always @(posedge clk or posedge rst)
1722
        if (rst)
1723
                tb_wadr <= #1 8'h00;
1724
        else if (tb_enw)
1725
                tb_wadr <= #1 tb_wadr + 8'd1;
1726
 
1727
//
1728
// Free running counter (time stamp)
1729
//
1730
always @(posedge clk or posedge rst)
1731
        if (rst)
1732
                tb_timstmp <= #1 32'h00000000;
1733
        else if (!dbg_bp_r)
1734
                tb_timstmp <= #1 tb_timstmp + 32'd1;
1735
 
1736
//
1737
// Trace buffer RAMs
1738
//
1739
 
1740
or1200_dpram_256x32 tbia_ram(
1741
        .clk_a(clk),
1742 141 marcus.erl
        .rst_a(1'b0),
1743 10 unneback
        .addr_a(spr_addr[7:0]),
1744
        .ce_a(1'b1),
1745
        .oe_a(1'b1),
1746
        .do_a(tbia_dat_o),
1747
 
1748
        .clk_b(clk),
1749 141 marcus.erl
        .rst_b(1'b0),
1750 10 unneback
        .addr_b(tb_wadr),
1751
        .di_b(spr_dat_npc),
1752
        .ce_b(1'b1),
1753
        .we_b(tb_enw)
1754
 
1755
);
1756
 
1757
or1200_dpram_256x32 tbim_ram(
1758
        .clk_a(clk),
1759 141 marcus.erl
        .rst_a(1'b0),
1760 10 unneback
        .addr_a(spr_addr[7:0]),
1761
        .ce_a(1'b1),
1762
        .oe_a(1'b1),
1763
        .do_a(tbim_dat_o),
1764
 
1765
        .clk_b(clk),
1766 141 marcus.erl
        .rst_b(1'b0),
1767 10 unneback
        .addr_b(tb_wadr),
1768
        .di_b(ex_insn),
1769
        .ce_b(1'b1),
1770
        .we_b(tb_enw)
1771
);
1772
 
1773
or1200_dpram_256x32 tbar_ram(
1774
        .clk_a(clk),
1775 141 marcus.erl
        .rst_a(1'b0),
1776 10 unneback
        .addr_a(spr_addr[7:0]),
1777
        .ce_a(1'b1),
1778
        .oe_a(1'b1),
1779
        .do_a(tbar_dat_o),
1780
 
1781
        .clk_b(clk),
1782 141 marcus.erl
        .rst_b(1'b0),
1783 10 unneback
        .addr_b(tb_wadr),
1784
        .di_b(rf_dataw),
1785
        .ce_b(1'b1),
1786
        .we_b(tb_enw)
1787
);
1788
 
1789
or1200_dpram_256x32 tbts_ram(
1790
        .clk_a(clk),
1791 141 marcus.erl
        .rst_a(1'b0),
1792 10 unneback
        .addr_a(spr_addr[7:0]),
1793
        .ce_a(1'b1),
1794
        .oe_a(1'b1),
1795
        .do_a(tbts_dat_o),
1796
 
1797
        .clk_b(clk),
1798 141 marcus.erl
        .rst_b(1'b0),
1799 10 unneback
        .addr_b(tb_wadr),
1800
        .di_b(tb_timstmp),
1801
        .ce_b(1'b1),
1802
        .we_b(tb_enw)
1803
);
1804
 
1805
`else
1806
 
1807
assign tbia_dat_o = 32'h0000_0000;
1808
assign tbim_dat_o = 32'h0000_0000;
1809
assign tbar_dat_o = 32'h0000_0000;
1810
assign tbts_dat_o = 32'h0000_0000;
1811
 
1812
`endif  // OR1200_DU_TB_IMPLEMENTED
1813
 
1814
`else   // OR1200_DU_IMPLEMENTED
1815
 
1816
//
1817
// When DU is not implemented, drive all outputs as would when DU is disabled
1818
//
1819
assign dbg_bp_o = 1'b0;
1820
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1821 141 marcus.erl
assign du_dmr1 = {25{1'b0}};
1822 10 unneback
assign du_hwbkpt = 1'b0;
1823
 
1824
//
1825
// Read DU registers
1826
//
1827
`ifdef OR1200_DU_READREGS
1828
assign spr_dat_o = 32'h0000_0000;
1829
`ifdef OR1200_DU_UNUSED_ZERO
1830
`endif
1831
`endif
1832
 
1833
`endif
1834
 
1835
endmodule

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