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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 32

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1 10 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  OR1200's Debug Unit                                         ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://www.opencores.org/cores/or1k/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Basic OR1200 debug unit.                                    ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////   - make it smaller and faster                               ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Damjan Lampret, lampret@opencores.org                 ////
16 
////                                                              ////
17 
//////////////////////////////////////////////////////////////////////
18 
////                                                              ////
19 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20 
////                                                              ////
21 
//// This source file may be used and distributed without         ////
22 
//// restriction provided that this copyright statement is not    ////
23 
//// removed from the file and that any derivative work contains  ////
24 
//// the original copyright notice and the associated disclaimer. ////
25 
////                                                              ////
26 
//// This source file is free software; you can redistribute it   ////
27 
//// and/or modify it under the terms of the GNU Lesser General   ////
28 
//// Public License as published by the Free Software Foundation; ////
29 
//// either version 2.1 of the License, or (at your option) any   ////
30 
//// later version.                                               ////
31 
////                                                              ////
32 
//// This source is distributed in the hope that it will be       ////
33 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36 
//// details.                                                     ////
37 
////                                                              ////
38 
//// You should have received a copy of the GNU Lesser General    ////
39 
//// Public License along with this source; if not, download it   ////
40 
//// from http://www.opencores.org/lgpl.shtml                     ////
41 
////                                                              ////
42 
//////////////////////////////////////////////////////////////////////
43 
//
44 
// CVS Revision History
45 
//
46 
// $Log: not supported by cvs2svn $
47 
// Revision 1.11  2005/01/07 09:35:08  andreje
48 
// du_hwbkpt disabled when debug unit not implemented
49 
//
50 
// Revision 1.10  2004/04/05 08:29:57  lampret
51 
// Merged branch_qmem into main tree.
52 
//
53 
// Revision 1.9.4.4  2004/02/11 01:40:11  lampret
54 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
55 
//
56 
// Revision 1.9.4.3  2004/01/18 10:08:00  simons
57 
// Error fixed.
58 
//
59 
// Revision 1.9.4.2  2004/01/17 21:14:14  simons
60 
// Errors fixed.
61 
//
62 
// Revision 1.9.4.1  2004/01/15 06:46:38  markom
63 
// interface to debug changed; no more opselect; stb-ack protocol
64 
//
65 
// Revision 1.9  2003/01/22 03:23:47  lampret
66 
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
67 
//
68 
// Revision 1.8  2002/09/08 19:31:52  lampret
69 
// Fixed a typo, reported by Taylor Su.
70 
//
71 
// Revision 1.7  2002/07/14 22:17:17  lampret
72 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
73 
//
74 
// Revision 1.6  2002/03/14 00:30:24  lampret
75 
// Added alternative for critical path in DU.
76 
//
77 
// Revision 1.5  2002/02/11 04:33:17  lampret
78 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
79 
//
80 
// Revision 1.4  2002/01/28 01:16:00  lampret
81 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
82 
//
83 
// Revision 1.3  2002/01/18 07:56:00  lampret
84 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
85 
//
86 
// Revision 1.2  2002/01/14 06:18:22  lampret
87 
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
88 
//
89 
// Revision 1.1  2002/01/03 08:16:15  lampret
90 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
91 
//
92 
// Revision 1.12  2001/11/30 18:58:00  simons
93 
// Trap insn couses break after exits ex_insn.
94 
//
95 
// Revision 1.11  2001/11/23 08:38:51  lampret
96 
// Changed DSR/DRR behavior and exception detection.
97 
//
98 
// Revision 1.10  2001/11/20 21:25:44  lampret
99 
// Fixed dbg_is_o assignment width.
100 
//
101 
// Revision 1.9  2001/11/20 18:46:14  simons
102 
// Break point bug fixed
103 
//
104 
// Revision 1.8  2001/11/18 08:36:28  lampret
105 
// For GDB changed single stepping and disabled trap exception.
106 
//
107 
// Revision 1.7  2001/10/21 18:09:53  lampret
108 
// Fixed sensitivity list.
109 
//
110 
// Revision 1.6  2001/10/14 13:12:09  lampret
111 
// MP3 version.
112 
//
113 
//
114 
 
115 
// synopsys translate_off
116 
`include "timescale.v"
117 
// synopsys translate_on
118 
`include "or1200_defines.v"
119 
 
120 
//
121 
// Debug unit
122 
//
123 
 
124 
module or1200_du(
125 
        // RISC Internal Interface
126 
        clk, rst,
127 
        dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
128 
        dcpu_dat_dc, icpu_cycstb_i,
129 
        ex_freeze, branch_op, ex_insn, id_pc,
130 
        spr_dat_npc, rf_dataw,
131 
        du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
132 
        du_read, du_write, du_except, du_hwbkpt,
133 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
134 
 
135 
        // External Debug Interface
136 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
137 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
138 
);
139 
 
140 
parameter dw = `OR1200_OPERAND_WIDTH;
141 
parameter aw = `OR1200_OPERAND_WIDTH;
142 
 
143 
//
144 
// I/O
145 
//
146 
 
147 
//
148 
// RISC Internal Interface
149 
//
150 
input                           clk;            // Clock
151 
input                           rst;            // Reset
152 
input                           dcpu_cycstb_i;  // LSU status
153 
input                           dcpu_we_i;      // LSU status
154 
input   [31:0]                   dcpu_adr_i;     // LSU addr
155 
input   [31:0]                   dcpu_dat_lsu;   // LSU store data
156 
input   [31:0]                   dcpu_dat_dc;    // LSU load data
157 
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
158 
input                           ex_freeze;      // EX stage freeze
159 
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
160 
input   [dw-1:0]         ex_insn;        // EX insn
161 
input   [31:0]                   id_pc;          // insn fetch EA
162 
input   [31:0]                   spr_dat_npc;    // Next PC (for trace)
163 
input   [31:0]                   rf_dataw;       // ALU result (for trace)
164 
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
165 
output                          du_stall;       // Debug Unit Stall
166 
output  [aw-1:0]         du_addr;        // Debug Unit Address
167 
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
168 
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
169 
output                          du_read;        // Debug Unit Read Enable
170 
output                          du_write;       // Debug Unit Write Enable
171 
input   [12:0]                   du_except;      // Exception masked by DSR
172 
output                          du_hwbkpt;      // Cause trap exception (HW Breakpoints)
173 
input                           spr_cs;         // SPR Chip Select
174 
input                           spr_write;      // SPR Read/Write
175 
input   [aw-1:0]         spr_addr;       // SPR Address
176 
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
177 
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
178 
 
179 
//
180 
// External Debug Interface
181 
//
182 
input                   dbg_stall_i;    // External Stall Input
183 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
184 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
185 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
186 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
187 
output                  dbg_bp_o;       // Breakpoint Output
188 
input                   dbg_stb_i;      // External Address/Data Strobe
189 
input                   dbg_we_i;       // External Write Enable
190 
input   [aw-1:0] dbg_adr_i;      // External Address Input
191 
input   [dw-1:0] dbg_dat_i;      // External Data Input
192 
output  [dw-1:0] dbg_dat_o;      // External Data Output
193 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
194 
 
195 
 
196 
//
197 
// Some connections go directly from the CPU through DU to Debug I/F
198 
//
199 
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
200 
assign dbg_lss_o = 4'b0000;
201 
 
202 
reg     [1:0]                    dbg_is_o;
203 
//
204 
// Show insn activity (temp, must be removed)
205 
//
206 
always @(posedge clk or posedge rst)
207 
        if (rst)
208 
                dbg_is_o <= #1 2'b00;
209 
        else if (!ex_freeze &
210 
                ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
211 
                dbg_is_o <= #1 ~dbg_is_o;
212 
`ifdef UNUSED
213 
assign dbg_is_o = 2'b00;
214 
`endif
215 
`else
216 
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
217 
assign dbg_is_o = {1'b0, icpu_cycstb_i};
218 
`endif
219 
assign dbg_wp_o = 11'b000_0000_0000;
220 
assign dbg_dat_o = du_dat_i;
221 
 
222 
//
223 
// Some connections go directly from Debug I/F through DU to the CPU
224 
//
225 
assign du_stall = dbg_stall_i;
226 
assign du_addr = dbg_adr_i;
227 
assign du_dat_o = dbg_dat_i;
228 
assign du_read = dbg_stb_i && !dbg_we_i;
229 
assign du_write = dbg_stb_i && dbg_we_i;
230 
 
231 
//
232 
// Generate acknowledge -- just delay stb signal
233 
//
234 
reg dbg_ack_o;
235 
always @(posedge clk or posedge rst)
236 
        if (rst)
237 
                dbg_ack_o <= #1 1'b0;
238 
        else
239 
                dbg_ack_o <= #1 dbg_stb_i;
240 
 
241 
`ifdef OR1200_DU_IMPLEMENTED
242 
 
243 
//
244 
// Debug Mode Register 1
245 
//
246 
`ifdef OR1200_DU_DMR1
247 
reg     [24:0]                   dmr1;           // DMR1 implemented
248 
`else
249 
wire    [24:0]                   dmr1;           // DMR1 not implemented
250 
`endif
251 
 
252 
//
253 
// Debug Mode Register 2
254 
//
255 
`ifdef OR1200_DU_DMR2
256 
reg     [23:0]                   dmr2;           // DMR2 implemented
257 
`else
258 
wire    [23:0]                   dmr2;           // DMR2 not implemented
259 
`endif
260 
 
261 
//
262 
// Debug Stop Register
263 
//
264 
`ifdef OR1200_DU_DSR
265 
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
266 
`else
267 
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
268 
`endif
269 
 
270 
//
271 
// Debug Reason Register
272 
//
273 
`ifdef OR1200_DU_DRR
274 
reg     [13:0]                   drr;            // DRR implemented
275 
`else
276 
wire    [13:0]                   drr;            // DRR not implemented
277 
`endif
278 
 
279 
//
280 
// Debug Value Register N
281 
//
282 
`ifdef OR1200_DU_DVR0
283 
reg     [31:0]                   dvr0;
284 
`else
285 
wire    [31:0]                   dvr0;
286 
`endif
287 
 
288 
//
289 
// Debug Value Register N
290 
//
291 
`ifdef OR1200_DU_DVR1
292 
reg     [31:0]                   dvr1;
293 
`else
294 
wire    [31:0]                   dvr1;
295 
`endif
296 
 
297 
//
298 
// Debug Value Register N
299 
//
300 
`ifdef OR1200_DU_DVR2
301 
reg     [31:0]                   dvr2;
302 
`else
303 
wire    [31:0]                   dvr2;
304 
`endif
305 
 
306 
//
307 
// Debug Value Register N
308 
//
309 
`ifdef OR1200_DU_DVR3
310 
reg     [31:0]                   dvr3;
311 
`else
312 
wire    [31:0]                   dvr3;
313 
`endif
314 
 
315 
//
316 
// Debug Value Register N
317 
//
318 
`ifdef OR1200_DU_DVR4
319 
reg     [31:0]                   dvr4;
320 
`else
321 
wire    [31:0]                   dvr4;
322 
`endif
323 
 
324 
//
325 
// Debug Value Register N
326 
//
327 
`ifdef OR1200_DU_DVR5
328 
reg     [31:0]                   dvr5;
329 
`else
330 
wire    [31:0]                   dvr5;
331 
`endif
332 
 
333 
//
334 
// Debug Value Register N
335 
//
336 
`ifdef OR1200_DU_DVR6
337 
reg     [31:0]                   dvr6;
338 
`else
339 
wire    [31:0]                   dvr6;
340 
`endif
341 
 
342 
//
343 
// Debug Value Register N
344 
//
345 
`ifdef OR1200_DU_DVR7
346 
reg     [31:0]                   dvr7;
347 
`else
348 
wire    [31:0]                   dvr7;
349 
`endif
350 
 
351 
//
352 
// Debug Control Register N
353 
//
354 
`ifdef OR1200_DU_DCR0
355 
reg     [7:0]                    dcr0;
356 
`else
357 
wire    [7:0]                    dcr0;
358 
`endif
359 
 
360 
//
361 
// Debug Control Register N
362 
//
363 
`ifdef OR1200_DU_DCR1
364 
reg     [7:0]                    dcr1;
365 
`else
366 
wire    [7:0]                    dcr1;
367 
`endif
368 
 
369 
//
370 
// Debug Control Register N
371 
//
372 
`ifdef OR1200_DU_DCR2
373 
reg     [7:0]                    dcr2;
374 
`else
375 
wire    [7:0]                    dcr2;
376 
`endif
377 
 
378 
//
379 
// Debug Control Register N
380 
//
381 
`ifdef OR1200_DU_DCR3
382 
reg     [7:0]                    dcr3;
383 
`else
384 
wire    [7:0]                    dcr3;
385 
`endif
386 
 
387 
//
388 
// Debug Control Register N
389 
//
390 
`ifdef OR1200_DU_DCR4
391 
reg     [7:0]                    dcr4;
392 
`else
393 
wire    [7:0]                    dcr4;
394 
`endif
395 
 
396 
//
397 
// Debug Control Register N
398 
//
399 
`ifdef OR1200_DU_DCR5
400 
reg     [7:0]                    dcr5;
401 
`else
402 
wire    [7:0]                    dcr5;
403 
`endif
404 
 
405 
//
406 
// Debug Control Register N
407 
//
408 
`ifdef OR1200_DU_DCR6
409 
reg     [7:0]                    dcr6;
410 
`else
411 
wire    [7:0]                    dcr6;
412 
`endif
413 
 
414 
//
415 
// Debug Control Register N
416 
//
417 
`ifdef OR1200_DU_DCR7
418 
reg     [7:0]                    dcr7;
419 
`else
420 
wire    [7:0]                    dcr7;
421 
`endif
422 
 
423 
//
424 
// Debug Watchpoint Counter Register 0
425 
//
426 
`ifdef OR1200_DU_DWCR0
427 
reg     [31:0]                   dwcr0;
428 
`else
429 
wire    [31:0]                   dwcr0;
430 
`endif
431 
 
432 
//
433 
// Debug Watchpoint Counter Register 1
434 
//
435 
`ifdef OR1200_DU_DWCR1
436 
reg     [31:0]                   dwcr1;
437 
`else
438 
wire    [31:0]                   dwcr1;
439 
`endif
440 
 
441 
//
442 
// Internal wires
443 
//
444 
wire                            dmr1_sel;       // DMR1 select
445 
wire                            dmr2_sel;       // DMR2 select
446 
wire                            dsr_sel;        // DSR select
447 
wire                            drr_sel;        // DRR select
448 
wire                            dvr0_sel,
449 
                                dvr1_sel,
450 
                                dvr2_sel,
451 
                                dvr3_sel,
452 
                                dvr4_sel,
453 
                                dvr5_sel,
454 
                                dvr6_sel,
455 
                                dvr7_sel;       // DVR selects
456 
wire                            dcr0_sel,
457 
                                dcr1_sel,
458 
                                dcr2_sel,
459 
                                dcr3_sel,
460 
                                dcr4_sel,
461 
                                dcr5_sel,
462 
                                dcr6_sel,
463 
                                dcr7_sel;       // DCR selects
464 
wire                            dwcr0_sel,
465 
                                dwcr1_sel;      // DWCR selects
466 
reg                             dbg_bp_r;
467 
`ifdef OR1200_DU_HWBKPTS
468 
reg     [31:0]                   match_cond0_ct;
469 
reg     [31:0]                   match_cond1_ct;
470 
reg     [31:0]                   match_cond2_ct;
471 
reg     [31:0]                   match_cond3_ct;
472 
reg     [31:0]                   match_cond4_ct;
473 
reg     [31:0]                   match_cond5_ct;
474 
reg     [31:0]                   match_cond6_ct;
475 
reg     [31:0]                   match_cond7_ct;
476 
reg                             match_cond0_stb;
477 
reg                             match_cond1_stb;
478 
reg                             match_cond2_stb;
479 
reg                             match_cond3_stb;
480 
reg                             match_cond4_stb;
481 
reg                             match_cond5_stb;
482 
reg                             match_cond6_stb;
483 
reg                             match_cond7_stb;
484 
reg                             match0;
485 
reg                             match1;
486 
reg                             match2;
487 
reg                             match3;
488 
reg                             match4;
489 
reg                             match5;
490 
reg                             match6;
491 
reg                             match7;
492 
reg                             wpcntr0_match;
493 
reg                             wpcntr1_match;
494 
reg                             incr_wpcntr0;
495 
reg                             incr_wpcntr1;
496 
reg     [10:0]                   wp;
497 
`endif
498 
wire                            du_hwbkpt;
499 
`ifdef OR1200_DU_READREGS
500 
reg     [31:0]                   spr_dat_o;
501 
`endif
502 
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
503 
`ifdef OR1200_DU_TB_IMPLEMENTED
504 
wire                            tb_enw;
505 
reg     [7:0]                    tb_wadr;
506 
reg [31:0]                       tb_timstmp;
507 
`endif
508 
wire    [31:0]                   tbia_dat_o;
509 
wire    [31:0]                   tbim_dat_o;
510 
wire    [31:0]                   tbar_dat_o;
511 
wire    [31:0]                   tbts_dat_o;
512 
 
513 
//
514 
// DU registers address decoder
515 
//
516 
`ifdef OR1200_DU_DMR1
517 
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
518 
`endif
519 
`ifdef OR1200_DU_DMR2
520 
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
521 
`endif
522 
`ifdef OR1200_DU_DSR
523 
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
524 
`endif
525 
`ifdef OR1200_DU_DRR
526 
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
527 
`endif
528 
`ifdef OR1200_DU_DVR0
529 
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
530 
`endif
531 
`ifdef OR1200_DU_DVR1
532 
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
533 
`endif
534 
`ifdef OR1200_DU_DVR2
535 
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
536 
`endif
537 
`ifdef OR1200_DU_DVR3
538 
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
539 
`endif
540 
`ifdef OR1200_DU_DVR4
541 
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
542 
`endif
543 
`ifdef OR1200_DU_DVR5
544 
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
545 
`endif
546 
`ifdef OR1200_DU_DVR6
547 
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
548 
`endif
549 
`ifdef OR1200_DU_DVR7
550 
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
551 
`endif
552 
`ifdef OR1200_DU_DCR0
553 
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
554 
`endif
555 
`ifdef OR1200_DU_DCR1
556 
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
557 
`endif
558 
`ifdef OR1200_DU_DCR2
559 
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
560 
`endif
561 
`ifdef OR1200_DU_DCR3
562 
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
563 
`endif
564 
`ifdef OR1200_DU_DCR4
565 
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
566 
`endif
567 
`ifdef OR1200_DU_DCR5
568 
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
569 
`endif
570 
`ifdef OR1200_DU_DCR6
571 
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
572 
`endif
573 
`ifdef OR1200_DU_DCR7
574 
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
575 
`endif
576 
`ifdef OR1200_DU_DWCR0
577 
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
578 
`endif
579 
`ifdef OR1200_DU_DWCR1
580 
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
581 
`endif
582 
 
583 
//
584 
// Decode started exception
585 
//
586 
always @(du_except) begin
587 
        except_stop = 14'b0000_0000_0000;
588 
        casex (du_except)
589 
                13'b1_xxxx_xxxx_xxxx:
590 
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
591 
                13'b0_1xxx_xxxx_xxxx: begin
592 
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
593 
                end
594 
                13'b0_01xx_xxxx_xxxx: begin
595 
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
596 
                end
597 
                13'b0_001x_xxxx_xxxx:
598 
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
599 
                13'b0_0001_xxxx_xxxx: begin
600 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
601 
                end
602 
                13'b0_0000_1xxx_xxxx:
603 
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
604 
                13'b0_0000_01xx_xxxx: begin
605 
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
606 
                end
607 
                13'b0_0000_001x_xxxx: begin
608 
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
609 
                end
610 
                13'b0_0000_0001_xxxx:
611 
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
612 
                13'b0_0000_0000_1xxx:
613 
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
614 
                13'b0_0000_0000_01xx: begin
615 
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
616 
                end
617 
                13'b0_0000_0000_001x: begin
618 
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
619 
                end
620 
                13'b0_0000_0000_0001:
621 
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
622 
                default:
623 
                        except_stop = 14'b0000_0000_0000;
624 
        endcase
625 
end
626 
 
627 
//
628 
// dbg_bp_o is registered
629 
//
630 
assign dbg_bp_o = dbg_bp_r;
631 
 
632 
//
633 
// Breakpoint activation register
634 
//
635 
always @(posedge clk or posedge rst)
636 
        if (rst)
637 
                dbg_bp_r <= #1 1'b0;
638 
        else if (!ex_freeze)
639 
                dbg_bp_r <= #1 |except_stop
640 
`ifdef OR1200_DU_DMR1_ST
641 
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
642 
`endif
643 
`ifdef OR1200_DU_DMR1_BT
644 
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
645 
`endif
646 
                        ;
647 
        else
648 
                dbg_bp_r <= #1 |except_stop;
649 
 
650 
//
651 
// Write to DMR1
652 
//
653 
`ifdef OR1200_DU_DMR1
654 
always @(posedge clk or posedge rst)
655 
        if (rst)
656 
                dmr1 <= 25'h000_0000;
657 
        else if (dmr1_sel && spr_write)
658 
`ifdef OR1200_DU_HWBKPTS
659 
                dmr1 <= #1 spr_dat_i[24:0];
660 
`else
661 
                dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
662 
`endif
663 
`else
664 
assign dmr1 = 25'h000_0000;
665 
`endif
666 
 
667 
//
668 
// Write to DMR2
669 
//
670 
`ifdef OR1200_DU_DMR2
671 
always @(posedge clk or posedge rst)
672 
        if (rst)
673 
                dmr2 <= 24'h00_0000;
674 
        else if (dmr2_sel && spr_write)
675 
                dmr2 <= #1 spr_dat_i[23:0];
676 
`else
677 
assign dmr2 = 24'h00_0000;
678 
`endif
679 
 
680 
//
681 
// Write to DSR
682 
//
683 
`ifdef OR1200_DU_DSR
684 
always @(posedge clk or posedge rst)
685 
        if (rst)
686 
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
687 
        else if (dsr_sel && spr_write)
688 
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
689 
`else
690 
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
691 
`endif
692 
 
693 
//
694 
// Write to DRR
695 
//
696 
`ifdef OR1200_DU_DRR
697 
always @(posedge clk or posedge rst)
698 
        if (rst)
699 
                drr <= 14'b0;
700 
        else if (drr_sel && spr_write)
701 
                drr <= #1 spr_dat_i[13:0];
702 
        else
703 
                drr <= #1 drr | except_stop;
704 
`else
705 
assign drr = 14'b0;
706 
`endif
707 
 
708 
//
709 
// Write to DVR0
710 
//
711 
`ifdef OR1200_DU_DVR0
712 
always @(posedge clk or posedge rst)
713 
        if (rst)
714 
                dvr0 <= 32'h0000_0000;
715 
        else if (dvr0_sel && spr_write)
716 
                dvr0 <= #1 spr_dat_i[31:0];
717 
`else
718 
assign dvr0 = 32'h0000_0000;
719 
`endif
720 
 
721 
//
722 
// Write to DVR1
723 
//
724 
`ifdef OR1200_DU_DVR1
725 
always @(posedge clk or posedge rst)
726 
        if (rst)
727 
                dvr1 <= 32'h0000_0000;
728 
        else if (dvr1_sel && spr_write)
729 
                dvr1 <= #1 spr_dat_i[31:0];
730 
`else
731 
assign dvr1 = 32'h0000_0000;
732 
`endif
733 
 
734 
//
735 
// Write to DVR2
736 
//
737 
`ifdef OR1200_DU_DVR2
738 
always @(posedge clk or posedge rst)
739 
        if (rst)
740 
                dvr2 <= 32'h0000_0000;
741 
        else if (dvr2_sel && spr_write)
742 
                dvr2 <= #1 spr_dat_i[31:0];
743 
`else
744 
assign dvr2 = 32'h0000_0000;
745 
`endif
746 
 
747 
//
748 
// Write to DVR3
749 
//
750 
`ifdef OR1200_DU_DVR3
751 
always @(posedge clk or posedge rst)
752 
        if (rst)
753 
                dvr3 <= 32'h0000_0000;
754 
        else if (dvr3_sel && spr_write)
755 
                dvr3 <= #1 spr_dat_i[31:0];
756 
`else
757 
assign dvr3 = 32'h0000_0000;
758 
`endif
759 
 
760 
//
761 
// Write to DVR4
762 
//
763 
`ifdef OR1200_DU_DVR4
764 
always @(posedge clk or posedge rst)
765 
        if (rst)
766 
                dvr4 <= 32'h0000_0000;
767 
        else if (dvr4_sel && spr_write)
768 
                dvr4 <= #1 spr_dat_i[31:0];
769 
`else
770 
assign dvr4 = 32'h0000_0000;
771 
`endif
772 
 
773 
//
774 
// Write to DVR5
775 
//
776 
`ifdef OR1200_DU_DVR5
777 
always @(posedge clk or posedge rst)
778 
        if (rst)
779 
                dvr5 <= 32'h0000_0000;
780 
        else if (dvr5_sel && spr_write)
781 
                dvr5 <= #1 spr_dat_i[31:0];
782 
`else
783 
assign dvr5 = 32'h0000_0000;
784 
`endif
785 
 
786 
//
787 
// Write to DVR6
788 
//
789 
`ifdef OR1200_DU_DVR6
790 
always @(posedge clk or posedge rst)
791 
        if (rst)
792 
                dvr6 <= 32'h0000_0000;
793 
        else if (dvr6_sel && spr_write)
794 
                dvr6 <= #1 spr_dat_i[31:0];
795 
`else
796 
assign dvr6 = 32'h0000_0000;
797 
`endif
798 
 
799 
//
800 
// Write to DVR7
801 
//
802 
`ifdef OR1200_DU_DVR7
803 
always @(posedge clk or posedge rst)
804 
        if (rst)
805 
                dvr7 <= 32'h0000_0000;
806 
        else if (dvr7_sel && spr_write)
807 
                dvr7 <= #1 spr_dat_i[31:0];
808 
`else
809 
assign dvr7 = 32'h0000_0000;
810 
`endif
811 
 
812 
//
813 
// Write to DCR0
814 
//
815 
`ifdef OR1200_DU_DCR0
816 
always @(posedge clk or posedge rst)
817 
        if (rst)
818 
                dcr0 <= 8'h00;
819 
        else if (dcr0_sel && spr_write)
820 
                dcr0 <= #1 spr_dat_i[7:0];
821 
`else
822 
assign dcr0 = 8'h00;
823 
`endif
824 
 
825 
//
826 
// Write to DCR1
827 
//
828 
`ifdef OR1200_DU_DCR1
829 
always @(posedge clk or posedge rst)
830 
        if (rst)
831 
                dcr1 <= 8'h00;
832 
        else if (dcr1_sel && spr_write)
833 
                dcr1 <= #1 spr_dat_i[7:0];
834 
`else
835 
assign dcr1 = 8'h00;
836 
`endif
837 
 
838 
//
839 
// Write to DCR2
840 
//
841 
`ifdef OR1200_DU_DCR2
842 
always @(posedge clk or posedge rst)
843 
        if (rst)
844 
                dcr2 <= 8'h00;
845 
        else if (dcr2_sel && spr_write)
846 
                dcr2 <= #1 spr_dat_i[7:0];
847 
`else
848 
assign dcr2 = 8'h00;
849 
`endif
850 
 
851 
//
852 
// Write to DCR3
853 
//
854 
`ifdef OR1200_DU_DCR3
855 
always @(posedge clk or posedge rst)
856 
        if (rst)
857 
                dcr3 <= 8'h00;
858 
        else if (dcr3_sel && spr_write)
859 
                dcr3 <= #1 spr_dat_i[7:0];
860 
`else
861 
assign dcr3 = 8'h00;
862 
`endif
863 
 
864 
//
865 
// Write to DCR4
866 
//
867 
`ifdef OR1200_DU_DCR4
868 
always @(posedge clk or posedge rst)
869 
        if (rst)
870 
                dcr4 <= 8'h00;
871 
        else if (dcr4_sel && spr_write)
872 
                dcr4 <= #1 spr_dat_i[7:0];
873 
`else
874 
assign dcr4 = 8'h00;
875 
`endif
876 
 
877 
//
878 
// Write to DCR5
879 
//
880 
`ifdef OR1200_DU_DCR5
881 
always @(posedge clk or posedge rst)
882 
        if (rst)
883 
                dcr5 <= 8'h00;
884 
        else if (dcr5_sel && spr_write)
885 
                dcr5 <= #1 spr_dat_i[7:0];
886 
`else
887 
assign dcr5 = 8'h00;
888 
`endif
889 
 
890 
//
891 
// Write to DCR6
892 
//
893 
`ifdef OR1200_DU_DCR6
894 
always @(posedge clk or posedge rst)
895 
        if (rst)
896 
                dcr6 <= 8'h00;
897 
        else if (dcr6_sel && spr_write)
898 
                dcr6 <= #1 spr_dat_i[7:0];
899 
`else
900 
assign dcr6 = 8'h00;
901 
`endif
902 
 
903 
//
904 
// Write to DCR7
905 
//
906 
`ifdef OR1200_DU_DCR7
907 
always @(posedge clk or posedge rst)
908 
        if (rst)
909 
                dcr7 <= 8'h00;
910 
        else if (dcr7_sel && spr_write)
911 
                dcr7 <= #1 spr_dat_i[7:0];
912 
`else
913 
assign dcr7 = 8'h00;
914 
`endif
915 
 
916 
//
917 
// Write to DWCR0
918 
//
919 
`ifdef OR1200_DU_DWCR0
920 
always @(posedge clk or posedge rst)
921 
        if (rst)
922 
                dwcr0 <= 32'h0000_0000;
923 
        else if (dwcr0_sel && spr_write)
924 
                dwcr0 <= #1 spr_dat_i[31:0];
925 
        else if (incr_wpcntr0)
926 
                dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
927 
`else
928 
assign dwcr0 = 32'h0000_0000;
929 
`endif
930 
 
931 
//
932 
// Write to DWCR1
933 
//
934 
`ifdef OR1200_DU_DWCR1
935 
always @(posedge clk or posedge rst)
936 
        if (rst)
937 
                dwcr1 <= 32'h0000_0000;
938 
        else if (dwcr1_sel && spr_write)
939 
                dwcr1 <= #1 spr_dat_i[31:0];
940 
        else if (incr_wpcntr1)
941 
                dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
942 
`else
943 
assign dwcr1 = 32'h0000_0000;
944 
`endif
945 
 
946 
//
947 
// Read DU registers
948 
//
949 
`ifdef OR1200_DU_READREGS
950 
always @(spr_addr or dsr or drr or dmr1 or dmr2
951 
        or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
952 
        or dvr5 or dvr6 or dvr7
953 
        or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
954 
        or dcr5 or dcr6 or dcr7
955 
        or dwcr0 or dwcr1
956 
`ifdef OR1200_DU_TB_IMPLEMENTED
957 
        or tb_wadr or tbia_dat_o or tbim_dat_o
958 
        or tbar_dat_o or tbts_dat_o
959 
`endif
960 
        )
961 
        casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
962 
`ifdef OR1200_DU_DVR0
963 
                `OR1200_DU_DVR0:
964 
                        spr_dat_o = dvr0;
965 
`endif
966 
`ifdef OR1200_DU_DVR1
967 
                `OR1200_DU_DVR1:
968 
                        spr_dat_o = dvr1;
969 
`endif
970 
`ifdef OR1200_DU_DVR2
971 
                `OR1200_DU_DVR2:
972 
                        spr_dat_o = dvr2;
973 
`endif
974 
`ifdef OR1200_DU_DVR3
975 
                `OR1200_DU_DVR3:
976 
                        spr_dat_o = dvr3;
977 
`endif
978 
`ifdef OR1200_DU_DVR4
979 
                `OR1200_DU_DVR4:
980 
                        spr_dat_o = dvr4;
981 
`endif
982 
`ifdef OR1200_DU_DVR5
983 
                `OR1200_DU_DVR5:
984 
                        spr_dat_o = dvr5;
985 
`endif
986 
`ifdef OR1200_DU_DVR6
987 
                `OR1200_DU_DVR6:
988 
                        spr_dat_o = dvr6;
989 
`endif
990 
`ifdef OR1200_DU_DVR7
991 
                `OR1200_DU_DVR7:
992 
                        spr_dat_o = dvr7;
993 
`endif
994 
`ifdef OR1200_DU_DCR0
995 
                `OR1200_DU_DCR0:
996 
                        spr_dat_o = {24'h00_0000, dcr0};
997 
`endif
998 
`ifdef OR1200_DU_DCR1
999 
                `OR1200_DU_DCR1:
1000 
                        spr_dat_o = {24'h00_0000, dcr1};
1001 
`endif
1002 
`ifdef OR1200_DU_DCR2
1003 
                `OR1200_DU_DCR2:
1004 
                        spr_dat_o = {24'h00_0000, dcr2};
1005 
`endif
1006 
`ifdef OR1200_DU_DCR3
1007 
                `OR1200_DU_DCR3:
1008 
                        spr_dat_o = {24'h00_0000, dcr3};
1009 
`endif
1010 
`ifdef OR1200_DU_DCR4
1011 
                `OR1200_DU_DCR4:
1012 
                        spr_dat_o = {24'h00_0000, dcr4};
1013 
`endif
1014 
`ifdef OR1200_DU_DCR5
1015 
                `OR1200_DU_DCR5:
1016 
                        spr_dat_o = {24'h00_0000, dcr5};
1017 
`endif
1018 
`ifdef OR1200_DU_DCR6
1019 
                `OR1200_DU_DCR6:
1020 
                        spr_dat_o = {24'h00_0000, dcr6};
1021 
`endif
1022 
`ifdef OR1200_DU_DCR7
1023 
                `OR1200_DU_DCR7:
1024 
                        spr_dat_o = {24'h00_0000, dcr7};
1025 
`endif
1026 
`ifdef OR1200_DU_DMR1
1027 
                `OR1200_DU_DMR1:
1028 
                        spr_dat_o = {7'h00, dmr1};
1029 
`endif
1030 
`ifdef OR1200_DU_DMR2
1031 
                `OR1200_DU_DMR2:
1032 
                        spr_dat_o = {8'h00, dmr2};
1033 
`endif
1034 
`ifdef OR1200_DU_DWCR0
1035 
                `OR1200_DU_DWCR0:
1036 
                        spr_dat_o = dwcr0;
1037 
`endif
1038 
`ifdef OR1200_DU_DWCR1
1039 
                `OR1200_DU_DWCR1:
1040 
                        spr_dat_o = dwcr1;
1041 
`endif
1042 
`ifdef OR1200_DU_DSR
1043 
                `OR1200_DU_DSR:
1044 
                        spr_dat_o = {18'b0, dsr};
1045 
`endif
1046 
`ifdef OR1200_DU_DRR
1047 
                `OR1200_DU_DRR:
1048 
                        spr_dat_o = {18'b0, drr};
1049 
`endif
1050 
`ifdef OR1200_DU_TB_IMPLEMENTED
1051 
                `OR1200_DU_TBADR:
1052 
                        spr_dat_o = {24'h000000, tb_wadr};
1053 
                `OR1200_DU_TBIA:
1054 
                        spr_dat_o = tbia_dat_o;
1055 
                `OR1200_DU_TBIM:
1056 
                        spr_dat_o = tbim_dat_o;
1057 
                `OR1200_DU_TBAR:
1058 
                        spr_dat_o = tbar_dat_o;
1059 
                `OR1200_DU_TBTS:
1060 
                        spr_dat_o = tbts_dat_o;
1061 
`endif
1062 
                default:
1063 
                        spr_dat_o = 32'h0000_0000;
1064 
        endcase
1065 
`endif
1066 
 
1067 
//
1068 
// DSR alias
1069 
//
1070 
assign du_dsr = dsr;
1071 
 
1072 
`ifdef OR1200_DU_HWBKPTS
1073 
 
1074 
//
1075 
// Compare To What (Match Condition 0)
1076 
//
1077 
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
1078 
        or dcpu_dat_lsu or dcpu_we_i)
1079 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1080 
                3'b001: match_cond0_ct = id_pc;         // insn fetch EA
1081 
                3'b010: match_cond0_ct = dcpu_adr_i;    // load EA
1082 
                3'b011: match_cond0_ct = dcpu_adr_i;    // store EA
1083 
                3'b100: match_cond0_ct = dcpu_dat_dc;   // load data
1084 
                3'b101: match_cond0_ct = dcpu_dat_lsu;  // store data
1085 
                3'b110: match_cond0_ct = dcpu_adr_i;    // load/store EA
1086 
                default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1087 
        endcase
1088 
 
1089 
//
1090 
// When To Compare (Match Condition 0)
1091 
//
1092 
always @(dcr0 or dcpu_cycstb_i)
1093 
        case (dcr0[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1094 
                3'b000: match_cond0_stb = 1'b0;         //comparison disabled
1095 
                3'b001: match_cond0_stb = 1'b1;         // insn fetch EA
1096 
                default:match_cond0_stb = dcpu_cycstb_i; // any load/store
1097 
        endcase
1098 
 
1099 
//
1100 
// Match Condition 0
1101 
//
1102 
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
1103 
        casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
1104 
                4'b0_xxx,
1105 
                4'b1_000,
1106 
                4'b1_111: match0 = 1'b0;
1107 
                4'b1_001: match0 =
1108 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
1109 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1110 
                4'b1_010: match0 =
1111 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
1112 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1113 
                4'b1_011: match0 =
1114 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
1115 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1116 
                4'b1_100: match0 =
1117 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
1118 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1119 
                4'b1_101: match0 =
1120 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
1121 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1122 
                4'b1_110: match0 =
1123 
                        ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
1124 
                        (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
1125 
        endcase
1126 
 
1127 
//
1128 
// Watchpoint 0
1129 
//
1130 
always @(dmr1 or match0)
1131 
        case (dmr1[`OR1200_DU_DMR1_CW0])
1132 
                2'b00: wp[0] = match0;
1133 
                2'b01: wp[0] = match0;
1134 
                2'b10: wp[0] = match0;
1135 
                2'b11: wp[0] = 1'b0;
1136 
        endcase
1137 
 
1138 
//
1139 
// Compare To What (Match Condition 1)
1140 
//
1141 
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
1142 
        or dcpu_dat_lsu or dcpu_we_i)
1143 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1144 
                3'b001: match_cond1_ct = id_pc;         // insn fetch EA
1145 
                3'b010: match_cond1_ct = dcpu_adr_i;    // load EA
1146 
                3'b011: match_cond1_ct = dcpu_adr_i;    // store EA
1147 
                3'b100: match_cond1_ct = dcpu_dat_dc;   // load data
1148 
                3'b101: match_cond1_ct = dcpu_dat_lsu;  // store data
1149 
                3'b110: match_cond1_ct = dcpu_adr_i;    // load/store EA
1150 
                default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1151 
        endcase
1152 
 
1153 
//
1154 
// When To Compare (Match Condition 1)
1155 
//
1156 
always @(dcr1 or dcpu_cycstb_i)
1157 
        case (dcr1[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1158 
                3'b000: match_cond1_stb = 1'b0;         //comparison disabled
1159 
                3'b001: match_cond1_stb = 1'b1;         // insn fetch EA
1160 
                default:match_cond1_stb = dcpu_cycstb_i; // any load/store
1161 
        endcase
1162 
 
1163 
//
1164 
// Match Condition 1
1165 
//
1166 
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
1167 
        casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
1168 
                4'b0_xxx,
1169 
                4'b1_000,
1170 
                4'b1_111: match1 = 1'b0;
1171 
                4'b1_001: match1 =
1172 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
1173 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1174 
                4'b1_010: match1 =
1175 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
1176 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1177 
                4'b1_011: match1 =
1178 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
1179 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1180 
                4'b1_100: match1 =
1181 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
1182 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1183 
                4'b1_101: match1 =
1184 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
1185 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1186 
                4'b1_110: match1 =
1187 
                        ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
1188 
                        (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
1189 
        endcase
1190 
 
1191 
//
1192 
// Watchpoint 1
1193 
//
1194 
always @(dmr1 or match1 or wp)
1195 
        case (dmr1[`OR1200_DU_DMR1_CW1])
1196 
                2'b00: wp[1] = match1;
1197 
                2'b01: wp[1] = match1 & wp[0];
1198 
                2'b10: wp[1] = match1 | wp[0];
1199 
                2'b11: wp[1] = 1'b0;
1200 
        endcase
1201 
 
1202 
//
1203 
// Compare To What (Match Condition 2)
1204 
//
1205 
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
1206 
        or dcpu_dat_lsu or dcpu_we_i)
1207 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1208 
                3'b001: match_cond2_ct = id_pc;         // insn fetch EA
1209 
                3'b010: match_cond2_ct = dcpu_adr_i;    // load EA
1210 
                3'b011: match_cond2_ct = dcpu_adr_i;    // store EA
1211 
                3'b100: match_cond2_ct = dcpu_dat_dc;   // load data
1212 
                3'b101: match_cond2_ct = dcpu_dat_lsu;  // store data
1213 
                3'b110: match_cond2_ct = dcpu_adr_i;    // load/store EA
1214 
                default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1215 
        endcase
1216 
 
1217 
//
1218 
// When To Compare (Match Condition 2)
1219 
//
1220 
always @(dcr2 or dcpu_cycstb_i)
1221 
        case (dcr2[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1222 
                3'b000: match_cond2_stb = 1'b0;         //comparison disabled
1223 
                3'b001: match_cond2_stb = 1'b1;         // insn fetch EA
1224 
                default:match_cond2_stb = dcpu_cycstb_i; // any load/store
1225 
        endcase
1226 
 
1227 
//
1228 
// Match Condition 2
1229 
//
1230 
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
1231 
        casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
1232 
                4'b0_xxx,
1233 
                4'b1_000,
1234 
                4'b1_111: match2 = 1'b0;
1235 
                4'b1_001: match2 =
1236 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
1237 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1238 
                4'b1_010: match2 =
1239 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
1240 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1241 
                4'b1_011: match2 =
1242 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
1243 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1244 
                4'b1_100: match2 =
1245 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
1246 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1247 
                4'b1_101: match2 =
1248 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
1249 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1250 
                4'b1_110: match2 =
1251 
                        ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
1252 
                        (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
1253 
        endcase
1254 
 
1255 
//
1256 
// Watchpoint 2
1257 
//
1258 
always @(dmr1 or match2 or wp)
1259 
        case (dmr1[`OR1200_DU_DMR1_CW2])
1260 
                2'b00: wp[2] = match2;
1261 
                2'b01: wp[2] = match2 & wp[1];
1262 
                2'b10: wp[2] = match2 | wp[1];
1263 
                2'b11: wp[2] = 1'b0;
1264 
        endcase
1265 
 
1266 
//
1267 
// Compare To What (Match Condition 3)
1268 
//
1269 
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
1270 
        or dcpu_dat_lsu or dcpu_we_i)
1271 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1272 
                3'b001: match_cond3_ct = id_pc;         // insn fetch EA
1273 
                3'b010: match_cond3_ct = dcpu_adr_i;    // load EA
1274 
                3'b011: match_cond3_ct = dcpu_adr_i;    // store EA
1275 
                3'b100: match_cond3_ct = dcpu_dat_dc;   // load data
1276 
                3'b101: match_cond3_ct = dcpu_dat_lsu;  // store data
1277 
                3'b110: match_cond3_ct = dcpu_adr_i;    // load/store EA
1278 
                default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1279 
        endcase
1280 
 
1281 
//
1282 
// When To Compare (Match Condition 3)
1283 
//
1284 
always @(dcr3 or dcpu_cycstb_i)
1285 
        case (dcr3[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1286 
                3'b000: match_cond3_stb = 1'b0;         //comparison disabled
1287 
                3'b001: match_cond3_stb = 1'b1;         // insn fetch EA
1288 
                default:match_cond3_stb = dcpu_cycstb_i; // any load/store
1289 
        endcase
1290 
 
1291 
//
1292 
// Match Condition 3
1293 
//
1294 
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
1295 
        casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
1296 
                4'b0_xxx,
1297 
                4'b1_000,
1298 
                4'b1_111: match3 = 1'b0;
1299 
                4'b1_001: match3 =
1300 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
1301 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1302 
                4'b1_010: match3 =
1303 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
1304 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1305 
                4'b1_011: match3 =
1306 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
1307 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1308 
                4'b1_100: match3 =
1309 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
1310 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1311 
                4'b1_101: match3 =
1312 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
1313 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1314 
                4'b1_110: match3 =
1315 
                        ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
1316 
                        (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
1317 
        endcase
1318 
 
1319 
//
1320 
// Watchpoint 3
1321 
//
1322 
always @(dmr1 or match3 or wp)
1323 
        case (dmr1[`OR1200_DU_DMR1_CW3])
1324 
                2'b00: wp[3] = match3;
1325 
                2'b01: wp[3] = match3 & wp[2];
1326 
                2'b10: wp[3] = match3 | wp[2];
1327 
                2'b11: wp[3] = 1'b0;
1328 
        endcase
1329 
 
1330 
//
1331 
// Compare To What (Match Condition 4)
1332 
//
1333 
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
1334 
        or dcpu_dat_lsu or dcpu_we_i)
1335 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1336 
                3'b001: match_cond4_ct = id_pc;         // insn fetch EA
1337 
                3'b010: match_cond4_ct = dcpu_adr_i;    // load EA
1338 
                3'b011: match_cond4_ct = dcpu_adr_i;    // store EA
1339 
                3'b100: match_cond4_ct = dcpu_dat_dc;   // load data
1340 
                3'b101: match_cond4_ct = dcpu_dat_lsu;  // store data
1341 
                3'b110: match_cond4_ct = dcpu_adr_i;    // load/store EA
1342 
                default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1343 
        endcase
1344 
 
1345 
//
1346 
// When To Compare (Match Condition 4)
1347 
//
1348 
always @(dcr4 or dcpu_cycstb_i)
1349 
        case (dcr4[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1350 
                3'b000: match_cond4_stb = 1'b0;         //comparison disabled
1351 
                3'b001: match_cond4_stb = 1'b1;         // insn fetch EA
1352 
                default:match_cond4_stb = dcpu_cycstb_i; // any load/store
1353 
        endcase
1354 
 
1355 
//
1356 
// Match Condition 4
1357 
//
1358 
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
1359 
        casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
1360 
                4'b0_xxx,
1361 
                4'b1_000,
1362 
                4'b1_111: match4 = 1'b0;
1363 
                4'b1_001: match4 =
1364 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
1365 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1366 
                4'b1_010: match4 =
1367 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
1368 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1369 
                4'b1_011: match4 =
1370 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
1371 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1372 
                4'b1_100: match4 =
1373 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
1374 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1375 
                4'b1_101: match4 =
1376 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
1377 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1378 
                4'b1_110: match4 =
1379 
                        ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
1380 
                        (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
1381 
        endcase
1382 
 
1383 
//
1384 
// Watchpoint 4
1385 
//
1386 
always @(dmr1 or match4 or wp)
1387 
        case (dmr1[`OR1200_DU_DMR1_CW4])
1388 
                2'b00: wp[4] = match4;
1389 
                2'b01: wp[4] = match4 & wp[3];
1390 
                2'b10: wp[4] = match4 | wp[3];
1391 
                2'b11: wp[4] = 1'b0;
1392 
        endcase
1393 
 
1394 
//
1395 
// Compare To What (Match Condition 5)
1396 
//
1397 
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
1398 
        or dcpu_dat_lsu or dcpu_we_i)
1399 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1400 
                3'b001: match_cond5_ct = id_pc;         // insn fetch EA
1401 
                3'b010: match_cond5_ct = dcpu_adr_i;    // load EA
1402 
                3'b011: match_cond5_ct = dcpu_adr_i;    // store EA
1403 
                3'b100: match_cond5_ct = dcpu_dat_dc;   // load data
1404 
                3'b101: match_cond5_ct = dcpu_dat_lsu;  // store data
1405 
                3'b110: match_cond5_ct = dcpu_adr_i;    // load/store EA
1406 
                default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1407 
        endcase
1408 
 
1409 
//
1410 
// When To Compare (Match Condition 5)
1411 
//
1412 
always @(dcr5 or dcpu_cycstb_i)
1413 
        case (dcr5[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1414 
                3'b000: match_cond5_stb = 1'b0;         //comparison disabled
1415 
                3'b001: match_cond5_stb = 1'b1;         // insn fetch EA
1416 
                default:match_cond5_stb = dcpu_cycstb_i; // any load/store
1417 
        endcase
1418 
 
1419 
//
1420 
// Match Condition 5
1421 
//
1422 
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
1423 
        casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
1424 
                4'b0_xxx,
1425 
                4'b1_000,
1426 
                4'b1_111: match5 = 1'b0;
1427 
                4'b1_001: match5 =
1428 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
1429 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1430 
                4'b1_010: match5 =
1431 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
1432 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1433 
                4'b1_011: match5 =
1434 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
1435 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1436 
                4'b1_100: match5 =
1437 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
1438 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1439 
                4'b1_101: match5 =
1440 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
1441 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1442 
                4'b1_110: match5 =
1443 
                        ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
1444 
                        (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
1445 
        endcase
1446 
 
1447 
//
1448 
// Watchpoint 5
1449 
//
1450 
always @(dmr1 or match5 or wp)
1451 
        case (dmr1[`OR1200_DU_DMR1_CW5])
1452 
                2'b00: wp[5] = match5;
1453 
                2'b01: wp[5] = match5 & wp[4];
1454 
                2'b10: wp[5] = match5 | wp[4];
1455 
                2'b11: wp[5] = 1'b0;
1456 
        endcase
1457 
 
1458 
//
1459 
// Compare To What (Match Condition 6)
1460 
//
1461 
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
1462 
        or dcpu_dat_lsu or dcpu_we_i)
1463 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1464 
                3'b001: match_cond6_ct = id_pc;         // insn fetch EA
1465 
                3'b010: match_cond6_ct = dcpu_adr_i;    // load EA
1466 
                3'b011: match_cond6_ct = dcpu_adr_i;    // store EA
1467 
                3'b100: match_cond6_ct = dcpu_dat_dc;   // load data
1468 
                3'b101: match_cond6_ct = dcpu_dat_lsu;  // store data
1469 
                3'b110: match_cond6_ct = dcpu_adr_i;    // load/store EA
1470 
                default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1471 
        endcase
1472 
 
1473 
//
1474 
// When To Compare (Match Condition 6)
1475 
//
1476 
always @(dcr6 or dcpu_cycstb_i)
1477 
        case (dcr6[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1478 
                3'b000: match_cond6_stb = 1'b0;         //comparison disabled
1479 
                3'b001: match_cond6_stb = 1'b1;         // insn fetch EA
1480 
                default:match_cond6_stb = dcpu_cycstb_i; // any load/store
1481 
        endcase
1482 
 
1483 
//
1484 
// Match Condition 6
1485 
//
1486 
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
1487 
        casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
1488 
                4'b0_xxx,
1489 
                4'b1_000,
1490 
                4'b1_111: match6 = 1'b0;
1491 
                4'b1_001: match6 =
1492 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
1493 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1494 
                4'b1_010: match6 =
1495 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
1496 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1497 
                4'b1_011: match6 =
1498 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
1499 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1500 
                4'b1_100: match6 =
1501 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
1502 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1503 
                4'b1_101: match6 =
1504 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
1505 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1506 
                4'b1_110: match6 =
1507 
                        ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
1508 
                        (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
1509 
        endcase
1510 
 
1511 
//
1512 
// Watchpoint 6
1513 
//
1514 
always @(dmr1 or match6 or wp)
1515 
        case (dmr1[`OR1200_DU_DMR1_CW6])
1516 
                2'b00: wp[6] = match6;
1517 
                2'b01: wp[6] = match6 & wp[5];
1518 
                2'b10: wp[6] = match6 | wp[5];
1519 
                2'b11: wp[6] = 1'b0;
1520 
        endcase
1521 
 
1522 
//
1523 
// Compare To What (Match Condition 7)
1524 
//
1525 
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
1526 
        or dcpu_dat_lsu or dcpu_we_i)
1527 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1528 
                3'b001: match_cond7_ct = id_pc;         // insn fetch EA
1529 
                3'b010: match_cond7_ct = dcpu_adr_i;    // load EA
1530 
                3'b011: match_cond7_ct = dcpu_adr_i;    // store EA
1531 
                3'b100: match_cond7_ct = dcpu_dat_dc;   // load data
1532 
                3'b101: match_cond7_ct = dcpu_dat_lsu;  // store data
1533 
                3'b110: match_cond7_ct = dcpu_adr_i;    // load/store EA
1534 
                default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
1535 
        endcase
1536 
 
1537 
//
1538 
// When To Compare (Match Condition 7)
1539 
//
1540 
always @(dcr7 or dcpu_cycstb_i)
1541 
        case (dcr7[`OR1200_DU_DCR_CT])          // synopsys parallel_case
1542 
                3'b000: match_cond7_stb = 1'b0;         //comparison disabled
1543 
                3'b001: match_cond7_stb = 1'b1;         // insn fetch EA
1544 
                default:match_cond7_stb = dcpu_cycstb_i; // any load/store
1545 
        endcase
1546 
 
1547 
//
1548 
// Match Condition 7
1549 
//
1550 
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
1551 
        casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
1552 
                4'b0_xxx,
1553 
                4'b1_000,
1554 
                4'b1_111: match7 = 1'b0;
1555 
                4'b1_001: match7 =
1556 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
1557 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1558 
                4'b1_010: match7 =
1559 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
1560 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1561 
                4'b1_011: match7 =
1562 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
1563 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1564 
                4'b1_100: match7 =
1565 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
1566 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1567 
                4'b1_101: match7 =
1568 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
1569 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1570 
                4'b1_110: match7 =
1571 
                        ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
1572 
                        (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
1573 
        endcase
1574 
 
1575 
//
1576 
// Watchpoint 7
1577 
//
1578 
always @(dmr1 or match7 or wp)
1579 
        case (dmr1[`OR1200_DU_DMR1_CW7])
1580 
                2'b00: wp[7] = match7;
1581 
                2'b01: wp[7] = match7 & wp[6];
1582 
                2'b10: wp[7] = match7 | wp[6];
1583 
                2'b11: wp[7] = 1'b0;
1584 
        endcase
1585 
 
1586 
//
1587 
// Increment Watchpoint Counter 0
1588 
//
1589 
always @(wp or dmr2)
1590 
        if (dmr2[`OR1200_DU_DMR2_WCE0])
1591 
                incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
1592 
        else
1593 
                incr_wpcntr0 = 1'b0;
1594 
 
1595 
//
1596 
// Match Condition Watchpoint Counter 0
1597 
//
1598 
always @(dwcr0)
1599 
        if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
1600 
                wpcntr0_match = 1'b1;
1601 
        else
1602 
                wpcntr0_match = 1'b0;
1603 
 
1604 
 
1605 
//
1606 
// Watchpoint 8
1607 
//
1608 
always @(dmr1 or wpcntr0_match or wp)
1609 
        case (dmr1[`OR1200_DU_DMR1_CW8])
1610 
                2'b00: wp[8] = wpcntr0_match;
1611 
                2'b01: wp[8] = wpcntr0_match & wp[7];
1612 
                2'b10: wp[8] = wpcntr0_match | wp[7];
1613 
                2'b11: wp[8] = 1'b0;
1614 
        endcase
1615 
 
1616 
 
1617 
//
1618 
// Increment Watchpoint Counter 1
1619 
//
1620 
always @(wp or dmr2)
1621 
        if (dmr2[`OR1200_DU_DMR2_WCE1])
1622 
                incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
1623 
        else
1624 
                incr_wpcntr1 = 1'b0;
1625 
 
1626 
//
1627 
// Match Condition Watchpoint Counter 1
1628 
//
1629 
always @(dwcr1)
1630 
        if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
1631 
                wpcntr1_match = 1'b1;
1632 
        else
1633 
                wpcntr1_match = 1'b0;
1634 
 
1635 
//
1636 
// Watchpoint 9
1637 
//
1638 
always @(dmr1 or wpcntr1_match or wp)
1639 
        case (dmr1[`OR1200_DU_DMR1_CW9])
1640 
                2'b00: wp[9] = wpcntr1_match;
1641 
                2'b01: wp[9] = wpcntr1_match & wp[8];
1642 
                2'b10: wp[9] = wpcntr1_match | wp[8];
1643 
                2'b11: wp[9] = 1'b0;
1644 
        endcase
1645 
 
1646 
//
1647 
// Watchpoint 10
1648 
//
1649 
always @(dmr1 or dbg_ewt_i or wp)
1650 
        case (dmr1[`OR1200_DU_DMR1_CW10])
1651 
                2'b00: wp[10] = dbg_ewt_i;
1652 
                2'b01: wp[10] = dbg_ewt_i & wp[9];
1653 
                2'b10: wp[10] = dbg_ewt_i | wp[9];
1654 
                2'b11: wp[10] = 1'b0;
1655 
        endcase
1656 
 
1657 
`endif
1658 
 
1659 
//
1660 
// Watchpoints can cause trap exception
1661 
//
1662 
`ifdef OR1200_DU_HWBKPTS
1663 
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
1664 
`else
1665 
assign du_hwbkpt = 1'b0;
1666 
`endif
1667 
 
1668 
`ifdef OR1200_DU_TB_IMPLEMENTED
1669 
//
1670 
// Simple trace buffer
1671 
// (right now hardcoded for Xilinx Virtex FPGAs)
1672 
//
1673 
// Stores last 256 instruction addresses, instruction
1674 
// machine words and ALU results
1675 
//
1676 
 
1677 
//
1678 
// Trace buffer write enable
1679 
//
1680 
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
1681 
 
1682 
//
1683 
// Trace buffer write address pointer
1684 
//
1685 
always @(posedge clk or posedge rst)
1686 
        if (rst)
1687 
                tb_wadr <= #1 8'h00;
1688 
        else if (tb_enw)
1689 
                tb_wadr <= #1 tb_wadr + 8'd1;
1690 
 
1691 
//
1692 
// Free running counter (time stamp)
1693 
//
1694 
always @(posedge clk or posedge rst)
1695 
        if (rst)
1696 
                tb_timstmp <= #1 32'h00000000;
1697 
        else if (!dbg_bp_r)
1698 
                tb_timstmp <= #1 tb_timstmp + 32'd1;
1699 
 
1700 
//
1701 
// Trace buffer RAMs
1702 
//
1703 
 
1704 
or1200_dpram_256x32 tbia_ram(
1705 
        .clk_a(clk),
1706 
        .rst_a(rst),
1707 
        .addr_a(spr_addr[7:0]),
1708 
        .ce_a(1'b1),
1709 
        .oe_a(1'b1),
1710 
        .do_a(tbia_dat_o),
1711 
 
1712 
        .clk_b(clk),
1713 
        .rst_b(rst),
1714 
        .addr_b(tb_wadr),
1715 
        .di_b(spr_dat_npc),
1716 
        .ce_b(1'b1),
1717 
        .we_b(tb_enw)
1718 
 
1719 
);
1720 
 
1721 
or1200_dpram_256x32 tbim_ram(
1722 
        .clk_a(clk),
1723 
        .rst_a(rst),
1724 
        .addr_a(spr_addr[7:0]),
1725 
        .ce_a(1'b1),
1726 
        .oe_a(1'b1),
1727 
        .do_a(tbim_dat_o),
1728 
 
1729 
        .clk_b(clk),
1730 
        .rst_b(rst),
1731 
        .addr_b(tb_wadr),
1732 
        .di_b(ex_insn),
1733 
        .ce_b(1'b1),
1734 
        .we_b(tb_enw)
1735 
);
1736 
 
1737 
or1200_dpram_256x32 tbar_ram(
1738 
        .clk_a(clk),
1739 
        .rst_a(rst),
1740 
        .addr_a(spr_addr[7:0]),
1741 
        .ce_a(1'b1),
1742 
        .oe_a(1'b1),
1743 
        .do_a(tbar_dat_o),
1744 
 
1745 
        .clk_b(clk),
1746 
        .rst_b(rst),
1747 
        .addr_b(tb_wadr),
1748 
        .di_b(rf_dataw),
1749 
        .ce_b(1'b1),
1750 
        .we_b(tb_enw)
1751 
);
1752 
 
1753 
or1200_dpram_256x32 tbts_ram(
1754 
        .clk_a(clk),
1755 
        .rst_a(rst),
1756 
        .addr_a(spr_addr[7:0]),
1757 
        .ce_a(1'b1),
1758 
        .oe_a(1'b1),
1759 
        .do_a(tbts_dat_o),
1760 
 
1761 
        .clk_b(clk),
1762 
        .rst_b(rst),
1763 
        .addr_b(tb_wadr),
1764 
        .di_b(tb_timstmp),
1765 
        .ce_b(1'b1),
1766 
        .we_b(tb_enw)
1767 
);
1768 
 
1769 
`else
1770 
 
1771 
assign tbia_dat_o = 32'h0000_0000;
1772 
assign tbim_dat_o = 32'h0000_0000;
1773 
assign tbar_dat_o = 32'h0000_0000;
1774 
assign tbts_dat_o = 32'h0000_0000;
1775 
 
1776 
`endif  // OR1200_DU_TB_IMPLEMENTED
1777 
 
1778 
`else   // OR1200_DU_IMPLEMENTED
1779 
 
1780 
//
1781 
// When DU is not implemented, drive all outputs as would when DU is disabled
1782 
//
1783 
assign dbg_bp_o = 1'b0;
1784 
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
1785 
assign du_hwbkpt = 1'b0;
1786 
 
1787 
//
1788 
// Read DU registers
1789 
//
1790 
`ifdef OR1200_DU_READREGS
1791 
assign spr_dat_o = 32'h0000_0000;
1792 
`ifdef OR1200_DU_UNUSED_ZERO
1793 
`endif
1794 
`endif
1795 
 
1796 
`endif
1797 
 
1798 
endmodule

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