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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Exception logic                                    ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Handles all OR1K exceptions inside CPU block.               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_except.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered and bugs fixed. 
50
//
51
// Revision 1.17  2004/06/08 18:17:36  lampret
52
// Non-functional changes. Coding style fixes.
53
//
54 10 unneback
// Revision 1.16  2004/04/05 08:29:57  lampret
55
// Merged branch_qmem into main tree.
56
//
57
// Revision 1.15.4.1  2004/02/11 01:40:11  lampret
58
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
59
//
60
// Revision 1.15  2003/04/20 22:23:57  lampret
61
// No functional change. Only added customization for exception vectors.
62
//
63
// Revision 1.14  2002/09/03 22:28:21  lampret
64
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
65
//
66
// Revision 1.13  2002/08/28 01:44:25  lampret
67
// Removed some commented RTL. Fixed SR/ESR flag bug.
68
//
69
// Revision 1.12  2002/08/22 02:16:45  lampret
70
// Fixed IMMU bug.
71
//
72
// Revision 1.11  2002/08/18 19:54:28  lampret
73
// Added store buffer.
74
//
75
// Revision 1.10  2002/07/14 22:17:17  lampret
76
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
77
//
78
// Revision 1.9  2002/02/11 04:33:17  lampret
79
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
80
//
81
// Revision 1.8  2002/01/28 01:16:00  lampret
82
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
83
//
84
// Revision 1.7  2002/01/23 07:52:36  lampret
85
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
86
//
87
// Revision 1.6  2002/01/18 14:21:43  lampret
88
// Fixed 'the NPC single-step fix'.
89
//
90
// Revision 1.5  2002/01/18 07:56:00  lampret
91
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
92
//
93
// Revision 1.4  2002/01/14 21:11:50  lampret
94
// Changed alignment exception EPCR. Not tested yet.
95
//
96
// Revision 1.3  2002/01/14 19:09:57  lampret
97
// Fixed order of syscall and range exceptions.
98
//
99
// Revision 1.2  2002/01/14 06:18:22  lampret
100
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
101
//
102
// Revision 1.1  2002/01/03 08:16:15  lampret
103
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
104
//
105
// Revision 1.15  2001/11/27 23:13:11  lampret
106
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
107
//
108
// Revision 1.14  2001/11/23 08:38:51  lampret
109
// Changed DSR/DRR behavior and exception detection.
110
//
111
// Revision 1.13  2001/11/20 18:46:15  simons
112
// Break point bug fixed
113
//
114
// Revision 1.12  2001/11/18 09:58:28  lampret
115
// Fixed some l.trap typos.
116
//
117
// Revision 1.11  2001/11/18 08:36:28  lampret
118
// For GDB changed single stepping and disabled trap exception.
119
//
120
// Revision 1.10  2001/11/13 10:02:21  lampret
121
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
122
//
123
// Revision 1.9  2001/11/10 03:43:57  lampret
124
// Fixed exceptions.
125
//
126
// Revision 1.8  2001/10/21 17:57:16  lampret
127
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
128
//
129
// Revision 1.7  2001/10/14 13:12:09  lampret
130
// MP3 version.
131
//
132
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
133
// no message
134
//
135
// Revision 1.2  2001/08/09 13:39:33  lampret
136
// Major clean-up.
137
//
138
// Revision 1.1  2001/07/20 00:46:03  lampret
139
// Development version of RTL. Libraries are missing.
140
//
141
//
142
 
143
// synopsys translate_off
144
`include "timescale.v"
145
// synopsys translate_on
146
`include "or1200_defines.v"
147
 
148
`define OR1200_EXCEPTFSM_WIDTH 3
149
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
150
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
151
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
152
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
153
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
154
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
155
 
156
//
157
// Exception recognition and sequencing
158
//
159
 
160
module or1200_except(
161
        // Clock and reset
162
        clk, rst,
163
 
164
        // Internal i/f
165
        sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
166
        sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
167 141 marcus.erl
        ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
168
        if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, extend_flush, except_flushpipe, except_type, except_start,
169
        except_started, except_stop, except_trig, ex_void, abort_mvspr, branch_op,
170 10 unneback
        spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
171 141 marcus.erl
        du_dmr1, du_hwbkpt, du_hwbkpt_ls_r,
172 10 unneback
        esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
173 141 marcus.erl
 
174
 
175 10 unneback
);
176
 
177
//
178
// I/O
179
//
180
input                           clk;
181
input                           rst;
182
input                           sig_ibuserr;
183
input                           sig_dbuserr;
184
input                           sig_illegal;
185
input                           sig_align;
186
input                           sig_range;
187
input                           sig_dtlbmiss;
188
input                           sig_dmmufault;
189
input                           sig_int;
190
input                           sig_syscall;
191
input                           sig_trap;
192
input                           sig_itlbmiss;
193
input                           sig_immufault;
194
input                           sig_tick;
195 141 marcus.erl
input                           ex_branch_taken;
196 10 unneback
input                           genpc_freeze;
197
input                           id_freeze;
198
input                           ex_freeze;
199
input                           wb_freeze;
200
input                           if_stall;
201 141 marcus.erl
input   [31:0]           if_pc;
202
output  [31:0]           id_pc;
203
output  [31:0]      ex_pc;
204
output  [31:0]      wb_pc;
205
input   [31:0]           datain;
206 10 unneback
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
207 141 marcus.erl
input   [24:0]                       du_dmr1;
208
input                   du_hwbkpt;
209
input                   du_hwbkpt_ls_r;
210 10 unneback
input                           epcr_we;
211
input                           eear_we;
212
input                           esr_we;
213
input                           pc_we;
214
output  [31:0]                   epcr;
215
output  [31:0]                   eear;
216
output  [`OR1200_SR_WIDTH-1:0]   esr;
217
input   [`OR1200_SR_WIDTH-1:0]   to_sr;
218
input                           sr_we;
219
input   [`OR1200_SR_WIDTH-1:0]   sr;
220
input   [31:0]                   lsu_addr;
221 141 marcus.erl
input                   id_flushpipe;
222
input                   ex_flushpipe;
223
output                          except_flushpipe;
224 10 unneback
output                          extend_flush;
225
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
226
output                          except_start;
227
output                          except_started;
228 141 marcus.erl
output  [12:0]           except_stop;
229
output  [12:0]           except_trig;
230 10 unneback
input                           ex_void;
231 141 marcus.erl
input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
232 10 unneback
output  [31:0]                   spr_dat_ppc;
233
output  [31:0]                   spr_dat_npc;
234
output                          abort_ex;
235 141 marcus.erl
output              abort_mvspr;
236 10 unneback
input                           icpu_ack_i;
237
input                           icpu_err_i;
238
input                           dcpu_ack_i;
239
input                           dcpu_err_i;
240
 
241
//
242
// Internal regs and wires
243
//
244
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
245
reg     [31:0]                   id_pc;
246 141 marcus.erl
reg                 id_pc_val;
247 10 unneback
reg     [31:0]                   ex_pc;
248 141 marcus.erl
reg                 ex_pc_val;
249 10 unneback
reg     [31:0]                   wb_pc;
250 141 marcus.erl
reg [31:0]          dl_pc;
251 10 unneback
reg     [31:0]                   epcr;
252
reg     [31:0]                   eear;
253
reg     [`OR1200_SR_WIDTH-1:0]           esr;
254
reg     [2:0]                    id_exceptflags;
255
reg     [2:0]                    ex_exceptflags;
256
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
257
reg                             extend_flush;
258
reg                             extend_flush_last;
259
reg                             ex_dslot;
260
reg                             delayed1_ex_dslot;
261
reg                             delayed2_ex_dslot;
262
wire                            except_started;
263
reg     [2:0]                    delayed_iee;
264
reg     [2:0]                    delayed_tee;
265
wire                            int_pending;
266
wire                            tick_pending;
267 141 marcus.erl
reg trace_trap      ;
268
reg ex_freeze_prev;
269
reg sr_ted_prev;
270
reg dsr_te_prev;
271
reg dmr1_st_prev    ;
272
reg dmr1_bt_prev    ;
273
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
274
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
275
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
276
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
277 10 unneback
 
278
//
279
// Simple combinatorial logic
280
//
281
assign except_started = extend_flush & except_start;
282 141 marcus.erl
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
283
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE])) & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
284
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val  & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
285
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te);            // Abort write into RF by load & other instructions
286
assign abort_mvspr  = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te) ; // abort spr read/writes
287 10 unneback
assign spr_dat_ppc = wb_pc;
288
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
289
 
290
//
291
// Order defines exception detection priority
292
//
293
assign except_trig = {
294
                        tick_pending            & ~du_dsr[`OR1200_DU_DSR_TTE],
295
                        int_pending             & ~du_dsr[`OR1200_DU_DSR_IE],
296
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IME],
297
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_IPFE],
298
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
299
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
300
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
301
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
302
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
303
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
304
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
305 141 marcus.erl
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE],
306 10 unneback
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
307
                };
308 141 marcus.erl
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
309
`ifdef OR1200_DU_DMR1_ST
310
    ||  dmr1_st
311
`endif
312
`ifdef OR1200_DU_DMR1_BT
313
    ||  ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
314
`endif
315
    );
316
 
317 10 unneback
assign except_stop = {
318
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
319
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
320
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
321
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
322
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
323
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
324
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
325
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
326
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
327
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
328
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
329 141 marcus.erl
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],
330 10 unneback
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
331
                };
332
 
333 141 marcus.erl
always @(posedge clk or posedge rst) begin
334
        if (rst) begin
335
                trace_trap  <= #1 1'b0 ;
336
        end
337
        else if (!(trace_trap && !ex_pc_val)) begin
338
                trace_trap  <= #1 trace_cond & !dsr_te & !sr_ted ;
339
        end
340
end
341
 
342
always @(posedge clk or posedge rst) begin
343
        if (rst) begin
344
        ex_freeze_prev  <= #1 1'b0 ;
345
        sr_ted_prev     <= #1 1'b0 ;
346
        dsr_te_prev     <= #1 1'b0 ;
347
        dmr1_st_prev    <= #1 1'b0 ;
348
        dmr1_bt_prev    <= #1 1'b0 ;
349
    end
350
    else begin
351
        ex_freeze_prev  <= #1 ex_freeze ;
352
        if (!ex_freeze_prev || ex_void) begin
353
            sr_ted_prev     <= #1 sr     [`OR1200_SR_TED    ] ;
354
            dsr_te_prev     <= #1 du_dsr [`OR1200_DU_DSR_TE ] ;
355
            dmr1_st_prev    <= #1 du_dmr1[`OR1200_DU_DMR1_ST] ;
356
            dmr1_bt_prev    <= #1 du_dmr1[`OR1200_DU_DMR1_BT] ;
357
        end
358
    end
359
end
360
 
361 10 unneback
//
362
// PC and Exception flags pipelines
363
//
364
always @(posedge clk or posedge rst) begin
365
        if (rst) begin
366
                id_pc <= #1 32'd0;
367 141 marcus.erl
        id_pc_val <= #1 1'b0 ;
368 10 unneback
                id_exceptflags <= #1 3'b000;
369
        end
370 141 marcus.erl
        else if (id_flushpipe) begin
371
        id_pc_val <= #1 1'b0 ;
372 10 unneback
                id_exceptflags <= #1 3'b000;
373
        end
374
        else if (!id_freeze) begin
375
                id_pc <= #1 if_pc;
376 141 marcus.erl
        id_pc_val <= #1 1'b1 ;
377 10 unneback
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
378
        end
379
end
380
 
381
//
382
// delayed_iee
383
//
384
// SR[IEE] should not enable interrupts right away
385
// when it is restored with l.rfe. Instead delayed_iee
386
// together with SR[IEE] enables interrupts once
387
// pipeline is again ready.
388
//
389
always @(posedge rst or posedge clk)
390
        if (rst)
391
                delayed_iee <= #1 3'b000;
392
        else if (!sr[`OR1200_SR_IEE])
393
                delayed_iee <= #1 3'b000;
394
        else
395
                delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
396
 
397
//
398
// delayed_tee
399
//
400
// SR[TEE] should not enable tick exceptions right away
401
// when it is restored with l.rfe. Instead delayed_tee
402
// together with SR[TEE] enables tick exceptions once
403
// pipeline is again ready.
404
//
405
always @(posedge rst or posedge clk)
406
        if (rst)
407
                delayed_tee <= #1 3'b000;
408
        else if (!sr[`OR1200_SR_TEE])
409
                delayed_tee <= #1 3'b000;
410
        else
411
                delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
412
 
413
//
414
// PC and Exception flags pipelines
415
//
416
always @(posedge clk or posedge rst) begin
417
        if (rst) begin
418
                ex_dslot <= #1 1'b0;
419
                ex_pc <= #1 32'd0;
420 141 marcus.erl
        ex_pc_val <= #1 1'b0 ;
421 10 unneback
                ex_exceptflags <= #1 3'b000;
422
                delayed1_ex_dslot <= #1 1'b0;
423
                delayed2_ex_dslot <= #1 1'b0;
424
        end
425 141 marcus.erl
        else if (ex_flushpipe) begin
426 10 unneback
                ex_dslot <= #1 1'b0;
427 141 marcus.erl
        ex_pc_val <= #1 1'b0 ;
428 10 unneback
                ex_exceptflags <= #1 3'b000;
429
                delayed1_ex_dslot <= #1 1'b0;
430
                delayed2_ex_dslot <= #1 1'b0;
431
        end
432
        else if (!ex_freeze & id_freeze) begin
433
                ex_dslot <= #1 1'b0;
434
                ex_pc <= #1 id_pc;
435 141 marcus.erl
        ex_pc_val <= #1 id_pc_val ;
436 10 unneback
                ex_exceptflags <= #1 3'b000;
437
                delayed1_ex_dslot <= #1 ex_dslot;
438
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
439
        end
440
        else if (!ex_freeze) begin
441 141 marcus.erl
                ex_dslot <= #1 ex_branch_taken;
442 10 unneback
                ex_pc <= #1 id_pc;
443 141 marcus.erl
        ex_pc_val <= #1 id_pc_val ;
444 10 unneback
                ex_exceptflags <= #1 id_exceptflags;
445
                delayed1_ex_dslot <= #1 ex_dslot;
446
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
447
        end
448
end
449
 
450
//
451
// PC and Exception flags pipelines
452
//
453
always @(posedge clk or posedge rst) begin
454
        if (rst) begin
455
                wb_pc <= #1 32'd0;
456 141 marcus.erl
        dl_pc <= #1 32'd0;
457 10 unneback
        end
458
        else if (!wb_freeze) begin
459
                wb_pc <= #1 ex_pc;
460 141 marcus.erl
        dl_pc <= #1 wb_pc;
461 10 unneback
        end
462
end
463
 
464
//
465
// We have started execution of exception handler:
466
//  1. Asserted for 3 clock cycles
467
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
468
//
469
assign except_flushpipe = |except_trig & ~|state;
470
 
471
//
472
// Exception FSM that sequences execution of exception handler
473
//
474
// except_type signals which exception handler we start fetching in:
475
//  1. Asserted in next clock cycle after exception is recognized
476
//
477
always @(posedge clk or posedge rst) begin
478
        if (rst) begin
479
                state <= #1 `OR1200_EXCEPTFSM_IDLE;
480
                except_type <= #1 `OR1200_EXCEPT_NONE;
481
                extend_flush <= #1 1'b0;
482
                epcr <= #1 32'b0;
483
                eear <= #1 32'b0;
484 141 marcus.erl
                esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
485 10 unneback
                extend_flush_last <= #1 1'b0;
486
        end
487
        else begin
488
`ifdef OR1200_CASE_DEFAULT
489
                case (state)    // synopsys parallel_case
490
`else
491
                case (state)    // synopsys full_case parallel_case
492
`endif
493
                        `OR1200_EXCEPTFSM_IDLE:
494
                                if (except_flushpipe) begin
495
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
496
                                        extend_flush <= #1 1'b1;
497
                                        esr <= #1 sr_we ? to_sr : sr;
498
                                        casex (except_trig)
499
`ifdef OR1200_EXCEPT_TICK
500
                                                13'b1_xxxx_xxxx_xxxx: begin
501
                                                        except_type <= #1 `OR1200_EXCEPT_TICK;
502 141 marcus.erl
                                                        epcr <= #1 id_pc;
503
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
504 10 unneback
                                                end
505
`endif
506
`ifdef OR1200_EXCEPT_INT
507
                                                13'b0_1xxx_xxxx_xxxx: begin
508
                                                        except_type <= #1 `OR1200_EXCEPT_INT;
509 141 marcus.erl
                                                        epcr <= #1 id_pc;
510
                                                        //epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
511 10 unneback
                                                end
512
`endif
513
`ifdef OR1200_EXCEPT_ITLBMISS
514
                                                13'b0_01xx_xxxx_xxxx: begin
515
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
516
                                                        eear <= #1 ex_dslot ? ex_pc : ex_pc;
517
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
518
                                                end
519
`endif
520
`ifdef OR1200_EXCEPT_IPF
521
                                                13'b0_001x_xxxx_xxxx: begin
522
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
523
                                                        eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
524
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
525
                                                end
526
`endif
527
`ifdef OR1200_EXCEPT_BUSERR
528
                                                13'b0_0001_xxxx_xxxx: begin
529
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
530
                                                        eear <= #1 ex_dslot ? wb_pc : ex_pc;
531
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
532
                                                end
533
`endif
534
`ifdef OR1200_EXCEPT_ILLEGAL
535
                                                13'b0_0000_1xxx_xxxx: begin
536
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
537
                                                        eear <= #1 ex_pc;
538
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
539
                                                end
540
`endif
541
`ifdef OR1200_EXCEPT_ALIGN
542
                                                13'b0_0000_01xx_xxxx: begin
543
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
544
                                                        eear <= #1 lsu_addr;
545
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
546
                                                end
547
`endif
548
`ifdef OR1200_EXCEPT_DTLBMISS
549
                                                13'b0_0000_001x_xxxx: begin
550
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
551
                                                        eear <= #1 lsu_addr;
552 141 marcus.erl
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
553 10 unneback
                                                end
554
`endif
555
`ifdef OR1200_EXCEPT_DPF
556
                                                13'b0_0000_0001_xxxx: begin
557
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
558
                                                        eear <= #1 lsu_addr;
559 141 marcus.erl
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
560 10 unneback
                                                end
561
`endif
562
`ifdef OR1200_EXCEPT_BUSERR
563
                                                13'b0_0000_0000_1xxx: begin     // Data Bus Error
564
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
565
                                                        eear <= #1 lsu_addr;
566 141 marcus.erl
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
567 10 unneback
                                                end
568
`endif
569
`ifdef OR1200_EXCEPT_RANGE
570
                                                13'b0_0000_0000_01xx: begin
571
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
572
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
573
                                                end
574
`endif
575
`ifdef OR1200_EXCEPT_TRAP                       13'b0_0000_0000_001x: begin
576
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
577 141 marcus.erl
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
578 10 unneback
                                                end
579
`endif
580
`ifdef OR1200_EXCEPT_SYSCALL
581
                                                13'b0_0000_0000_0001: begin
582
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
583
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
584
                                                end
585
`endif
586
                                                default:
587
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
588
                                        endcase
589
                                end
590
                                else if (pc_we) begin
591
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
592
                                        extend_flush <= #1 1'b1;
593
                                end
594
                                else begin
595
                                        if (epcr_we)
596
                                                epcr <= #1 datain;
597
                                        if (eear_we)
598
                                                eear <= #1 datain;
599
                                        if (esr_we)
600 141 marcus.erl
                                                esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
601 10 unneback
                                end
602
                        `OR1200_EXCEPTFSM_FLU1:
603
                                if (icpu_ack_i | icpu_err_i | genpc_freeze)
604
                                        state <= #1 `OR1200_EXCEPTFSM_FLU2;
605
                        `OR1200_EXCEPTFSM_FLU2:
606
`ifdef OR1200_EXCEPT_TRAP
607
                                if (except_type == `OR1200_EXCEPT_TRAP) begin
608
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
609
                                        extend_flush <= #1 1'b0;
610
                                        extend_flush_last <= #1 1'b0;
611
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
612
                                end
613
                                else
614
`endif
615
                                        state <= #1 `OR1200_EXCEPTFSM_FLU3;
616
                        `OR1200_EXCEPTFSM_FLU3:
617
                                        begin
618
                                                state <= #1 `OR1200_EXCEPTFSM_FLU4;
619
                                        end
620
                        `OR1200_EXCEPTFSM_FLU4: begin
621
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
622
                                        extend_flush <= #1 1'b0;
623
                                        extend_flush_last <= #1 1'b0; // damjan
624
                                end
625
`ifdef OR1200_CASE_DEFAULT
626
                        default: begin
627
`else
628
                        `OR1200_EXCEPTFSM_FLU5: begin
629
`endif
630
                                if (!if_stall && !id_freeze) begin
631
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
632
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
633
                                        extend_flush_last <= #1 1'b0;
634
                                end
635
                        end
636
                endcase
637
        end
638
end
639
 
640
endmodule

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