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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Blame information for rev 357

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Exception logic                                    ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Handles all OR1K exceptions inside CPU block.               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 151 marcus.erl
// $Log: or1200_except.v,v $
45 10 unneback
//
46 141 marcus.erl
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
`define OR1200_EXCEPTFSM_WIDTH 3
56
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
57
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
58
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
59
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
60
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
61
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
62
 
63
//
64
// Exception recognition and sequencing
65
//
66
 
67 185 julius
module or1200_except
68
  (
69
   // Clock and reset
70
   clk, rst,
71
 
72
   // Internal i/f
73
   sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
74
   sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
75
   sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
76
   if_stall,  if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
77
   extend_flush, except_flushpipe, except_type, except_start, except_started,
78
   except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
79
   spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
80
   du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
81
   abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
82
 
83 10 unneback
);
84
 
85
//
86
// I/O
87
//
88
input                           clk;
89
input                           rst;
90
input                           sig_ibuserr;
91
input                           sig_dbuserr;
92
input                           sig_illegal;
93
input                           sig_align;
94
input                           sig_range;
95
input                           sig_dtlbmiss;
96
input                           sig_dmmufault;
97
input                           sig_int;
98
input                           sig_syscall;
99
input                           sig_trap;
100
input                           sig_itlbmiss;
101
input                           sig_immufault;
102
input                           sig_tick;
103 185 julius
input                           sig_fp;
104
input                           fpcsr_fpee;
105 141 marcus.erl
input                           ex_branch_taken;
106 10 unneback
input                           genpc_freeze;
107
input                           id_freeze;
108
input                           ex_freeze;
109
input                           wb_freeze;
110
input                           if_stall;
111 141 marcus.erl
input   [31:0]           if_pc;
112
output  [31:0]           id_pc;
113
output  [31:0]      ex_pc;
114
output  [31:0]      wb_pc;
115
input   [31:0]           datain;
116 10 unneback
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
117 141 marcus.erl
input   [24:0]                       du_dmr1;
118
input                   du_hwbkpt;
119
input                   du_hwbkpt_ls_r;
120 10 unneback
input                           epcr_we;
121
input                           eear_we;
122
input                           esr_we;
123
input                           pc_we;
124
output  [31:0]                   epcr;
125
output  [31:0]                   eear;
126
output  [`OR1200_SR_WIDTH-1:0]   esr;
127
input   [`OR1200_SR_WIDTH-1:0]   to_sr;
128
input                           sr_we;
129
input   [`OR1200_SR_WIDTH-1:0]   sr;
130
input   [31:0]                   lsu_addr;
131 141 marcus.erl
input                   id_flushpipe;
132
input                   ex_flushpipe;
133
output                          except_flushpipe;
134 10 unneback
output                          extend_flush;
135
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
136
output                          except_start;
137
output                          except_started;
138 185 julius
output  [13:0]           except_stop;
139
output  [13:0]           except_trig;
140 10 unneback
input                           ex_void;
141 141 marcus.erl
input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
142 10 unneback
output  [31:0]                   spr_dat_ppc;
143
output  [31:0]                   spr_dat_npc;
144
output                          abort_ex;
145 141 marcus.erl
output              abort_mvspr;
146 10 unneback
input                           icpu_ack_i;
147
input                           icpu_err_i;
148
input                           dcpu_ack_i;
149
input                           dcpu_err_i;
150
 
151
//
152
// Internal regs and wires
153
//
154 353 julius
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type /* verilator public */;
155
reg     [31:0]                   id_pc /* verilator public */;
156 141 marcus.erl
reg                 id_pc_val;
157 353 julius
reg     [31:0]                   ex_pc /* verilator public */;
158 141 marcus.erl
reg                 ex_pc_val;
159 353 julius
reg     [31:0]                   wb_pc /* verilator public */;
160 141 marcus.erl
reg [31:0]          dl_pc;
161 10 unneback
reg     [31:0]                   epcr;
162
reg     [31:0]                   eear;
163
reg     [`OR1200_SR_WIDTH-1:0]           esr;
164
reg     [2:0]                    id_exceptflags;
165
reg     [2:0]                    ex_exceptflags;
166
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
167
reg                             extend_flush;
168
reg                             extend_flush_last;
169 353 julius
reg                             ex_dslot /* verilator public */;
170 10 unneback
reg                             delayed1_ex_dslot;
171
reg                             delayed2_ex_dslot;
172
wire                            except_started;
173 353 julius
wire                            except_flushpipe /* verilator public */;
174 10 unneback
reg     [2:0]                    delayed_iee;
175
reg     [2:0]                    delayed_tee;
176
wire                            int_pending;
177
wire                            tick_pending;
178 185 julius
wire                            fp_pending;
179
 
180 141 marcus.erl
reg trace_trap      ;
181
reg ex_freeze_prev;
182
reg sr_ted_prev;
183
reg dsr_te_prev;
184
reg dmr1_st_prev    ;
185
reg dmr1_bt_prev    ;
186
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
187
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
188
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
189
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
190 10 unneback
 
191
//
192
// Simple combinatorial logic
193
//
194
assign except_started = extend_flush & except_start;
195 185 julius
 
196 141 marcus.erl
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
197 185 julius
 
198
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
199
                                (sr_we & to_sr[`OR1200_SR_IEE]))
200
                    & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
201
                     & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
202
 
203
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
204
                                  (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
205
                      & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
206
                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
207
 
208
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
209
                    & ~ex_dslot;
210
 
211
// Abort write into RF by load & other instructions   
212
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
213
                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
214
                                 & !sr_ted & !dsr_te);
215
 
216
// abort spr read/writes   
217
assign abort_mvspr  = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
218
                                     & !sr_ted & !dsr_te) ;
219 10 unneback
assign spr_dat_ppc = wb_pc;
220 185 julius
 
221 10 unneback
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
222
 
223
//
224
// Order defines exception detection priority
225
//
226
assign except_trig = {
227 151 marcus.erl
                      ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
228
                      ex_exceptflags[0]  & ~du_dsr[`OR1200_DU_DSR_IPFE],
229
                      ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
230 185 julius
                      sig_illegal       & ~du_dsr[`OR1200_DU_DSR_IIE],
231 151 marcus.erl
                      sig_align         & ~du_dsr[`OR1200_DU_DSR_AE],
232 185 julius
                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],
233 151 marcus.erl
                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],
234 185 julius
                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
235
                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],
236
                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
237 151 marcus.erl
                      sig_range         & ~du_dsr[`OR1200_DU_DSR_RE],
238 185 julius
                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],
239
                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],
240
                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]
241 151 marcus.erl
                      };
242 185 julius
 
243 141 marcus.erl
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
244
`ifdef OR1200_DU_DMR1_ST
245
    ||  dmr1_st
246
`endif
247
`ifdef OR1200_DU_DMR1_BT
248
    ||  ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
249
`endif
250
    );
251
 
252 10 unneback
assign except_stop = {
253
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
254
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
255
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
256
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
257
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
258
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
259
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
260
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
261
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
262
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
263
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
264 141 marcus.erl
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],
265 185 julius
                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],
266 10 unneback
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
267
                };
268
 
269 141 marcus.erl
always @(posedge clk or posedge rst) begin
270
        if (rst) begin
271 258 julius
                trace_trap  <=  1'b0 ;
272 141 marcus.erl
        end
273
        else if (!(trace_trap && !ex_pc_val)) begin
274 258 julius
                trace_trap  <=  trace_cond & !dsr_te & !sr_ted ;
275 141 marcus.erl
        end
276
end
277
 
278
always @(posedge clk or posedge rst) begin
279
        if (rst) begin
280 258 julius
        ex_freeze_prev  <=  1'b0 ;
281
        sr_ted_prev     <=  1'b0 ;
282
        dsr_te_prev     <=  1'b0 ;
283
        dmr1_st_prev    <=  1'b0 ;
284
        dmr1_bt_prev    <=  1'b0 ;
285 141 marcus.erl
    end
286
    else begin
287 258 julius
        ex_freeze_prev  <=  ex_freeze ;
288 141 marcus.erl
        if (!ex_freeze_prev || ex_void) begin
289 258 julius
            sr_ted_prev     <=  sr     [`OR1200_SR_TED    ] ;
290
            dsr_te_prev     <=  du_dsr [`OR1200_DU_DSR_TE ] ;
291
            dmr1_st_prev    <=  du_dmr1[`OR1200_DU_DMR1_ST] ;
292
            dmr1_bt_prev    <=  du_dmr1[`OR1200_DU_DMR1_BT] ;
293 141 marcus.erl
        end
294
    end
295
end
296
 
297 353 julius
`ifdef verilator
298
   // Function to access wb_pc (for Verilator). Have to hide this from
299
   // simulator, since functions with no inputs are not allowed in IEEE
300
   // 1364-2001.
301
   function [31:0] get_wb_pc;
302
      // verilator public
303
      get_wb_pc = wb_pc;
304
   endfunction // get_wb_pc
305
 
306
   // Function to access id_pc (for Verilator). Have to hide this from
307
   // simulator, since functions with no inputs are not allowed in IEEE
308
   // 1364-2001.
309
   function [31:0] get_id_pc;
310
      // verilator public
311
      get_id_pc = id_pc;
312
   endfunction // get_id_pc
313
 
314
   // Function to access ex_pc (for Verilator). Have to hide this from
315
   // simulator, since functions with no inputs are not allowed in IEEE
316
   // 1364-2001.
317
   function [31:0] get_ex_pc;
318
      // verilator public
319
      get_ex_pc = ex_pc;
320
   endfunction // get_ex_pc
321
   // Function to access except_type[3:0] (for Verilator). Have to hide this from
322
   // simulator, since functions with no inputs are not allowed in IEEE
323
   // 1364-2001.
324
   function [3:0] get_except_type;
325
      // verilator public
326
      get_except_type = except_type;
327
   endfunction // get_except_type
328
 
329
`endif
330
 
331
 
332 10 unneback
//
333
// PC and Exception flags pipelines
334
//
335
always @(posedge clk or posedge rst) begin
336
        if (rst) begin
337 258 julius
                id_pc <=  32'd0;
338
        id_pc_val <=  1'b0 ;
339
                id_exceptflags <=  3'b000;
340 10 unneback
        end
341 141 marcus.erl
        else if (id_flushpipe) begin
342 258 julius
        id_pc_val <=  1'b0 ;
343
                id_exceptflags <=  3'b000;
344 10 unneback
        end
345
        else if (!id_freeze) begin
346 258 julius
                id_pc <=  if_pc;
347
        id_pc_val <=  1'b1 ;
348
                id_exceptflags <=  { sig_ibuserr, sig_itlbmiss, sig_immufault };
349 10 unneback
        end
350
end
351
 
352
//
353
// delayed_iee
354
//
355
// SR[IEE] should not enable interrupts right away
356
// when it is restored with l.rfe. Instead delayed_iee
357
// together with SR[IEE] enables interrupts once
358
// pipeline is again ready.
359
//
360
always @(posedge rst or posedge clk)
361
        if (rst)
362 258 julius
                delayed_iee <=  3'b000;
363 10 unneback
        else if (!sr[`OR1200_SR_IEE])
364 258 julius
                delayed_iee <=  3'b000;
365 10 unneback
        else
366 258 julius
                delayed_iee <=  {delayed_iee[1:0], 1'b1};
367 10 unneback
 
368
//
369
// delayed_tee
370
//
371
// SR[TEE] should not enable tick exceptions right away
372
// when it is restored with l.rfe. Instead delayed_tee
373
// together with SR[TEE] enables tick exceptions once
374
// pipeline is again ready.
375
//
376
always @(posedge rst or posedge clk)
377
        if (rst)
378 258 julius
                delayed_tee <=  3'b000;
379 10 unneback
        else if (!sr[`OR1200_SR_TEE])
380 258 julius
                delayed_tee <=  3'b000;
381 10 unneback
        else
382 258 julius
                delayed_tee <=  {delayed_tee[1:0], 1'b1};
383 10 unneback
 
384
//
385
// PC and Exception flags pipelines
386
//
387
always @(posedge clk or posedge rst) begin
388
        if (rst) begin
389 258 julius
                ex_dslot <=  1'b0;
390
                ex_pc <=  32'd0;
391
                ex_pc_val <=  1'b0 ;
392
                ex_exceptflags <=  3'b000;
393
                delayed1_ex_dslot <=  1'b0;
394
                delayed2_ex_dslot <=  1'b0;
395 10 unneback
        end
396 141 marcus.erl
        else if (ex_flushpipe) begin
397 258 julius
                ex_dslot <=  1'b0;
398
                ex_pc_val <=  1'b0 ;
399
                ex_exceptflags <=  3'b000;
400
                delayed1_ex_dslot <=  1'b0;
401
                delayed2_ex_dslot <=  1'b0;
402 10 unneback
        end
403
        else if (!ex_freeze & id_freeze) begin
404 258 julius
                ex_dslot <=  1'b0;
405
                ex_pc <=  id_pc;
406
                ex_pc_val <=  id_pc_val ;
407
                ex_exceptflags <=  3'b000;
408
                delayed1_ex_dslot <=  ex_dslot;
409
                delayed2_ex_dslot <=  delayed1_ex_dslot;
410 10 unneback
        end
411
        else if (!ex_freeze) begin
412 258 julius
                ex_dslot <=  ex_branch_taken;
413
                ex_pc <=  id_pc;
414
                ex_pc_val <=  id_pc_val ;
415
                ex_exceptflags <=  id_exceptflags;
416
                delayed1_ex_dslot <=  ex_dslot;
417
                delayed2_ex_dslot <=  delayed1_ex_dslot;
418 10 unneback
        end
419
end
420
 
421
//
422
// PC and Exception flags pipelines
423
//
424
always @(posedge clk or posedge rst) begin
425
        if (rst) begin
426 258 julius
                wb_pc <=  32'd0;
427
        dl_pc <=  32'd0;
428 10 unneback
        end
429
        else if (!wb_freeze) begin
430 258 julius
                wb_pc <=  ex_pc;
431
        dl_pc <=  wb_pc;
432 10 unneback
        end
433
end
434
 
435
//
436
// We have started execution of exception handler:
437
//  1. Asserted for 3 clock cycles
438
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
439
//
440
assign except_flushpipe = |except_trig & ~|state;
441
 
442
//
443
// Exception FSM that sequences execution of exception handler
444
//
445
// except_type signals which exception handler we start fetching in:
446
//  1. Asserted in next clock cycle after exception is recognized
447
//
448 185 julius
   always @(posedge clk or posedge rst) begin
449
      if (rst) begin
450 258 julius
         state <=  `OR1200_EXCEPTFSM_IDLE;
451
         except_type <=  `OR1200_EXCEPT_NONE;
452
         extend_flush <=  1'b0;
453
         epcr <=  32'b0;
454
         eear <=  32'b0;
455
         esr <=  {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
456
         extend_flush_last <=  1'b0;
457 185 julius
      end
458
      else begin
459 10 unneback
`ifdef OR1200_CASE_DEFAULT
460 185 julius
         case (state)   // synopsys parallel_case
461 10 unneback
`else
462 185 julius
           case (state) // synopsys full_case parallel_case
463 10 unneback
`endif
464 185 julius
             `OR1200_EXCEPTFSM_IDLE:
465
               if (except_flushpipe) begin
466 258 julius
                  state <=  `OR1200_EXCEPTFSM_FLU1;
467
                  extend_flush <=  1'b1;
468
                  esr <=  sr_we ? to_sr : sr;
469 185 julius
                  casex (except_trig)
470 151 marcus.erl
`ifdef OR1200_EXCEPT_ITLBMISS
471 185 julius
                    14'b1x_xxxx_xxxx_xxxx: begin
472 258 julius
                       except_type <=  `OR1200_EXCEPT_ITLBMISS;
473
                       eear <=  ex_dslot ?
474 185 julius
                               ex_pc : ex_pc;
475 258 julius
                       epcr <=  ex_dslot ?
476 185 julius
                               wb_pc : ex_pc;
477
                    end
478 10 unneback
`endif
479
`ifdef OR1200_EXCEPT_IPF
480 185 julius
                    14'b01_xxxx_xxxx_xxxx: begin
481 258 julius
                       except_type <=  `OR1200_EXCEPT_IPF;
482
                       eear <=  ex_dslot ?
483 185 julius
                               ex_pc : delayed1_ex_dslot ?
484
                               id_pc : delayed2_ex_dslot ?
485
                               id_pc : id_pc;
486 258 julius
                       epcr <=  ex_dslot ?
487 185 julius
                               wb_pc : delayed1_ex_dslot ?
488
                               id_pc : delayed2_ex_dslot ?
489
                               id_pc : id_pc;
490
                    end
491 10 unneback
`endif
492
`ifdef OR1200_EXCEPT_BUSERR
493 185 julius
                    14'b00_1xxx_xxxx_xxxx: begin        // Insn. Bus Error
494 258 julius
                       except_type <=  `OR1200_EXCEPT_BUSERR;
495
                       eear <=  ex_dslot ?
496 185 julius
                               wb_pc : ex_pc;
497 258 julius
                       epcr <=  ex_dslot ?
498 185 julius
                               wb_pc : ex_pc;
499
                    end
500 10 unneback
`endif
501
`ifdef OR1200_EXCEPT_ILLEGAL
502 185 julius
                    14'b00_01xx_xxxx_xxxx: begin
503 258 julius
                       except_type <=  `OR1200_EXCEPT_ILLEGAL;
504
                       eear <=  ex_pc;
505
                       epcr <=  ex_dslot ?
506 185 julius
                               wb_pc : ex_pc;
507
                    end
508 10 unneback
`endif
509
`ifdef OR1200_EXCEPT_ALIGN
510 185 julius
                    14'b00_001x_xxxx_xxxx: begin
511 258 julius
                       except_type <=  `OR1200_EXCEPT_ALIGN;
512
                       eear <=  lsu_addr;
513
                       epcr <=  ex_dslot ?
514 185 julius
                               wb_pc : ex_pc;
515
                    end
516 10 unneback
`endif
517
`ifdef OR1200_EXCEPT_DTLBMISS
518 185 julius
                    14'b00_0001_xxxx_xxxx: begin
519 258 julius
                       except_type <=  `OR1200_EXCEPT_DTLBMISS;
520
                       eear <=  lsu_addr;
521
                       epcr <=  ex_dslot ?
522 185 julius
                               wb_pc : delayed1_ex_dslot ?
523
                               dl_pc : ex_pc;
524
                    end
525 10 unneback
`endif
526 185 julius
`ifdef OR1200_EXCEPT_TRAP
527
                    14'b00_0000_1xxx_xxxx: begin
528 258 julius
                       except_type <=  `OR1200_EXCEPT_TRAP;
529
                       epcr <=  ex_dslot ?
530 185 julius
                               wb_pc : delayed1_ex_dslot ?
531
                               id_pc : ex_pc;
532
                    end
533 151 marcus.erl
`endif
534
`ifdef OR1200_EXCEPT_SYSCALL
535 185 julius
                    14'b00_0000_01xx_xxxx: begin
536 258 julius
                       except_type <=  `OR1200_EXCEPT_SYSCALL;
537
                       epcr <=  ex_dslot ?
538 185 julius
                               wb_pc : delayed1_ex_dslot ?
539
                               id_pc : delayed2_ex_dslot ?
540
                               id_pc : id_pc;
541
                    end
542 151 marcus.erl
`endif
543 10 unneback
`ifdef OR1200_EXCEPT_DPF
544 185 julius
                    14'b00_0000_001x_xxxx: begin
545 258 julius
                       except_type <=  `OR1200_EXCEPT_DPF;
546
                       eear <=  lsu_addr;
547
                       epcr <=  ex_dslot ?
548 185 julius
                               wb_pc : delayed1_ex_dslot ?
549
                               dl_pc : ex_pc;
550
                    end
551 10 unneback
`endif
552
`ifdef OR1200_EXCEPT_BUSERR
553 185 julius
                    14'b00_0000_0001_xxxx: begin        // Data Bus Error
554 258 julius
                       except_type <=  `OR1200_EXCEPT_BUSERR;
555
                       eear <=  lsu_addr;
556
                       epcr <=  ex_dslot ?
557 185 julius
                               wb_pc : delayed1_ex_dslot ?
558
                               dl_pc : ex_pc;
559
                    end
560 10 unneback
`endif
561
`ifdef OR1200_EXCEPT_RANGE
562 185 julius
                    14'b00_0000_0000_1xxx: begin
563 258 julius
                       except_type <=  `OR1200_EXCEPT_RANGE;
564
                       epcr <=  ex_dslot ?
565 185 julius
                               wb_pc : delayed1_ex_dslot ?
566
                               id_pc : delayed2_ex_dslot ?
567
                               id_pc : id_pc;
568
                    end
569 10 unneback
`endif
570 185 julius
`ifdef OR1200_EXCEPT_FLOAT
571
                    14'b00_0000_0000_01xx: begin
572 258 julius
                       except_type <=  `OR1200_EXCEPT_FLOAT;
573
                       epcr <=  id_pc;
574 185 julius
                    end
575
`endif
576 151 marcus.erl
`ifdef OR1200_EXCEPT_INT
577 185 julius
                    14'b00_0000_0000_001x: begin
578 258 julius
                       except_type <=  `OR1200_EXCEPT_INT;
579
                       epcr <=  id_pc;
580 185 julius
                    end
581 10 unneback
`endif
582 151 marcus.erl
`ifdef OR1200_EXCEPT_TICK
583 185 julius
                    14'b00_0000_0000_0001: begin
584 258 julius
                       except_type <=  `OR1200_EXCEPT_TICK;
585
                       epcr <=  id_pc;
586 185 julius
                    end
587 10 unneback
`endif
588 185 julius
                    default:
589 258 julius
                      except_type <=  `OR1200_EXCEPT_NONE;
590 185 julius
                  endcase
591
               end
592
               else if (pc_we) begin
593 258 julius
                  state <=  `OR1200_EXCEPTFSM_FLU1;
594
                  extend_flush <=  1'b1;
595 185 julius
               end
596
               else begin
597
                  if (epcr_we)
598 258 julius
                    epcr <=  datain;
599 185 julius
                  if (eear_we)
600 258 julius
                    eear <=  datain;
601 185 julius
                  if (esr_we)
602 258 julius
                    esr <=  {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
603 185 julius
               end
604
             `OR1200_EXCEPTFSM_FLU1:
605
               if (icpu_ack_i | icpu_err_i | genpc_freeze)
606 258 julius
                 state <=  `OR1200_EXCEPTFSM_FLU2;
607 185 julius
             `OR1200_EXCEPTFSM_FLU2:
608 10 unneback
`ifdef OR1200_EXCEPT_TRAP
609 185 julius
               if (except_type == `OR1200_EXCEPT_TRAP) begin
610 258 julius
                  state <=  `OR1200_EXCEPTFSM_IDLE;
611
                  extend_flush <=  1'b0;
612
                  extend_flush_last <=  1'b0;
613
                  except_type <=  `OR1200_EXCEPT_NONE;
614 185 julius
               end
615
               else
616 10 unneback
`endif
617 258 julius
                 state <=  `OR1200_EXCEPTFSM_FLU3;
618 185 julius
             `OR1200_EXCEPTFSM_FLU3:
619
               begin
620 258 julius
                  state <=  `OR1200_EXCEPTFSM_FLU4;
621 185 julius
               end
622
             `OR1200_EXCEPTFSM_FLU4: begin
623 258 julius
                state <=  `OR1200_EXCEPTFSM_FLU5;
624
                extend_flush <=  1'b0;
625
                extend_flush_last <=  1'b0; // damjan
626 185 julius
             end
627 10 unneback
`ifdef OR1200_CASE_DEFAULT
628 185 julius
             default: begin
629 10 unneback
`else
630 185 julius
                `OR1200_EXCEPTFSM_FLU5: begin
631 10 unneback
`endif
632 185 julius
                   if (!if_stall && !id_freeze) begin
633 258 julius
                      state <=  `OR1200_EXCEPTFSM_IDLE;
634
                      except_type <=  `OR1200_EXCEPT_NONE;
635
                      extend_flush_last <=  1'b0;
636 185 julius
                   end
637
                end
638
           endcase
639
         end
640
   end
641 10 unneback
 
642
endmodule

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