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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Exception logic                                    ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Handles all OR1K exceptions inside CPU block.               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 151 marcus.erl
// $Log: or1200_except.v,v $
45 10 unneback
//
46 141 marcus.erl
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
`define OR1200_EXCEPTFSM_WIDTH 3
56
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
57
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
58
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
59
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
60
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
61
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
62
 
63
//
64
// Exception recognition and sequencing
65
//
66
 
67 185 julius
module or1200_except
68
  (
69
   // Clock and reset
70
   clk, rst,
71
 
72
   // Internal i/f
73
   sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
74
   sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
75
   sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
76
   if_stall,  if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
77
   extend_flush, except_flushpipe, except_type, except_start, except_started,
78
   except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
79
   spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
80
   du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
81
   abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee
82
 
83 10 unneback
);
84
 
85
//
86
// I/O
87
//
88
input                           clk;
89
input                           rst;
90
input                           sig_ibuserr;
91
input                           sig_dbuserr;
92
input                           sig_illegal;
93
input                           sig_align;
94
input                           sig_range;
95
input                           sig_dtlbmiss;
96
input                           sig_dmmufault;
97
input                           sig_int;
98
input                           sig_syscall;
99
input                           sig_trap;
100
input                           sig_itlbmiss;
101
input                           sig_immufault;
102
input                           sig_tick;
103 185 julius
input                           sig_fp;
104
input                           fpcsr_fpee;
105 141 marcus.erl
input                           ex_branch_taken;
106 10 unneback
input                           genpc_freeze;
107
input                           id_freeze;
108
input                           ex_freeze;
109
input                           wb_freeze;
110
input                           if_stall;
111 141 marcus.erl
input   [31:0]           if_pc;
112
output  [31:0]           id_pc;
113
output  [31:0]      ex_pc;
114
output  [31:0]      wb_pc;
115
input   [31:0]           datain;
116 10 unneback
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
117 141 marcus.erl
input   [24:0]                       du_dmr1;
118
input                   du_hwbkpt;
119
input                   du_hwbkpt_ls_r;
120 10 unneback
input                           epcr_we;
121
input                           eear_we;
122
input                           esr_we;
123
input                           pc_we;
124
output  [31:0]                   epcr;
125
output  [31:0]                   eear;
126
output  [`OR1200_SR_WIDTH-1:0]   esr;
127
input   [`OR1200_SR_WIDTH-1:0]   to_sr;
128
input                           sr_we;
129
input   [`OR1200_SR_WIDTH-1:0]   sr;
130
input   [31:0]                   lsu_addr;
131 141 marcus.erl
input                   id_flushpipe;
132
input                   ex_flushpipe;
133
output                          except_flushpipe;
134 10 unneback
output                          extend_flush;
135
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
136
output                          except_start;
137
output                          except_started;
138 185 julius
output  [13:0]           except_stop;
139
output  [13:0]           except_trig;
140 10 unneback
input                           ex_void;
141 141 marcus.erl
input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
142 10 unneback
output  [31:0]                   spr_dat_ppc;
143
output  [31:0]                   spr_dat_npc;
144
output                          abort_ex;
145 141 marcus.erl
output              abort_mvspr;
146 10 unneback
input                           icpu_ack_i;
147
input                           icpu_err_i;
148
input                           dcpu_ack_i;
149
input                           dcpu_err_i;
150
 
151
//
152
// Internal regs and wires
153
//
154
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
155
reg     [31:0]                   id_pc;
156 141 marcus.erl
reg                 id_pc_val;
157 10 unneback
reg     [31:0]                   ex_pc;
158 141 marcus.erl
reg                 ex_pc_val;
159 10 unneback
reg     [31:0]                   wb_pc;
160 141 marcus.erl
reg [31:0]          dl_pc;
161 10 unneback
reg     [31:0]                   epcr;
162
reg     [31:0]                   eear;
163
reg     [`OR1200_SR_WIDTH-1:0]           esr;
164
reg     [2:0]                    id_exceptflags;
165
reg     [2:0]                    ex_exceptflags;
166
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
167
reg                             extend_flush;
168
reg                             extend_flush_last;
169
reg                             ex_dslot;
170
reg                             delayed1_ex_dslot;
171
reg                             delayed2_ex_dslot;
172
wire                            except_started;
173
reg     [2:0]                    delayed_iee;
174
reg     [2:0]                    delayed_tee;
175
wire                            int_pending;
176
wire                            tick_pending;
177 185 julius
wire                            fp_pending;
178
 
179 141 marcus.erl
reg trace_trap      ;
180
reg ex_freeze_prev;
181
reg sr_ted_prev;
182
reg dsr_te_prev;
183
reg dmr1_st_prev    ;
184
reg dmr1_bt_prev    ;
185
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
186
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
187
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
188
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
189 10 unneback
 
190
//
191
// Simple combinatorial logic
192
//
193
assign except_started = extend_flush & except_start;
194 185 julius
 
195 141 marcus.erl
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
196 185 julius
 
197
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
198
                                (sr_we & to_sr[`OR1200_SR_IEE]))
199
                    & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
200
                     & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
201
 
202
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
203
                                  (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
204
                      & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
205
                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
206
 
207
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
208
                    & ~ex_dslot;
209
 
210
// Abort write into RF by load & other instructions   
211
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
212
                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
213
                                 & !sr_ted & !dsr_te);
214
 
215
// abort spr read/writes   
216
assign abort_mvspr  = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
217
                                     & !sr_ted & !dsr_te) ;
218 10 unneback
assign spr_dat_ppc = wb_pc;
219 185 julius
 
220 10 unneback
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
221
 
222
//
223
// Order defines exception detection priority
224
//
225
assign except_trig = {
226 151 marcus.erl
                      ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
227
                      ex_exceptflags[0]  & ~du_dsr[`OR1200_DU_DSR_IPFE],
228
                      ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
229 185 julius
                      sig_illegal       & ~du_dsr[`OR1200_DU_DSR_IIE],
230 151 marcus.erl
                      sig_align         & ~du_dsr[`OR1200_DU_DSR_AE],
231 185 julius
                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],
232 151 marcus.erl
                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],
233 185 julius
                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
234
                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],
235
                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
236 151 marcus.erl
                      sig_range         & ~du_dsr[`OR1200_DU_DSR_RE],
237 185 julius
                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],
238
                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],
239
                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]
240 151 marcus.erl
                      };
241 185 julius
 
242 141 marcus.erl
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
243
`ifdef OR1200_DU_DMR1_ST
244
    ||  dmr1_st
245
`endif
246
`ifdef OR1200_DU_DMR1_BT
247
    ||  ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
248
`endif
249
    );
250
 
251 10 unneback
assign except_stop = {
252
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
253
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
254
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
255
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
256
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
257
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
258
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
259
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
260
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
261
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
262
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
263 141 marcus.erl
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],
264 185 julius
                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],
265 10 unneback
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
266
                };
267
 
268 141 marcus.erl
always @(posedge clk or posedge rst) begin
269
        if (rst) begin
270
                trace_trap  <= #1 1'b0 ;
271
        end
272
        else if (!(trace_trap && !ex_pc_val)) begin
273
                trace_trap  <= #1 trace_cond & !dsr_te & !sr_ted ;
274
        end
275
end
276
 
277
always @(posedge clk or posedge rst) begin
278
        if (rst) begin
279
        ex_freeze_prev  <= #1 1'b0 ;
280
        sr_ted_prev     <= #1 1'b0 ;
281
        dsr_te_prev     <= #1 1'b0 ;
282
        dmr1_st_prev    <= #1 1'b0 ;
283
        dmr1_bt_prev    <= #1 1'b0 ;
284
    end
285
    else begin
286
        ex_freeze_prev  <= #1 ex_freeze ;
287
        if (!ex_freeze_prev || ex_void) begin
288
            sr_ted_prev     <= #1 sr     [`OR1200_SR_TED    ] ;
289
            dsr_te_prev     <= #1 du_dsr [`OR1200_DU_DSR_TE ] ;
290
            dmr1_st_prev    <= #1 du_dmr1[`OR1200_DU_DMR1_ST] ;
291
            dmr1_bt_prev    <= #1 du_dmr1[`OR1200_DU_DMR1_BT] ;
292
        end
293
    end
294
end
295
 
296 10 unneback
//
297
// PC and Exception flags pipelines
298
//
299
always @(posedge clk or posedge rst) begin
300
        if (rst) begin
301
                id_pc <= #1 32'd0;
302 141 marcus.erl
        id_pc_val <= #1 1'b0 ;
303 10 unneback
                id_exceptflags <= #1 3'b000;
304
        end
305 141 marcus.erl
        else if (id_flushpipe) begin
306
        id_pc_val <= #1 1'b0 ;
307 10 unneback
                id_exceptflags <= #1 3'b000;
308
        end
309
        else if (!id_freeze) begin
310
                id_pc <= #1 if_pc;
311 141 marcus.erl
        id_pc_val <= #1 1'b1 ;
312 10 unneback
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
313
        end
314
end
315
 
316
//
317
// delayed_iee
318
//
319
// SR[IEE] should not enable interrupts right away
320
// when it is restored with l.rfe. Instead delayed_iee
321
// together with SR[IEE] enables interrupts once
322
// pipeline is again ready.
323
//
324
always @(posedge rst or posedge clk)
325
        if (rst)
326
                delayed_iee <= #1 3'b000;
327
        else if (!sr[`OR1200_SR_IEE])
328
                delayed_iee <= #1 3'b000;
329
        else
330
                delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
331
 
332
//
333
// delayed_tee
334
//
335
// SR[TEE] should not enable tick exceptions right away
336
// when it is restored with l.rfe. Instead delayed_tee
337
// together with SR[TEE] enables tick exceptions once
338
// pipeline is again ready.
339
//
340
always @(posedge rst or posedge clk)
341
        if (rst)
342
                delayed_tee <= #1 3'b000;
343
        else if (!sr[`OR1200_SR_TEE])
344
                delayed_tee <= #1 3'b000;
345
        else
346
                delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
347
 
348
//
349
// PC and Exception flags pipelines
350
//
351
always @(posedge clk or posedge rst) begin
352
        if (rst) begin
353
                ex_dslot <= #1 1'b0;
354
                ex_pc <= #1 32'd0;
355 185 julius
                ex_pc_val <= #1 1'b0 ;
356 10 unneback
                ex_exceptflags <= #1 3'b000;
357
                delayed1_ex_dslot <= #1 1'b0;
358
                delayed2_ex_dslot <= #1 1'b0;
359
        end
360 141 marcus.erl
        else if (ex_flushpipe) begin
361 10 unneback
                ex_dslot <= #1 1'b0;
362 185 julius
                ex_pc_val <= #1 1'b0 ;
363 10 unneback
                ex_exceptflags <= #1 3'b000;
364
                delayed1_ex_dslot <= #1 1'b0;
365
                delayed2_ex_dslot <= #1 1'b0;
366
        end
367
        else if (!ex_freeze & id_freeze) begin
368
                ex_dslot <= #1 1'b0;
369
                ex_pc <= #1 id_pc;
370 185 julius
                ex_pc_val <= #1 id_pc_val ;
371 10 unneback
                ex_exceptflags <= #1 3'b000;
372
                delayed1_ex_dslot <= #1 ex_dslot;
373
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
374
        end
375
        else if (!ex_freeze) begin
376 141 marcus.erl
                ex_dslot <= #1 ex_branch_taken;
377 10 unneback
                ex_pc <= #1 id_pc;
378 185 julius
                ex_pc_val <= #1 id_pc_val ;
379 10 unneback
                ex_exceptflags <= #1 id_exceptflags;
380
                delayed1_ex_dslot <= #1 ex_dslot;
381
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
382
        end
383
end
384
 
385
//
386
// PC and Exception flags pipelines
387
//
388
always @(posedge clk or posedge rst) begin
389
        if (rst) begin
390
                wb_pc <= #1 32'd0;
391 141 marcus.erl
        dl_pc <= #1 32'd0;
392 10 unneback
        end
393
        else if (!wb_freeze) begin
394
                wb_pc <= #1 ex_pc;
395 141 marcus.erl
        dl_pc <= #1 wb_pc;
396 10 unneback
        end
397
end
398
 
399
//
400
// We have started execution of exception handler:
401
//  1. Asserted for 3 clock cycles
402
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
403
//
404
assign except_flushpipe = |except_trig & ~|state;
405
 
406
//
407
// Exception FSM that sequences execution of exception handler
408
//
409
// except_type signals which exception handler we start fetching in:
410
//  1. Asserted in next clock cycle after exception is recognized
411
//
412 185 julius
   always @(posedge clk or posedge rst) begin
413
      if (rst) begin
414
         state <= #1 `OR1200_EXCEPTFSM_IDLE;
415
         except_type <= #1 `OR1200_EXCEPT_NONE;
416
         extend_flush <= #1 1'b0;
417
         epcr <= #1 32'b0;
418
         eear <= #1 32'b0;
419
         esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
420
         extend_flush_last <= #1 1'b0;
421
      end
422
      else begin
423 10 unneback
`ifdef OR1200_CASE_DEFAULT
424 185 julius
         case (state)   // synopsys parallel_case
425 10 unneback
`else
426 185 julius
           case (state) // synopsys full_case parallel_case
427 10 unneback
`endif
428 185 julius
             `OR1200_EXCEPTFSM_IDLE:
429
               if (except_flushpipe) begin
430
                  state <= #1 `OR1200_EXCEPTFSM_FLU1;
431
                  extend_flush <= #1 1'b1;
432
                  esr <= #1 sr_we ? to_sr : sr;
433
                  casex (except_trig)
434 151 marcus.erl
`ifdef OR1200_EXCEPT_ITLBMISS
435 185 julius
                    14'b1x_xxxx_xxxx_xxxx: begin
436
                       except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
437
                       eear <= #1 ex_dslot ?
438
                               ex_pc : ex_pc;
439
                       epcr <= #1 ex_dslot ?
440
                               wb_pc : ex_pc;
441
                    end
442 10 unneback
`endif
443
`ifdef OR1200_EXCEPT_IPF
444 185 julius
                    14'b01_xxxx_xxxx_xxxx: begin
445
                       except_type <= #1 `OR1200_EXCEPT_IPF;
446
                       eear <= #1 ex_dslot ?
447
                               ex_pc : delayed1_ex_dslot ?
448
                               id_pc : delayed2_ex_dslot ?
449
                               id_pc : id_pc;
450
                       epcr <= #1 ex_dslot ?
451
                               wb_pc : delayed1_ex_dslot ?
452
                               id_pc : delayed2_ex_dslot ?
453
                               id_pc : id_pc;
454
                    end
455 10 unneback
`endif
456
`ifdef OR1200_EXCEPT_BUSERR
457 185 julius
                    14'b00_1xxx_xxxx_xxxx: begin        // Insn. Bus Error
458
                       except_type <= #1 `OR1200_EXCEPT_BUSERR;
459
                       eear <= #1 ex_dslot ?
460
                               wb_pc : ex_pc;
461
                       epcr <= #1 ex_dslot ?
462
                               wb_pc : ex_pc;
463
                    end
464 10 unneback
`endif
465
`ifdef OR1200_EXCEPT_ILLEGAL
466 185 julius
                    14'b00_01xx_xxxx_xxxx: begin
467
                       except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
468
                       eear <= #1 ex_pc;
469
                       epcr <= #1 ex_dslot ?
470
                               wb_pc : ex_pc;
471
                    end
472 10 unneback
`endif
473
`ifdef OR1200_EXCEPT_ALIGN
474 185 julius
                    14'b00_001x_xxxx_xxxx: begin
475
                       except_type <= #1 `OR1200_EXCEPT_ALIGN;
476
                       eear <= #1 lsu_addr;
477
                       epcr <= #1 ex_dslot ?
478
                               wb_pc : ex_pc;
479
                    end
480 10 unneback
`endif
481
`ifdef OR1200_EXCEPT_DTLBMISS
482 185 julius
                    14'b00_0001_xxxx_xxxx: begin
483
                       except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
484
                       eear <= #1 lsu_addr;
485
                       epcr <= #1 ex_dslot ?
486
                               wb_pc : delayed1_ex_dslot ?
487
                               dl_pc : ex_pc;
488
                    end
489 10 unneback
`endif
490 185 julius
`ifdef OR1200_EXCEPT_TRAP
491
                    14'b00_0000_1xxx_xxxx: begin
492
                       except_type <= #1 `OR1200_EXCEPT_TRAP;
493
                       epcr <= #1 ex_dslot ?
494
                               wb_pc : delayed1_ex_dslot ?
495
                               id_pc : ex_pc;
496
                    end
497 151 marcus.erl
`endif
498
`ifdef OR1200_EXCEPT_SYSCALL
499 185 julius
                    14'b00_0000_01xx_xxxx: begin
500
                       except_type <= #1 `OR1200_EXCEPT_SYSCALL;
501
                       epcr <= #1 ex_dslot ?
502
                               wb_pc : delayed1_ex_dslot ?
503
                               id_pc : delayed2_ex_dslot ?
504
                               id_pc : id_pc;
505
                    end
506 151 marcus.erl
`endif
507 10 unneback
`ifdef OR1200_EXCEPT_DPF
508 185 julius
                    14'b00_0000_001x_xxxx: begin
509
                       except_type <= #1 `OR1200_EXCEPT_DPF;
510
                       eear <= #1 lsu_addr;
511
                       epcr <= #1 ex_dslot ?
512
                               wb_pc : delayed1_ex_dslot ?
513
                               dl_pc : ex_pc;
514
                    end
515 10 unneback
`endif
516
`ifdef OR1200_EXCEPT_BUSERR
517 185 julius
                    14'b00_0000_0001_xxxx: begin        // Data Bus Error
518
                       except_type <= #1 `OR1200_EXCEPT_BUSERR;
519
                       eear <= #1 lsu_addr;
520
                       epcr <= #1 ex_dslot ?
521
                               wb_pc : delayed1_ex_dslot ?
522
                               dl_pc : ex_pc;
523
                    end
524 10 unneback
`endif
525
`ifdef OR1200_EXCEPT_RANGE
526 185 julius
                    14'b00_0000_0000_1xxx: begin
527
                       except_type <= #1 `OR1200_EXCEPT_RANGE;
528
                       epcr <= #1 ex_dslot ?
529
                               wb_pc : delayed1_ex_dslot ?
530
                               id_pc : delayed2_ex_dslot ?
531
                               id_pc : id_pc;
532
                    end
533 10 unneback
`endif
534 185 julius
`ifdef OR1200_EXCEPT_FLOAT
535
                    14'b00_0000_0000_01xx: begin
536
                       except_type <= #1 `OR1200_EXCEPT_FLOAT;
537
                       epcr <= #1 id_pc;
538
                    end
539
`endif
540 151 marcus.erl
`ifdef OR1200_EXCEPT_INT
541 185 julius
                    14'b00_0000_0000_001x: begin
542
                       except_type <= #1 `OR1200_EXCEPT_INT;
543
                       epcr <= #1 id_pc;
544
                    end
545 10 unneback
`endif
546 151 marcus.erl
`ifdef OR1200_EXCEPT_TICK
547 185 julius
                    14'b00_0000_0000_0001: begin
548
                       except_type <= #1 `OR1200_EXCEPT_TICK;
549
                       epcr <= #1 id_pc;
550
                    end
551 10 unneback
`endif
552 185 julius
                    default:
553
                      except_type <= #1 `OR1200_EXCEPT_NONE;
554
                  endcase
555
               end
556
               else if (pc_we) begin
557
                  state <= #1 `OR1200_EXCEPTFSM_FLU1;
558
                  extend_flush <= #1 1'b1;
559
               end
560
               else begin
561
                  if (epcr_we)
562
                    epcr <= #1 datain;
563
                  if (eear_we)
564
                    eear <= #1 datain;
565
                  if (esr_we)
566
                    esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
567
               end
568
             `OR1200_EXCEPTFSM_FLU1:
569
               if (icpu_ack_i | icpu_err_i | genpc_freeze)
570
                 state <= #1 `OR1200_EXCEPTFSM_FLU2;
571
             `OR1200_EXCEPTFSM_FLU2:
572 10 unneback
`ifdef OR1200_EXCEPT_TRAP
573 185 julius
               if (except_type == `OR1200_EXCEPT_TRAP) begin
574
                  state <= #1 `OR1200_EXCEPTFSM_IDLE;
575
                  extend_flush <= #1 1'b0;
576
                  extend_flush_last <= #1 1'b0;
577
                  except_type <= #1 `OR1200_EXCEPT_NONE;
578
               end
579
               else
580 10 unneback
`endif
581 185 julius
                 state <= #1 `OR1200_EXCEPTFSM_FLU3;
582
             `OR1200_EXCEPTFSM_FLU3:
583
               begin
584
                  state <= #1 `OR1200_EXCEPTFSM_FLU4;
585
               end
586
             `OR1200_EXCEPTFSM_FLU4: begin
587
                state <= #1 `OR1200_EXCEPTFSM_FLU5;
588
                extend_flush <= #1 1'b0;
589
                extend_flush_last <= #1 1'b0; // damjan
590
             end
591 10 unneback
`ifdef OR1200_CASE_DEFAULT
592 185 julius
             default: begin
593 10 unneback
`else
594 185 julius
                `OR1200_EXCEPTFSM_FLU5: begin
595 10 unneback
`endif
596 185 julius
                   if (!if_stall && !id_freeze) begin
597
                      state <= #1 `OR1200_EXCEPTFSM_IDLE;
598
                      except_type <= #1 `OR1200_EXCEPT_NONE;
599
                      extend_flush_last <= #1 1'b0;
600
                   end
601
                end
602
           endcase
603
         end
604
   end
605 10 unneback
 
606
endmodule

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