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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_addsub.v] - Blame information for rev 258

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1 258 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  or1200_fpu_addsub                                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
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////  addition/subtraction entity for the addition/subtraction    ////
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////  unit                                                        ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Original design (FPU100) -                            ////
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////        Jidan Al-eryani, jidan@gmx.net                        ////
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////      - Conv. to Verilog and inclusion in OR1200 -            ////
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////        Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//  Copyright (C) 2006, 2010
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//
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//      This source file may be used and distributed without        
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//      restriction provided that this copyright statement is not   
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//      removed from the file and that any derivative work contains 
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//      the original copyright notice and the associated disclaimer.
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//                                                           
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//              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
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//      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
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//      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
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//      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
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//      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
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//      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
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//      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
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//      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
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//      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
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//      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
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//      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
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//      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
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//      POSSIBILITY OF SUCH DAMAGE. 
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//
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module or1200_fpu_addsub(
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                 clk_i,
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                 fpu_op_i,
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                 fracta_i,
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                 fractb_i,
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                 signa_i,
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                 signb_i,
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                 fract_o,
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                 sign_o);
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   parameter FP_WIDTH = 32;
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   parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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   parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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   parameter FRAC_WIDTH = 23;
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   parameter EXP_WIDTH = 8;
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   parameter ZERO_VECTOR = 31'd0;
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   parameter INF = 31'b1111111100000000000000000000000;
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   parameter QNAN = 31'b1111111110000000000000000000000;
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   parameter SNAN = 31'b1111111100000000000000000000001;
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   input clk_i;
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   input fpu_op_i;
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   input [FRAC_WIDTH+4:0] fracta_i;
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   input [FRAC_WIDTH+4:0] fractb_i;
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   input                  signa_i;
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   input                  signb_i;
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   output reg [FRAC_WIDTH+4:0] fract_o;
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   output reg                  sign_o;
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   wire [FRAC_WIDTH+4:0]       s_fracta_i;
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   wire [FRAC_WIDTH+4:0]       s_fractb_i;
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   wire [FRAC_WIDTH+4:0]       s_fract_o;
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   wire                        s_signa_i, s_signb_i, s_sign_o;
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   wire                        s_fpu_op_i;
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   wire                        fracta_gt_fractb;
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   wire                        s_addop;
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   assign s_fracta_i = fracta_i;
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   assign s_fractb_i = fractb_i;
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   assign s_signa_i  = signa_i;
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   assign s_signb_i  = signb_i;
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   assign s_fpu_op_i = fpu_op_i;
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   always @(posedge clk_i)
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     begin
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        fract_o <= s_fract_o;
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        sign_o <= s_sign_o;
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     end
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   assign fracta_gt_fractb = s_fracta_i > s_fractb_i;
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   // check if its a subtraction or an addition operation
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   assign s_addop = ((s_signa_i ^ s_signb_i) & !s_fpu_op_i) |
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                    ((s_signa_i ^~ s_signb_i) & s_fpu_op_i);
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   // sign of result
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   assign s_sign_o = ((s_fract_o == 28'd0) & !(s_signa_i & s_signb_i)) ? 0 :
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                     (!s_signa_i & (!fracta_gt_fractb & (fpu_op_i^s_signb_i)))|
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                     (s_signa_i & (fracta_gt_fractb | (fpu_op_i^s_signb_i)));
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   // add/substract
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   assign s_fract_o = s_addop ?
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                      (fracta_gt_fractb ? s_fracta_i - s_fractb_i :
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                       s_fractb_i - s_fracta_i) :
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                      s_fracta_i + s_fractb_i;
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endmodule // or1200_fpu_addsub
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