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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_fcmp.v] - Blame information for rev 708

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1 258 julius
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  or1200_fpu_fcmp                                            ////
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////  Single precision Floating Point Compare Unit               ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module or1200_fpu_fcmp(opa, opb, unordered, altb, blta, aeqb, inf, zero);
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input   [31:0]   opa, opb;
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output          unordered;
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output          altb, blta, aeqb;
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output          inf, zero;
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////////////////////////////////////////////////////////////////////////
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//
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// Local Wire
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//
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reg             altb, blta, aeqb;
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wire            signa, signb;
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wire    [7:0]    expa, expb;
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wire    [22:0]   fracta, fractb;
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wire            expa_ff, expb_ff, fracta_00, fractb_00;
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wire            qnan_a, snan_a, qnan_b, snan_b, opa_inf, opb_inf, inf;
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wire            qnan, snan, opa_zero, opb_zero;
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wire            exp_eq, exp_gt, exp_lt;
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wire            fract_eq, fract_gt, fract_lt;
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wire            all_zero;
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////////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign  signa = opa[31];
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assign  signb = opb[31];
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assign   expa = opa[30:23];
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assign   expb = opb[30:23];
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assign fracta = opa[22:0];
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assign fractb = opb[22:0];
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////////////////////////////////////////////////////////////////////////
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//
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// Exception Logic
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//
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assign expa_ff = &expa;
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assign expb_ff = &expb;
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assign fracta_00 = !(|fracta);
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assign fractb_00 = !(|fractb);
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assign qnan_a =  fracta[22];
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assign snan_a = !fracta[22] & |fracta[21:0];
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assign qnan_b =  fractb[22];
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assign snan_b = !fractb[22] & |fractb[21:0];
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assign opa_inf = (expa_ff & fracta_00);
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assign opb_inf = (expb_ff & fractb_00);
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assign inf  = opa_inf | opb_inf;
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assign qnan = (expa_ff & qnan_a) | (expb_ff & qnan_b);
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assign snan = (expa_ff & snan_a) | (expb_ff & snan_b);
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assign unordered = qnan | snan;
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assign opa_zero = !(|expa) & fracta_00;
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assign opb_zero = !(|expb) & fractb_00;
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assign zero = opa_zero;
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////////////////////////////////////////////////////////////////////////
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//
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// Comparison Logic
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//
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assign exp_eq = expa == expb;
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assign exp_gt = expa  > expb;
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assign exp_lt = expa  < expb;
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assign fract_eq = fracta == fractb;
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assign fract_gt = fracta  > fractb;
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assign fract_lt = fracta  < fractb;
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assign all_zero = opa_zero & opb_zero;
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always @( qnan or snan or opa_inf or opb_inf or signa or signb or exp_eq or exp_gt or
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        exp_lt or fract_eq or fract_gt or fract_lt or all_zero)
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        casez( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero})
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           //13'b??_??_??_???_???_?: {altb, blta, aeqb} = 3'b000;
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           13'b1?_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // qnan
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           13'b?1_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // snan
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           13'b00_11_00_???_???_?: {altb, blta, aeqb} = 3'b001; // both op INF comparisson
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           13'b00_11_01_???_???_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_11_10_???_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_11_11_???_???_?: {altb, blta, aeqb} = 3'b001;
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           13'b00_10_00_???_???_?: {altb, blta, aeqb} = 3'b100; // opa INF comparisson
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           13'b00_10_01_???_???_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_10_10_???_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_10_11_???_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_01_00_???_???_?: {altb, blta, aeqb} = 3'b010; // opb INF comparisson
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           13'b00_01_01_???_???_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_01_10_???_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_01_11_???_???_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_00_10_???_???_0: {altb, blta, aeqb} = 3'b010; //compare base on sign
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           13'b00_00_01_???_???_0: {altb, blta, aeqb} = 3'b100; //compare base on sign
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           13'b00_00_??_???_???_1: {altb, blta, aeqb} = 3'b001; //compare base on sign both are zero
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           13'b00_00_00_010_???_?: {altb, blta, aeqb} = 3'b100; // cmp exp, equal sign
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           13'b00_00_00_001_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_00_11_010_???_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_00_11_001_???_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_00_00_100_010_?: {altb, blta, aeqb} = 3'b100; // compare fractions, equal sign, equal exp
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           13'b00_00_00_100_001_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_00_11_100_010_?: {altb, blta, aeqb} = 3'b010;
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           13'b00_00_11_100_001_?: {altb, blta, aeqb} = 3'b100;
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           13'b00_00_00_100_100_?: {altb, blta, aeqb} = 3'b001;
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           13'b00_00_11_100_100_?: {altb, blta, aeqb} = 3'b001;
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           default: {altb, blta, aeqb} = 3'bxxx;
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        endcase
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endmodule // or1200_fpu_fcmp
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