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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_mul.v] - Blame information for rev 589

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1 258 julius 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  or1200_fpu_mul                                              ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Serial multiplication entity for the multiplication unit    ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Original design (FPU100) -                            ////
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////        Jidan Al-eryani, jidan@gmx.net                        ////
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////      - Conv. to Verilog and inclusion in OR1200 -            ////
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////        Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//  Copyright (C) 2006, 2010
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//
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//      This source file may be used and distributed without
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//      restriction provided that this copyright statement is not
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//      removed from the file and that any derivative work contains
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//      the original copyright notice and the associated disclaimer.
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//
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//              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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//      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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//      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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//      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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//      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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//      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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//      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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//      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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//      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
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//      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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//      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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//      POSSIBILITY OF SUCH DAMAGE.
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//
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module or1200_fpu_mul
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(
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   clk_i,
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   fracta_i,
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   fractb_i,
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   signa_i,
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   signb_i,
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   start_i,
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   fract_o,
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   sign_o,
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   ready_o
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   );
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   parameter FP_WIDTH = 32;
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   parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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   parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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   parameter FRAC_WIDTH = 23;
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   parameter EXP_WIDTH = 8;
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   parameter ZERO_VECTOR = 31'd0;
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   parameter INF = 31'b1111111100000000000000000000000;
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   parameter QNAN = 31'b1111111110000000000000000000000;
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   parameter SNAN = 31'b1111111100000000000000000000001;
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   input clk_i;
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   input [FRAC_WIDTH:0] fracta_i;
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   input [FRAC_WIDTH:0] fractb_i;
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   input                signa_i;
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   input                signb_i;
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   input                start_i;
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   output reg [2*FRAC_WIDTH+1:0] fract_o;
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   output reg                sign_o;
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   output reg                ready_o;
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   parameter t_state_waiting = 1'b0,
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               t_state_busy = 1'b1;
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   reg [47:0]                 s_fract_o;
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   reg [23:0]                 s_fracta_i;
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   reg [23:0]                 s_fractb_i;
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   reg                       s_signa_i, s_signb_i;
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   wire                      s_sign_o;
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   reg                       s_start_i;
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   reg                       s_ready_o;
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   reg                       s_state;
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   reg [4:0]                  s_count;
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   wire [23:0]                s_tem_prod;
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   // Input Register
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   always @(posedge clk_i)
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     begin
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        s_fracta_i <= fracta_i;
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        s_fractb_i <= fractb_i;
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        s_signa_i<= signa_i;
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        s_signb_i<= signb_i;
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        s_start_i <= start_i;
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     end
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   // Output Register
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   always @(posedge clk_i)
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     begin
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        fract_o <= s_fract_o;
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        sign_o <= s_sign_o;
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        ready_o <= s_ready_o;
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     end
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   assign s_sign_o = signa_i ^ signb_i;
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   // FSM
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   always @(posedge clk_i)
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     if (s_start_i)
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       begin
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          s_state <= t_state_busy;
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          s_count <= 0;
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       end
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     else if (s_count==23)
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       begin
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          s_state <= t_state_waiting;
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          s_ready_o <= 1;
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          s_count <=0;
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       end
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     else if (s_state==t_state_busy)
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       s_count <= s_count + 1;
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     else
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       begin
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          s_state <= t_state_waiting;
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          s_ready_o <= 0;
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       end
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   assign s_tem_prod[0] = s_fracta_i[0] & s_fractb_i[s_count];
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   assign s_tem_prod[1] = s_fracta_i[1] & s_fractb_i[s_count];
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   assign s_tem_prod[2] = s_fracta_i[2] & s_fractb_i[s_count];
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   assign s_tem_prod[3] = s_fracta_i[3] & s_fractb_i[s_count];
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   assign s_tem_prod[4] = s_fracta_i[4] & s_fractb_i[s_count];
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   assign s_tem_prod[5] = s_fracta_i[5] & s_fractb_i[s_count];
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   assign s_tem_prod[6] = s_fracta_i[6] & s_fractb_i[s_count];
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   assign s_tem_prod[7] = s_fracta_i[7] & s_fractb_i[s_count];
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   assign s_tem_prod[8] = s_fracta_i[8] & s_fractb_i[s_count];
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   assign s_tem_prod[9] = s_fracta_i[9] & s_fractb_i[s_count];
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   assign s_tem_prod[10] = s_fracta_i[10] & s_fractb_i[s_count];
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   assign s_tem_prod[11] = s_fracta_i[11] & s_fractb_i[s_count];
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   assign s_tem_prod[12] = s_fracta_i[12] & s_fractb_i[s_count];
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   assign s_tem_prod[13] = s_fracta_i[13] & s_fractb_i[s_count];
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   assign s_tem_prod[14] = s_fracta_i[14] & s_fractb_i[s_count];
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   assign s_tem_prod[15] = s_fracta_i[15] & s_fractb_i[s_count];
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   assign s_tem_prod[16] = s_fracta_i[16] & s_fractb_i[s_count];
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   assign s_tem_prod[17] = s_fracta_i[17] & s_fractb_i[s_count];
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   assign s_tem_prod[18] = s_fracta_i[18] & s_fractb_i[s_count];
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   assign s_tem_prod[19] = s_fracta_i[19] & s_fractb_i[s_count];
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   assign s_tem_prod[20] = s_fracta_i[20] & s_fractb_i[s_count];
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   assign s_tem_prod[21] = s_fracta_i[21] & s_fractb_i[s_count];
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   assign s_tem_prod[22] = s_fracta_i[22] & s_fractb_i[s_count];
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   assign s_tem_prod[23] = s_fracta_i[23] & s_fractb_i[s_count];
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   wire [47:0] v_prod_shl;
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   assign v_prod_shl = {24'd0,s_tem_prod} << s_count[4:0];
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   always @(posedge clk_i)
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     if (s_state==t_state_busy)
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       begin
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          if (|s_count)
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            s_fract_o <= v_prod_shl + s_fract_o;
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          else
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            s_fract_o <= v_prod_shl;
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       end
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endmodule // or1200_fpu_mul
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